drivers/intel/fsp1_1: fix linking romstage when SEPARATE_VERSTAGE used

The skylake-based Chromebooks use a separate verstage which runs
just after bootblock and prior to romstage. However, that
config is not enabled for coreboot.org so when
C_ENVIRONMENT_BOOTBLOCK changes were done it wasn't observed
that the Chromebook config failed because 2 _start symbols
were present. Remedy this failure by using the common
car_stage_entry symbol for taking over control flow.

Change-Id: I3f29b90ba8e3786b2106a34e49e6d1f9831dcc7c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14549
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>

src/drivers/intel/fsp1_1/romstage_after_verstage.S

@@ -16,18 +16,8 @@
 #define LHLT_DELAY	0x50000		/* I/O delay between post codes on failure */
 
 .text
-.global _start
-_start:
-	/* This is the romstage entry point when CONFIG_SEPARATE_VERSTAGE
-	 * is used. The stack, descriptors, and gdt are already initialized
-	 * by verstage. However, in order to maintain the semantics of
-	 * CAR_GLOBAL variables we need to clear those to zero. */
-	cld
-	xor	%eax, %eax
-	movl	$(_car_global_end), %ecx
-	movl	$(_car_global_start), %edi
-	sub	%edi, %ecx
-	rep	stosl
+.global car_stage_entry
+car_stage_entry:
 	call	romstage_after_verstage
 	#include "after_raminit.S"