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This patch cleans up and clarifies Geode source code comments.

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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones
2007-05-10 23:22:27 +00:00
committed by Stefan Reinauer
parent 03625f4daf
commit ddf845f620
7 changed files with 153 additions and 166 deletions
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6
src/southbridge/amd/cs5536/cs5536.c
View File

@@ -131,14 +131,12 @@ static void pmChipsetInit(void)
/* PM_SED */
port = (PMS_IO_BASE + 0x014);
/* mov eax, 0x057642 ; 100ms, works*/
val = 0x04601; /* 5ms */
val = 0x04601; /* 5ms, # of 3.57954MHz clock edges */
outl(val, port);
/* PM_SIDD */
port = (PMS_IO_BASE + 0x020);
/* mov eax, 0x0AEC84 ; 200ms, works*/
val = 0x08C02; /* 10ms */
val = 0x08C02; /* 10ms, # of 3.57954MHz clock edges */
outl(val, port);
}

8
src/southbridge/amd/cs5536/cs5536_early_setup.c
View File

@@ -97,10 +97,10 @@ static void cs5536_setup_power_button(void)
/* Power Button Setup */
outl(0x40020000, PMS_IO_BASE + 0x40);
/* setup GPIO24, it is the external signal for 5536 vsb_work_aux
* which controls all voltage rails except Vstandby & Vmem.
/* setup WORK_AUX/GPIO24, it is the external signal for 5536
* vsb_work_aux controls all voltage rails except Vstandby & Vmem.
* We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
* If GPIO24 is not enabled then soft-off will not work.
* If WORK_AUX/GPIO24 is not enabled then soft-off will not work.
*/
outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
@@ -127,7 +127,7 @@ static void cs5536_disable_internal_uart(void)
{
msr_t msr;
/* The UARTs default to enabled.
* Disable and reset them and configure them later. (SIO init)
* Disable and reset them and configure them later. (SIO init)
*/
msr = rdmsr(MDD_UART1_CONF);
msr.lo = 1; // reset