This patch cleans up and clarifies Geode source code comments.
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones
Stefan Reinauer
parent
03625f4daf
commit
ddf845f620
@ -101,11 +101,6 @@ void SetDelayControl(void)
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;1 16 400MHz 0x82*10055 0x56960004 4
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;
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;2 4,4 400MHz 0x82710000 0x56960004 4
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;2 8,8 400MHz 0xC27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
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;
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;2 16,4 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
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;2 16,8 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
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;2 16,16 >333 0xB2710000 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
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;
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;1 4 <=333MHz 0x83*100FF 0x56960004 3
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;1 8 <=333MHz 0x83*100AA 0x56960004 3
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@ -114,9 +109,6 @@ void SetDelayControl(void)
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;2 4,4 <=333MHz 0x837100A5 0x56960004 3
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;2 8,8 <=333MHz 0x937100A5 0x56960004 3
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;
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;2 16,4 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE ***
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;2 16,8 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE ***
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;2 16,16 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE ***
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;=========================================================================
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;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0,
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; but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1.
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@ -130,9 +122,9 @@ void SetDelayControl(void)
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; DIMM Max MBUS
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;DIMMs devices Frequency MCP 0x4C00000F Setting
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;----- ------- --------- ----------------------
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;1 4 400MHz 0xF2F100FF 0x56960004 4 The MC changes improve Salsa.
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;1 8 400MHz 0xF2F100FF 0x56960004 4 Delay controls no real change,
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;1 4 <=333MHz 0xF2F100FF 0x56960004 3 just fixing typo in left side.
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;1 4 400MHz 0xF2F100FF 0x56960004 4 The No VTT changes improve timing.
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;1 8 400MHz 0xF2F100FF 0x56960004 4
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;1 4 <=333MHz 0xF2F100FF 0x56960004 3
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;1 8 <=333MHz 0xF2F100FF 0x56960004 3
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;1 16 <=333MHz 0xF2F100FF 0x56960004 3
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*/
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@ -233,8 +225,8 @@ void cpuRegInit(void)
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wrmsr(msrnum, msr);
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/*
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; Castle performance setting.
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; Enable Quack for fewer re-RAS on the MC
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* LX performance setting.
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* Enable Quack for fewer re-RAS on the MC
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*/
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msrnum = GLIU0_ARB;
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msr = rdmsr(msrnum);
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@ -290,8 +290,7 @@ void do_vsmbios(void)
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/* this is the base of rom on the LX at present. At some point, this has to be
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* much better parameterized
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*/
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/* the VSA starts at the base of rom - 64 */
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//rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024);
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//VSA is cat onto the end after LB builds
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rom = ((unsigned long)0) - (ROM_SIZE + 36 * 1024);
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buf = (unsigned char *)VSA2_BUFFER;
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@ -19,178 +19,178 @@
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/* standard AMD post definitions -- might as well use them. */
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#define POST_Output_Port (0x080) /* port to write post codes to*/
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#define POST_preSioInit (0x000) /* geode.asm*/
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#define POST_clockInit (0x001) /* geode.asm*/
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#define POST_CPURegInit (0x002) /* geode.asm*/
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#define POST_UNREAL (0x003) /* geode.asm*/
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#define POST_CPUMemRegInit (0x004) /* geode.asm*/
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#define POST_CPUTest (0x005) /* geode.asm*/
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#define POST_memSetup (0x006) /* geode.asm*/
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#define POST_memSetUpStack (0x007) /* geode.asm*/
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#define POST_memTest (0x008) /* geode.asm*/
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#define POST_shadowRom (0x009) /* geode.asm*/
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#define POST_memRAMoptimize (0x00A) /* geode.asm*/
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#define POST_cacheInit (0x00B) /* geode.asm*/
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#define POST_northBridgeInit (0x00C) /* geode.asm*/
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#define POST_chipsetInit (0x00D) /* geode.asm*/
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#define POST_sioTest (0x00E) /* geode.asm*/
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#define POST_pcATjunk (0x00F) /* geode.asm*/
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#define POST_preSioInit (0x000)
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#define POST_clockInit (0x001)
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#define POST_CPURegInit (0x002)
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#define POST_UNREAL (0x003)
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#define POST_CPUMemRegInit (0x004)
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#define POST_CPUTest (0x005)
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#define POST_memSetup (0x006)
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#define POST_memSetUpStack (0x007)
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#define POST_memTest (0x008)
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#define POST_shadowRom (0x009)
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#define POST_memRAMoptimize (0x00A)
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#define POST_cacheInit (0x00B)
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#define POST_northBridgeInit (0x00C)
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#define POST_chipsetInit (0x00D)
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#define POST_sioTest (0x00E)
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#define POST_pcATjunk (0x00F)
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#define POST_intTable (0x010) /* geode.asm*/
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#define POST_memInfo (0x011) /* geode.asm*/
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#define POST_romCopy (0x012) /* geode.asm*/
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#define POST_PLLCheck (0x013) /* geode.asm*/
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#define POST_keyboardInit (0x014) /* geode.asm*/
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#define POST_cpuCacheOff (0x015) /* geode.asm*/
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#define POST_BDAInit (0x016) /* geode.asm*/
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#define POST_pciScan (0x017) /* geode.asm*/
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#define POST_optionRomInit (0x018) /* geode.asm*/
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#define POST_ResetLimits (0x019) /* geode.asm*/
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#define POST_summary_screen (0x01A) /* geode.asm*/
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#define POST_Boot (0x01B) /* geode.asm*/
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#define POST_SystemPreInit (0x01C) /* geode.asm*/
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#define POST_ClearRebootFlag (0x01D) /* geode.asm*/
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#define POST_GLIUInit (0x01E) /* geode.asm*/
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#define POST_BootFailed (0x01F) /* geode.asm*/
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#define POST_intTable (0x010)
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#define POST_memInfo (0x011)
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#define POST_romCopy (0x012)
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#define POST_PLLCheck (0x013)
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#define POST_keyboardInit (0x014)
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#define POST_cpuCacheOff (0x015)
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#define POST_BDAInit (0x016)
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#define POST_pciScan (0x017)
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#define POST_optionRomInit (0x018)
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#define POST_ResetLimits (0x019)
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#define POST_summary_screen (0x01A)
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#define POST_Boot (0x01B)
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#define POST_SystemPreInit (0x01C)
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#define POST_ClearRebootFlag (0x01D)
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#define POST_GLIUInit (0x01E)
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#define POST_BootFailed (0x01F)
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#define POST_CPU_ID (0x020) /* cpucpuid.asm*/
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#define POST_COUNTERBROKEN (0x021) /* pllinit.asm*/
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#define POST_DIFF_DIMMS (0x022) /* pllinit.asm*/
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#define POST_WIGGLE_MEM_LINES (0x023) /* pllinit.asm*/
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#define POST_NO_GLIU_DESC (0x024) /* pllinit.asm*/
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#define POST_CPU_LCD_CHECK (0x025) /* pllinit.asm*/
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#define POST_CPU_LCD_PASS (0x026) /* pllinit.asm*/
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#define POST_CPU_LCD_FAIL (0x027) /* pllinit.asm*/
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#define POST_CPU_STEPPING (0x028) /* cpucpuid.asm*/
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#define POST_CPU_DM_BIST_FAILURE (0x029) /* gx2reg.asm*/
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#define POST_CPU_FLAGS (0x02A) /* cpucpuid.asm*/
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#define POST_CHIPSET_ID (0x02b) /* chipset.asm*/
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#define POST_CHIPSET_ID_PASS (0x02c) /* chipset.asm*/
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#define POST_CHIPSET_ID_FAIL (0x02d) /* chipset.asm*/
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#define POST_CPU_ID_GOOD (0x02E) /* cpucpuid.asm*/
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#define POST_CPU_ID_FAIL (0x02F) /* cpucpuid.asm*/
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#define POST_CPU_ID (0x020)
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#define POST_COUNTERBROKEN (0x021)
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#define POST_DIFF_DIMMS (0x022)
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#define POST_WIGGLE_MEM_LINES (0x023)
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#define POST_NO_GLIU_DESC (0x024)
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#define POST_CPU_LCD_CHECK (0x025)
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#define POST_CPU_LCD_PASS (0x026)
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#define POST_CPU_LCD_FAIL (0x027)
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#define POST_CPU_STEPPING (0x028)
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#define POST_CPU_DM_BIST_FAILURE (0x029)
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#define POST_CPU_FLAGS (0x02A)
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#define POST_CHIPSET_ID (0x02b)
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#define POST_CHIPSET_ID_PASS (0x02c)
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#define POST_CHIPSET_ID_FAIL (0x02d)
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#define POST_CPU_ID_GOOD (0x02E)
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#define POST_CPU_ID_FAIL (0x02F)
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/* PCI config*/
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#define P80_PCICFG (0x030) /* pcispace.asm*/
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#define P80_PCICFG (0x030)
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/* PCI io*/
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#define P80_PCIIO (0x040) /* pcispace.asm*/
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#define P80_PCIIO (0x040)
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/* PCI memory*/
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#define P80_PCIMEM (0x050) /* pcispace.asm*/
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#define P80_PCIMEM (0x050)
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/* SIO*/
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#define P80_SIO (0x060) /* *sio.asm*/
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#define P80_SIO (0x060)
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/* Memory Setp*/
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#define P80_MEM_SETUP (0x070) /* docboot meminit*/
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#define POST_MEM_SETUP (0x070) /* memsize.asm*/
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#define ERROR_32BIT_DIMMS (0x071) /* memsize.asm*/
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#define POST_MEM_SETUP2 (0x072) /* memsize.asm*/
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#define POST_MEM_SETUP3 (0x073) /* memsize.asm*/
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#define POST_MEM_SETUP4 (0x074) /* memsize.asm*/
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#define POST_MEM_SETUP5 (0x075) /* memsize.asm*/
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#define POST_MEM_ENABLE (0x076) /* memsize.asm*/
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#define ERROR_NO_DIMMS (0x077) /* memsize.asm*/
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#define ERROR_DIFF_DIMMS (0x078) /* memsize.asm*/
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#define ERROR_BAD_LATENCY (0x079) /* memsize.asm*/
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#define ERROR_SET_PAGE (0x07a) /* memsize.asm*/
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#define ERROR_DENSITY_DIMM (0x07b) /* memsize.asm*/
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#define ERROR_UNSUPPORTED_DIMM (0x07c) /* memsize.asm*/
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#define ERROR_BANK_SET (0x07d) /* memsize.asm*/
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#define POST_MEM_SETUP_GOOD (0x07E) /* memsize.asm*/
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#define POST_MEM_SETUP_FAIL (0x07F) /* memsize.asm*/
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#define P80_MEM_SETUP (0x070)
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#define POST_MEM_SETUP (0x070)
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#define ERROR_32BIT_DIMMS (0x071)
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#define POST_MEM_SETUP2 (0x072)
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#define POST_MEM_SETUP3 (0x073)
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#define POST_MEM_SETUP4 (0x074)
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#define POST_MEM_SETUP5 (0x075)
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#define POST_MEM_ENABLE (0x076)
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#define ERROR_NO_DIMMS (0x077)
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#define ERROR_DIFF_DIMMS (0x078)
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#define ERROR_BAD_LATENCY (0x079)
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#define ERROR_SET_PAGE (0x07a)
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#define ERROR_DENSITY_DIMM (0x07b)
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#define ERROR_UNSUPPORTED_DIMM (0x07c)
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#define ERROR_BANK_SET (0x07d)
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#define POST_MEM_SETUP_GOOD (0x07E)
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#define POST_MEM_SETUP_FAIL (0x07F)
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#define POST_UserPreInit (0x080) /* geode.asm*/
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#define POST_UserPostInit (0x081) /* geode.asm*/
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#define POST_Equipment_check (0x082) /* geode.asm*/
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#define POST_InitNVRAMBX (0x083) /* geode.asm*/
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#define POST_NoPIRTable (0x084) /* pci.asm*/
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#define POST_ChipsetFingerPrintPass (0x085) /* prechipsetinit*/
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#define POST_ChipsetFingerPrintFail (0x086) /* prechipsetinit*/
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#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) /* gx2reg.asm*/
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#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) /* gx2reg.asm*/
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#define POST_CPU_FPU_BIST_FAILURE (0x089) /* gx2reg.asm*/
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#define POST_CPU_BTB_BIST_FAILURE (0x08a) /* gx2reg.asm*/
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#define POST_CPU_EX_BIST_FAILURE (0x08b) /* gx2reg.asm*/
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#define POST_Chipset_PI_Test_Fail (0x08c) /* prechipsetinit*/
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#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) /* prechipsetinit*/
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#define POST_BIT_CLK_Fail (0x08e) /* Hawk geode.asm override*/
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#define POST_UserPreInit (0x080)
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#define POST_UserPostInit (0x081)
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#define POST_Equipment_check (0x082)
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#define POST_InitNVRAMBX (0x083)
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#define POST_NoPIRTable (0x084)
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#define POST_ChipsetFingerPrintPass (0x085)
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#define POST_ChipsetFingerPrintFail (0x086)
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#define POST_CPU_IM_TAG_BIST_FAILURE (0x087)
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#define POST_CPU_IM_DATA_BIST_FAILURE (0x088)
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#define POST_CPU_FPU_BIST_FAILURE (0x089)
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#define POST_CPU_BTB_BIST_FAILURE (0x08a)
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#define POST_CPU_EX_BIST_FAILURE (0x08b)
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#define POST_Chipset_PI_Test_Fail (0x08c)
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#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d)
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#define POST_BIT_CLK_Fail (0x08e)
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#define POST_STACK_SETUP (0x090) /* memstack.asm*/
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#define POST_CPU_PF_BIST_FAILURE (0x091) /* gx2reg.asm*/
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#define POST_CPU_L2_BIST_FAILURE (0x092) /* gx2reg.asm*/
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#define POST_CPU_GLCP_BIST_FAILURE (0x093) /* gx2reg.asm*/
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#define POST_CPU_DF_BIST_FAILURE (0x094) /* gx2reg.asm*/
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#define POST_CPU_VG_BIST_FAILURE (0x095) /* gx2reg.asm*/
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#define POST_CPU_VIP_BIST_FAILURE (0x096) /* gx2reg.asm*/
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#define POST_STACK_SETUP_PASS (0x09E) /* memstack.asm*/
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#define POST_STACK_SETUP_FAIL (0x09F) /* memstack.asm*/
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#define POST_STACK_SETUP (0x090)
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#define POST_CPU_PF_BIST_FAILURE (0x091)
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#define POST_CPU_L2_BIST_FAILURE (0x092)
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#define POST_CPU_GLCP_BIST_FAILURE (0x093)
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#define POST_CPU_DF_BIST_FAILURE (0x094)
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#define POST_CPU_VG_BIST_FAILURE (0x095)
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#define POST_CPU_VIP_BIST_FAILURE (0x096)
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#define POST_STACK_SETUP_PASS (0x09E)
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#define POST_STACK_SETUP_FAIL (0x09F)
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#define POST_PLL_INIT (0x0A0) /* pllinit.asm*/
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#define POST_PLL_MANUAL (0x0A1) /* pllinit.asm*/
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#define POST_PLL_STRAP (0x0A2) /* pllinit.asm*/
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#define POST_PLL_RESET_FAIL (0x0A3) /* pllinit.asm*/
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#define POST_PLL_PCI_FAIL (0x0A4) /* pllinit.asm*/
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#define POST_PLL_MEM_FAIL (0x0A5) /* pllinit.asm*/
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#define POST_PLL_CPU_VER_FAIL (0x0A6) /* pllinit.asm*/
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#define POST_PLL_INIT (0x0A0)
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#define POST_PLL_MANUAL (0x0A1)
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#define POST_PLL_STRAP (0x0A2)
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#define POST_PLL_RESET_FAIL (0x0A3)
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#define POST_PLL_PCI_FAIL (0x0A4)
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#define POST_PLL_MEM_FAIL (0x0A5)
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#define POST_PLL_CPU_VER_FAIL (0x0A6)
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#define POST_MEM_TESTMEM (0x0B0) /* memtest.asm*/
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#define POST_MEM_TESTMEM1 (0x0B1) /* memtest.asm*/
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#define POST_MEM_TESTMEM2 (0x0B2) /* memtest.asm*/
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#define POST_MEM_TESTMEM3 (0x0B3) /* memtest.asm*/
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#define POST_MEM_TESTMEM4 (0x0B4) /* memtest.asm*/
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#define POST_MEM_TESTMEM_PASS (0x0BE) /* memtest.asm*/
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#define POST_MEM_TESTMEM_FAIL (0x0BF) /* memtest.asm*/
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#define POST_MEM_TESTMEM (0x0B0)
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#define POST_MEM_TESTMEM1 (0x0B1)
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#define POST_MEM_TESTMEM2 (0x0B2)
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#define POST_MEM_TESTMEM3 (0x0B3)
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#define POST_MEM_TESTMEM4 (0x0B4)
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#define POST_MEM_TESTMEM_PASS (0x0BE)
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#define POST_MEM_TESTMEM_FAIL (0x0BF)
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#define POST_SECUROM_SECBOOT_START (0x0C0) /* secstart.asm*/
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#define POST_SECUROM_BOOTSRCSETUP (0x0C1) /* secstart.asm*/
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#define POST_SECUROM_REMAP_FAIL (0x0C2) /* secstart.asm*/
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#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) /* secstart.asm*/
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#define POST_SECUROM_DCACHESETUP (0x0C4) /* secstart.asm*/
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#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) /* secstart.asm*/
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#define POST_SECUROM_ICACHESETUP (0x0C6) /* secstart.asm*/
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#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) /* secstart.asm*/
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#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) /* secstart.asm*/
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#define POST_SECUROM_PLATFORMSETUP (0x0C9) /* secstart.asm*/
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#define POST_SECUROM_SIGCHECKBIOS (0x0CA) /* secstart.asm*/
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#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) /* secstart.asm*/
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#define POST_SECUROM_PASS (0x0CC) /* secstart.asm*/
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#define POST_SECUROM_FAIL (0x0CD) /* secstart.asm*/
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#define POST_SECUROM_SECBOOT_START (0x0C0)
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#define POST_SECUROM_BOOTSRCSETUP (0x0C1)
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#define POST_SECUROM_REMAP_FAIL (0x0C2)
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#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3)
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#define POST_SECUROM_DCACHESETUP (0x0C4)
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||||
#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5)
|
||||
#define POST_SECUROM_ICACHESETUP (0x0C6)
|
||||
#define POST_SECUROM_DESCRIPTORSETUP (0x0C7)
|
||||
#define POST_SECUROM_DCACHESETUPBIOS (0x0C8)
|
||||
#define POST_SECUROM_PLATFORMSETUP (0x0C9)
|
||||
#define POST_SECUROM_SIGCHECKBIOS (0x0CA)
|
||||
#define POST_SECUROM_ICACHESETUPBIOS (0x0CB)
|
||||
#define POST_SECUROM_PASS (0x0CC)
|
||||
#define POST_SECUROM_FAIL (0x0CD)
|
||||
|
||||
#define POST_RCONFInitError (0x0CE) /* cache.asm*/
|
||||
#define POST_CacheInitError (0x0CF) /* cache.asm*/
|
||||
#define POST_RCONFInitError (0x0CE)
|
||||
#define POST_CacheInitError (0x0CF)
|
||||
|
||||
|
||||
#define POST_ROM_PREUNCOMPRESS (0x0D0) /* rominit.asm*/
|
||||
#define POST_ROM_UNCOMPRESS (0x0D1) /* rominit.asm*/
|
||||
#define POST_ROM_SMM_INIT (0x0D2) /* rominit.asm*/
|
||||
#define POST_ROM_VID_BIOS (0x0D3) /* rominit.asm*/
|
||||
#define POST_ROM_LCDINIT (0x0D4) /* rominit.asm*/
|
||||
#define POST_ROM_SPLASH (0x0D5) /* rominit.asm*/
|
||||
#define POST_ROM_HDDINIT (0x0D6) /* rominit.asm*/
|
||||
#define POST_ROM_SYS_INIT (0x0D7) /* rominit.asm*/
|
||||
#define POST_ROM_DMM_INIT (0x0D8) /* rominit.asm*/
|
||||
#define POST_ROM_TVINIT (0x0D9) /* rominit.asm*/
|
||||
#define POST_ROM_PREUNCOMPRESS (0x0D0)
|
||||
#define POST_ROM_UNCOMPRESS (0x0D1)
|
||||
#define POST_ROM_SMM_INIT (0x0D2)
|
||||
#define POST_ROM_VID_BIOS (0x0D3)
|
||||
#define POST_ROM_LCDINIT (0x0D4)
|
||||
#define POST_ROM_SPLASH (0x0D5)
|
||||
#define POST_ROM_HDDINIT (0x0D6)
|
||||
#define POST_ROM_SYS_INIT (0x0D7)
|
||||
#define POST_ROM_DMM_INIT (0x0D8)
|
||||
#define POST_ROM_TVINIT (0x0D9)
|
||||
#define POST_ROM_POSTUNCOMPRESS (0x0DE)
|
||||
|
||||
|
||||
#define P80_CHIPSET_INIT (0x0E0) /* chipset.asm*/
|
||||
#define POST_PreChipsetInit (0x0E1) /* geode.asm*/
|
||||
#define POST_LateChipsetInit (0x0E2) /* geode.asm*/
|
||||
#define POST_NORTHB_INIT (0x0E8) /* northb.asm*/
|
||||
#define P80_CHIPSET_INIT (0x0E0)
|
||||
#define POST_PreChipsetInit (0x0E1)
|
||||
#define POST_LateChipsetInit (0x0E2)
|
||||
#define POST_NORTHB_INIT (0x0E8)
|
||||
|
||||
|
||||
#define POST_INTR_SEG_JUMP (0x0F0) /* vector.asm*/
|
||||
#define POST_INTR_SEG_JUMP (0x0F0)
|
||||
|
||||
@ -476,8 +476,6 @@
|
||||
|
||||
/*
|
||||
* Write to a Virtual Register
|
||||
* AX = Class/Index
|
||||
* CX = data to write
|
||||
*/
|
||||
static inline void vrWrite(uint16_t wClassIndex, uint16_t wData)
|
||||
{
|
||||
@ -487,7 +485,6 @@ static inline void vrWrite(uint16_t wClassIndex, uint16_t wData)
|
||||
|
||||
/*
|
||||
* Read from a Virtual Register
|
||||
* AX = Class/Index
|
||||
* Returns a 16-bit word of data
|
||||
*/
|
||||
static inline uint16_t vrRead(uint16_t wClassIndex)
|
||||
|
||||
@ -127,6 +127,7 @@ int sizeram(void)
|
||||
int sizem = 0;
|
||||
unsigned short dimm;
|
||||
|
||||
/* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
|
||||
msr = rdmsr(MC_CF07_DATA);
|
||||
printk_debug("sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
|
||||
|
||||
@ -134,14 +135,14 @@ int sizeram(void)
|
||||
dimm = msr.hi;
|
||||
/* installed? */
|
||||
if ((dimm & 7) != 7) {
|
||||
sizem = 4 << ((dimm >> 12) & 0x0F);
|
||||
sizem = 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
|
||||
}
|
||||
|
||||
/* dimm 1 */
|
||||
dimm = msr.hi >> 16;
|
||||
/* installed? */
|
||||
if ((dimm & 7) != 7) {
|
||||
sizem += 4 << ((dimm >> 12) & 0x0F);
|
||||
sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
|
||||
}
|
||||
|
||||
printk_debug("sizeram: sizem 0x%xMB\n", sizem);
|
||||
|
||||
@ -131,14 +131,12 @@ static void pmChipsetInit(void)
|
||||
|
||||
/* PM_SED */
|
||||
port = (PMS_IO_BASE + 0x014);
|
||||
/* mov eax, 0x057642 ; 100ms, works*/
|
||||
val = 0x04601; /* 5ms */
|
||||
val = 0x04601; /* 5ms, # of 3.57954MHz clock edges */
|
||||
outl(val, port);
|
||||
|
||||
/* PM_SIDD */
|
||||
port = (PMS_IO_BASE + 0x020);
|
||||
/* mov eax, 0x0AEC84 ; 200ms, works*/
|
||||
val = 0x08C02; /* 10ms */
|
||||
val = 0x08C02; /* 10ms, # of 3.57954MHz clock edges */
|
||||
outl(val, port);
|
||||
}
|
||||
|
||||
|
||||
@ -97,10 +97,10 @@ static void cs5536_setup_power_button(void)
|
||||
/* Power Button Setup */
|
||||
outl(0x40020000, PMS_IO_BASE + 0x40);
|
||||
|
||||
/* setup GPIO24, it is the external signal for 5536 vsb_work_aux
|
||||
* which controls all voltage rails except Vstandby & Vmem.
|
||||
/* setup WORK_AUX/GPIO24, it is the external signal for 5536
|
||||
* vsb_work_aux controls all voltage rails except Vstandby & Vmem.
|
||||
* We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
|
||||
* If GPIO24 is not enabled then soft-off will not work.
|
||||
* If WORK_AUX/GPIO24 is not enabled then soft-off will not work.
|
||||
*/
|
||||
outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
|
||||
outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
|
||||
@ -127,7 +127,7 @@ static void cs5536_disable_internal_uart(void)
|
||||
{
|
||||
msr_t msr;
|
||||
/* The UARTs default to enabled.
|
||||
* Disable and reset them and configure them later. (SIO init)
|
||||
* Disable and reset them and configure them later. (SIO init)
|
||||
*/
|
||||
msr = rdmsr(MDD_UART1_CONF);
|
||||
msr.lo = 1; // reset
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user