- add support for socket 754
- fix configuration creation for amd solo (doesn't compile yet) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
3
src/cpu/amd/socket_754/Config.lb
Normal file
3
src/cpu/amd/socket_754/Config.lb
Normal file
@ -0,0 +1,3 @@
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config chip.h
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object socket_754.o
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dir /cpu/amd/model_fxx
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4
src/cpu/amd/socket_754/chip.h
Normal file
4
src/cpu/amd/socket_754/chip.h
Normal file
@ -0,0 +1,4 @@
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extern struct chip_operations cpu_amd_socket_754_ops;
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struct cpu_amd_socket_754_config {
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};
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7
src/cpu/amd/socket_754/socket_754.c
Normal file
7
src/cpu/amd/socket_754/socket_754.c
Normal file
@ -0,0 +1,7 @@
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#include <device/device.h>
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#include "chip.h"
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struct chip_operations cpu_amd_socket_754_ops = {
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.name = "socket 754",
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};
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@ -1,122 +1,3 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HARD_RESET_BUS
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uses HARD_RESET_DEVICE
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uses HARD_RESET_FUNCTION
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uses IRQ_SLOT_COUNT
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uses HAVE_OPTION_TABLE
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uses CONFIG_MAX_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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||||||
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE=262144
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###
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### Build options
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###
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=1
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default HARD_RESET_BUS=1
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default HARD_RESET_DEVICE=5
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default HARD_RESET_FUNCTION=0
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=8
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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default HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=1
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##
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## Move the default LinuxBIOS cmos range off of AMD RTC registers
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##
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default LB_CKS_RANGE_START=49
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default LB_CKS_RANGE_END=122
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default LB_CKS_LOC=123
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##
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## AMD Solo is a 1cpu board
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##
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default CONFIG_SMP=1
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default CONFIG_MAX_CPUS=1
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##
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## Build code to setup a generic IOAPIC
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##
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default CONFIG_IOAPIC=1
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##
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## Clean up the motherboard id strings
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##
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default MAINBOARD_PART_NUMBER="SOLO"
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default MAINBOARD_VENDOR="AMD"
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###
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### LinuxBIOS layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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##
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##
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## Compute the location and size of where this firmware image
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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@ -135,7 +16,6 @@ end
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##
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_STREAM = 1
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##
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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## Compute where this copy of linuxBIOS will start in the boot rom
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@ -152,12 +32,7 @@ default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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default XIP_ROM_SIZE=65536
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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arch i386 end
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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#cpu k8 end
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##
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##
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## Build the objects we have code for in this directory.
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## Build the objects we have code for in this directory.
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@ -166,12 +41,13 @@ arch i386 end
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driver mainboard.o
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driver mainboard.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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##
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##
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## Romcc output
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## Romcc output
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##
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##
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makerule ./failover.E
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c"
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depends "$(MAINBOARD)/failover.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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end
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end
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@ -180,11 +56,11 @@ makerule ./failover.inc
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
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end
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end
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makerule ./auto.E
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h "
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depends "$(MAINBOARD)/auto.c option_table.h "
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action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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end
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makerule ./auto.inc
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makerule ./auto.inc
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depends "./auto.E ./romcc"
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depends "./auto.E ./romcc"
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action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
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action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
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end
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end
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@ -192,21 +68,20 @@ end
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##
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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##
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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#mainboardinit cpu/i386/bist32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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ldscript /cpu/i386/entry32.lds
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##
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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##
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if USE_FALLBACK_IMAGE
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset16.inc
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/i386/reset16.lds
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ldscript /cpu/x86/16bit/reset16.lds
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else
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else
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mainboardinit cpu/i386/reset32.inc
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/i386/reset32.lds
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ldscript /cpu/x86/32bit/reset32.lds
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end
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end
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### Should this be in the northbridge code?
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### Should this be in the northbridge code?
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@ -218,18 +93,13 @@ mainboardinit arch/i386/lib/cpu_reset.inc
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mainboardinit arch/i386/lib/id.inc
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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ldscript /arch/i386/lib/id.lds
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||||||
##
|
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## Setup our mtrrs
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||||||
##
|
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||||||
mainboardinit cpu/k8/earlymtrr.inc
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|
||||||
|
|
||||||
###
|
###
|
||||||
### This is the early phase of linuxBIOS startup
|
### This is the early phase of linuxBIOS startup
|
||||||
### Things are delicate and we test to see if we should
|
### Things are delicate and we test to see if we should
|
||||||
### failover to another image.
|
### failover to another image.
|
||||||
###
|
###
|
||||||
if USE_FALLBACK_IMAGE
|
if USE_FALLBACK_IMAGE
|
||||||
ldscript /arch/i386/lib/failover.lds
|
ldscript /arch/i386/lib/failover.lds
|
||||||
mainboardinit ./failover.inc
|
mainboardinit ./failover.inc
|
||||||
end
|
end
|
||||||
|
|
||||||
@ -240,74 +110,107 @@ end
|
|||||||
##
|
##
|
||||||
## Setup RAM
|
## Setup RAM
|
||||||
##
|
##
|
||||||
mainboardinit cpu/k8/enable_mmx_sse.inc
|
mainboardinit cpu/x86/fpu/enable_fpu.inc
|
||||||
|
mainboardinit cpu/x86/mmx/enable_mmx.inc
|
||||||
|
mainboardinit cpu/x86/sse/enable_sse.inc
|
||||||
mainboardinit ./auto.inc
|
mainboardinit ./auto.inc
|
||||||
mainboardinit cpu/k8/disable_mmx_sse.inc
|
mainboardinit cpu/x86/sse/disable_sse.inc
|
||||||
|
mainboardinit cpu/x86/mmx/disable_mmx.inc
|
||||||
|
|
||||||
##
|
##
|
||||||
## Include the secondary Configuration files
|
## Include the secondary Configuration files
|
||||||
##
|
##
|
||||||
dir /pc80
|
dir /pc80
|
||||||
config chip.h
|
config chip.h
|
||||||
|
|
||||||
northbridge amd/amdk8 "mc0"
|
# sample config for arima/hdama
|
||||||
pci 0:18.0
|
chip northbridge/amd/amdk8
|
||||||
pci 0:18.0
|
device pci_domain 0 on
|
||||||
pci 0:18.0
|
device pci 18.0 on # northbridge
|
||||||
pci 0:18.1
|
# devices on link 0, link 0 == LDT 0
|
||||||
pci 0:18.2
|
chip southbridge/amd/amd8151
|
||||||
pci 0:18.3
|
# the on/off keyword is mandatory
|
||||||
southbridge amd/amd8151 "amd8151" link 0
|
device pci 0.0 on end
|
||||||
pci 0:0.0
|
device pci 1.0 on end
|
||||||
pci 0:1.0
|
end
|
||||||
end
|
chip southbridge/amd/amd8111
|
||||||
southbridge amd/amd8111 "amd8111" link 0
|
# this "device pci 0.0" is the parent the next one
|
||||||
pci 0:0.0
|
# PCI bridge
|
||||||
pci 0:1.0 on
|
device pci 0.0 on
|
||||||
pci 0:1.1 on
|
device pci 0.0 on end
|
||||||
pci 0:1.2 on
|
device pci 0.1 on end
|
||||||
pci 0:1.3 on
|
device pci 0.2 on end
|
||||||
pci 0:1.5 on
|
device pci 1.0 off end
|
||||||
pci 0:1.6 on
|
end
|
||||||
pci 1:0.0 on
|
device pci 1.0 on
|
||||||
pci 1:0.1 on
|
chip superio/NSC/pc87360
|
||||||
pci 1:0.2 on
|
device pnp 2e.0 off # Floppy
|
||||||
# pci 1:1.0 off
|
io 0x60 = 0x3f0
|
||||||
superio NSC/pc87360 link 1
|
irq 0x70 = 6
|
||||||
pnp 2e.0 off # Floppy
|
drq 0x74 = 2
|
||||||
io 0x60 = 0x3f0
|
end
|
||||||
irq 0x70 = 6
|
device pnp 2e.1 off # Parallel Port
|
||||||
drq 0x74 = 2
|
io 0x60 = 0x378
|
||||||
pnp 2e.1 off # Parallel Port
|
irq 0x70 = 7
|
||||||
io 0x60 = 0x378
|
end
|
||||||
irq 0x70 = 7
|
device pnp 2e.2 off # Com 2
|
||||||
pnp 2e.2 off # Com 2
|
io 0x60 = 0x2f8
|
||||||
io 0x60 = 0x2f8
|
irq 0x70 = 3
|
||||||
irq 0x70 = 3
|
end
|
||||||
pnp 2e.3 on # Com 1
|
device pnp 2e.3 on # Com 1
|
||||||
io 0x60 = 0x3f8
|
io 0x60 = 0x3f8
|
||||||
irq 0x70 = 4
|
irq 0x70 = 4
|
||||||
pnp 2e.4 off # SWC
|
end
|
||||||
pnp 2e.5 off # Mouse
|
device pnp 2e.4 off end # SWC
|
||||||
pnp 2e.6 on # Keyboard
|
device pnp 2e.5 off end # Mouse
|
||||||
io 0x60 = 0x60
|
device pnp 2e.6 on # Keyboard
|
||||||
io 0x62 = 0x64
|
io 0x60 = 0x60
|
||||||
irq 0x70 = 1
|
io 0x62 = 0x64
|
||||||
pnp 2e.7 off # GPIO
|
irq 0x70 = 1
|
||||||
pnp 2e.8 off # ACB
|
end
|
||||||
pnp 2e.9 off # FSCM
|
device pnp 2e.7 off end # GPIO
|
||||||
pnp 2e.a off # WDT
|
device pnp 2e.8 off end # ACB
|
||||||
|
device pnp 2e.9 off end # FSCM
|
||||||
|
device pnp 2e.a off end # WDT
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device pci 1.1 on end
|
||||||
|
device pci 1.2 on end
|
||||||
|
device pci 1.3 on
|
||||||
|
chip drivers/generic/generic
|
||||||
|
#phillips pca9545 smbus mux
|
||||||
|
device i2c 70 on
|
||||||
|
# analog_devices adm1026
|
||||||
|
chip drivers/generic/generic
|
||||||
|
device i2c 2c on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device i2c 70 on end
|
||||||
|
device i2c 70 on end
|
||||||
|
device i2c 70 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 0-0-0
|
||||||
|
device i2c 50 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 0-0-1
|
||||||
|
device i2c 51 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device pci 1.5 off end
|
||||||
|
device pci 1.6 on end
|
||||||
|
end
|
||||||
|
end # device pci 18.0
|
||||||
|
|
||||||
|
device pci 18.0 on end # LDT1
|
||||||
|
device pci 18.0 on end # LDT2
|
||||||
|
device pci 18.1 on end
|
||||||
|
device pci 18.2 on end
|
||||||
|
device pci 18.3 on end
|
||||||
|
end
|
||||||
|
device apic_cluster 0 on
|
||||||
|
chip cpu/amd/socket_754
|
||||||
|
device apic 0 on end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
cpu k8 "cpu0"
|
|
||||||
end
|
|
||||||
|
|
||||||
##
|
|
||||||
## Include the old serial code for those few places that still need it.
|
|
||||||
##
|
|
||||||
mainboardinit pc80/serial.inc
|
|
||||||
mainboardinit arch/i386/lib/console.inc
|
|
||||||
#mainboardinit cpu/i386/bist32_fail.inc
|
|
||||||
|
|
||||||
|
|||||||
210
src/mainboard/amd/solo/Options.lb
Normal file
210
src/mainboard/amd/solo/Options.lb
Normal file
@ -0,0 +1,210 @@
|
|||||||
|
uses HAVE_MP_TABLE
|
||||||
|
uses HAVE_PIRQ_TABLE
|
||||||
|
uses USE_FALLBACK_IMAGE
|
||||||
|
uses HAVE_FALLBACK_BOOT
|
||||||
|
uses HAVE_HARD_RESET
|
||||||
|
uses HARD_RESET_BUS
|
||||||
|
uses HARD_RESET_DEVICE
|
||||||
|
uses HARD_RESET_FUNCTION
|
||||||
|
uses IRQ_SLOT_COUNT
|
||||||
|
uses HAVE_OPTION_TABLE
|
||||||
|
uses CONFIG_MAX_CPUS
|
||||||
|
uses CONFIG_IOAPIC
|
||||||
|
uses CONFIG_SMP
|
||||||
|
uses FALLBACK_SIZE
|
||||||
|
uses ROM_SIZE
|
||||||
|
uses ROM_SECTION_SIZE
|
||||||
|
uses ROM_IMAGE_SIZE
|
||||||
|
uses ROM_SECTION_SIZE
|
||||||
|
uses ROM_SECTION_OFFSET
|
||||||
|
uses CONFIG_ROM_STREAM
|
||||||
|
uses CONFIG_ROM_STREAM_START
|
||||||
|
uses PAYLOAD_SIZE
|
||||||
|
uses _ROMBASE
|
||||||
|
uses XIP_ROM_SIZE
|
||||||
|
uses XIP_ROM_BASE
|
||||||
|
uses STACK_SIZE
|
||||||
|
uses HEAP_SIZE
|
||||||
|
uses USE_OPTION_TABLE
|
||||||
|
uses LB_CKS_RANGE_START
|
||||||
|
uses LB_CKS_RANGE_END
|
||||||
|
uses LB_CKS_LOC
|
||||||
|
uses MAINBOARD_PART_NUMBER
|
||||||
|
uses MAINBOARD_VENDOR
|
||||||
|
uses MAINBOARD
|
||||||
|
uses LINUXBIOS_EXTRA_VERSION
|
||||||
|
uses _RAMBASE
|
||||||
|
uses CC
|
||||||
|
uses HOSTCC
|
||||||
|
uses TTYS0_BAUD
|
||||||
|
uses TTYS0_BASE
|
||||||
|
uses TTYS0_LCS
|
||||||
|
uses DEFAULT_CONSOLE_LOGLEVEL
|
||||||
|
uses MAXIMUM_CONSOLE_LOGLEVEL
|
||||||
|
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||||
|
uses CONFIG_CONSOLE_SERIAL8250
|
||||||
|
|
||||||
|
|
||||||
|
###
|
||||||
|
### Build options
|
||||||
|
###
|
||||||
|
|
||||||
|
##
|
||||||
|
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||||
|
##
|
||||||
|
default ROM_SIZE=524288
|
||||||
|
|
||||||
|
##
|
||||||
|
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||||
|
##
|
||||||
|
default FALLBACK_SIZE=131072
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code for the fallback boot
|
||||||
|
##
|
||||||
|
default HAVE_FALLBACK_BOOT=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to reset the motherboard from linuxBIOS
|
||||||
|
##
|
||||||
|
default HAVE_HARD_RESET=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Funky hard reset implementation
|
||||||
|
##
|
||||||
|
default HARD_RESET_BUS=1
|
||||||
|
default HARD_RESET_DEVICE=4
|
||||||
|
default HARD_RESET_FUNCTION=0
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to export a programmable irq routing table
|
||||||
|
##
|
||||||
|
default HAVE_PIRQ_TABLE=1
|
||||||
|
default IRQ_SLOT_COUNT=9
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to export an x86 MP table
|
||||||
|
## Useful for specifying IRQ routing values
|
||||||
|
##
|
||||||
|
default HAVE_MP_TABLE=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to export a CMOS option table
|
||||||
|
##
|
||||||
|
default HAVE_OPTION_TABLE=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Move the default LinuxBIOS cmos range off of AMD RTC registers
|
||||||
|
##
|
||||||
|
default LB_CKS_RANGE_START=49
|
||||||
|
default LB_CKS_RANGE_END=122
|
||||||
|
default LB_CKS_LOC=123
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code for SMP support
|
||||||
|
## Only worry about 2 micro processors
|
||||||
|
##
|
||||||
|
default CONFIG_SMP=1
|
||||||
|
default CONFIG_MAX_CPUS=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to setup a generic IOAPIC
|
||||||
|
##
|
||||||
|
default CONFIG_IOAPIC=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Clean up the motherboard id strings
|
||||||
|
##
|
||||||
|
default MAINBOARD_PART_NUMBER="SOLO"
|
||||||
|
default MAINBOARD_VENDOR="AMD"
|
||||||
|
|
||||||
|
###
|
||||||
|
### LinuxBIOS layout values
|
||||||
|
###
|
||||||
|
|
||||||
|
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||||
|
default ROM_IMAGE_SIZE = 65536
|
||||||
|
|
||||||
|
##
|
||||||
|
## Use a small 8K stack
|
||||||
|
##
|
||||||
|
default STACK_SIZE=0x2000
|
||||||
|
|
||||||
|
##
|
||||||
|
## Use a small 16K heap
|
||||||
|
##
|
||||||
|
default HEAP_SIZE=0x4000
|
||||||
|
|
||||||
|
##
|
||||||
|
## Only use the option table in a normal image
|
||||||
|
##
|
||||||
|
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||||
|
|
||||||
|
##
|
||||||
|
## LinuxBIOS C code runs at this location in RAM
|
||||||
|
##
|
||||||
|
default _RAMBASE=0x00004000
|
||||||
|
|
||||||
|
##
|
||||||
|
## Load the payload from the ROM
|
||||||
|
##
|
||||||
|
default CONFIG_ROM_STREAM = 1
|
||||||
|
|
||||||
|
###
|
||||||
|
### Defaults of options that you may want to override in the target config file
|
||||||
|
###
|
||||||
|
|
||||||
|
##
|
||||||
|
## The default compiler
|
||||||
|
##
|
||||||
|
default CC="gcc -m32"
|
||||||
|
default HOSTCC="gcc"
|
||||||
|
|
||||||
|
##
|
||||||
|
## The Serial Console
|
||||||
|
##
|
||||||
|
|
||||||
|
# To Enable the Serial Console
|
||||||
|
default CONFIG_CONSOLE_SERIAL8250=1
|
||||||
|
|
||||||
|
## Select the serial console baud rate
|
||||||
|
default TTYS0_BAUD=115200
|
||||||
|
#default TTYS0_BAUD=57600
|
||||||
|
#default TTYS0_BAUD=38400
|
||||||
|
#default TTYS0_BAUD=19200
|
||||||
|
#default TTYS0_BAUD=9600
|
||||||
|
#default TTYS0_BAUD=4800
|
||||||
|
#default TTYS0_BAUD=2400
|
||||||
|
#default TTYS0_BAUD=1200
|
||||||
|
|
||||||
|
# Select the serial console base port
|
||||||
|
default TTYS0_BASE=0x3f8
|
||||||
|
|
||||||
|
# Select the serial protocol
|
||||||
|
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||||
|
default TTYS0_LCS=0x3
|
||||||
|
|
||||||
|
##
|
||||||
|
### Select the linuxBIOS loglevel
|
||||||
|
##
|
||||||
|
## EMERG 1 system is unusable
|
||||||
|
## ALERT 2 action must be taken immediately
|
||||||
|
## CRIT 3 critical conditions
|
||||||
|
## ERR 4 error conditions
|
||||||
|
## WARNING 5 warning conditions
|
||||||
|
## NOTICE 6 normal but significant condition
|
||||||
|
## INFO 7 informational
|
||||||
|
## DEBUG 8 debug-level messages
|
||||||
|
## SPEW 9 Way too many details
|
||||||
|
|
||||||
|
## Request this level of debugging output
|
||||||
|
default DEFAULT_CONSOLE_LOGLEVEL=8
|
||||||
|
## At a maximum only compile in this level of debugging
|
||||||
|
default MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||||
|
|
||||||
|
##
|
||||||
|
## Select power on after power fail setting
|
||||||
|
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||||
|
|
||||||
|
### End Options.lb
|
||||||
|
end
|
||||||
@ -1,105 +1,22 @@
|
|||||||
# Sample config file for building AMD Solo7 images
|
# AMD Solo
|
||||||
# This will make a target directory of ./solo
|
# This will make a target directory of ./solo
|
||||||
|
|
||||||
loadoptions
|
|
||||||
|
|
||||||
target solo
|
target solo
|
||||||
|
mainboard amd/solo
|
||||||
|
|
||||||
uses ARCH
|
|
||||||
uses CONFIG_COMPRESS
|
|
||||||
uses CONFIG_IOAPIC
|
|
||||||
uses CONFIG_ROM_STREAM
|
|
||||||
uses CONFIG_ROM_STREAM_START
|
|
||||||
uses CONFIG_UDELAY_TSC
|
|
||||||
uses CPU_FIXUP
|
|
||||||
uses FALLBACK_SIZE
|
|
||||||
uses HAVE_FALLBACK_BOOT
|
|
||||||
uses HAVE_MP_TABLE
|
|
||||||
uses HAVE_PIRQ_TABLE
|
|
||||||
uses HAVE_HARD_RESET
|
|
||||||
uses i586
|
|
||||||
uses i686
|
|
||||||
uses INTEL_PPRO_MTRR
|
|
||||||
uses HEAP_SIZE
|
|
||||||
uses IRQ_SLOT_COUNT
|
|
||||||
uses k7
|
|
||||||
uses k8
|
|
||||||
uses MAINBOARD_PART_NUMBER
|
|
||||||
uses MAINBOARD_VENDOR
|
|
||||||
uses CONFIG_SMP
|
|
||||||
uses CONFIG_MAX_CPUS
|
|
||||||
uses MEMORY_HOLE
|
|
||||||
uses PAYLOAD_SIZE
|
|
||||||
uses _RAMBASE
|
|
||||||
uses _ROMBASE
|
|
||||||
uses ROM_IMAGE_SIZE
|
|
||||||
uses ROM_SECTION_OFFSET
|
|
||||||
uses ROM_SECTION_SIZE
|
|
||||||
uses ROM_SIZE
|
|
||||||
uses STACK_SIZE
|
|
||||||
uses USE_FALLBACK_IMAGE
|
|
||||||
uses USE_OPTION_TABLE
|
|
||||||
uses HAVE_OPTION_TABLE
|
|
||||||
uses MAXIMUM_CONSOLE_LOGLEVEL
|
|
||||||
uses DEFAULT_CONSOLE_LOGLEVEL
|
|
||||||
uses CONFIG_CONSOLE_SERIAL8250
|
|
||||||
uses MAINBOARD
|
|
||||||
uses CONFIG_CHIP_CONFIGURE
|
|
||||||
uses XIP_ROM_SIZE
|
|
||||||
uses XIP_ROM_BASE
|
|
||||||
uses LINUXBIOS_EXTRA_VERSION
|
|
||||||
uses HAVE_ACPI_TABLES
|
|
||||||
uses CC
|
|
||||||
|
|
||||||
option CC="gcc -m32"
|
|
||||||
|
|
||||||
option CONFIG_CHIP_CONFIGURE=1
|
|
||||||
|
|
||||||
option MAXIMUM_CONSOLE_LOGLEVEL=7
|
|
||||||
option DEFAULT_CONSOLE_LOGLEVEL=7
|
|
||||||
option CONFIG_CONSOLE_SERIAL8250=1
|
|
||||||
|
|
||||||
option CPU_FIXUP=1
|
|
||||||
option CONFIG_UDELAY_TSC=0
|
|
||||||
option i686=1
|
|
||||||
option i586=1
|
|
||||||
option INTEL_PPRO_MTRR=1
|
|
||||||
option k7=1
|
|
||||||
option k8=1
|
|
||||||
|
|
||||||
option ROM_SIZE=262144
|
|
||||||
|
|
||||||
option HAVE_OPTION_TABLE=1
|
|
||||||
option CONFIG_ROM_STREAM=1
|
|
||||||
option HAVE_FALLBACK_BOOT=1
|
|
||||||
option HAVE_HARD_RESET=1
|
|
||||||
option HAVE_ACPI_TABLES=1
|
|
||||||
|
|
||||||
###
|
|
||||||
### Compute the location and size of where this firmware image
|
|
||||||
### (linuxBIOS plus bootloader) will live in the boot rom chip.
|
|
||||||
###
|
|
||||||
option FALLBACK_SIZE=131072
|
|
||||||
|
|
||||||
## LinuxBIOS C code runs at this location in RAM
|
|
||||||
option _RAMBASE=0x00004000
|
|
||||||
|
|
||||||
#
|
|
||||||
# AMD Solo
|
|
||||||
romimage "normal"
|
romimage "normal"
|
||||||
option USE_FALLBACK_IMAGE=0
|
option USE_FALLBACK_IMAGE=0
|
||||||
option ROM_IMAGE_SIZE=0x10000
|
option ROM_IMAGE_SIZE=0x10000
|
||||||
option LINUXBIOS_EXTRA_VERSION=".0-Normal"
|
option LINUXBIOS_EXTRA_VERSION=".0-Normal"
|
||||||
mainboard amd/solo
|
payload /usr/share/LinuxBIOS/tg3--ide_disk.zelf
|
||||||
payload /suse/stepan/tg3--ide_disk.zelf
|
|
||||||
end
|
end
|
||||||
|
|
||||||
romimage "fallback"
|
romimage "fallback"
|
||||||
option USE_FALLBACK_IMAGE=1
|
option USE_FALLBACK_IMAGE=1
|
||||||
option ROM_IMAGE_SIZE=0x10000
|
option ROM_IMAGE_SIZE=0x10000
|
||||||
option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
|
option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
|
||||||
mainboard amd/solo
|
payload /usr/share/LinuxBIOS/tg3--ide_disk.zelf
|
||||||
payload /suse/stepan/tg3--ide_disk.zelf
|
|
||||||
end
|
end
|
||||||
|
|
||||||
buildrom ./solo.rom ROM_SIZE "normal" "fallback"
|
buildrom ./solo.rom ROM_SIZE "normal" "fallback"
|
||||||
|
|||||||
Reference in New Issue
Block a user