From de3ee05f9385145c9de996300e1389564720e40a Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Mon, 8 Jan 2024 16:41:32 -0700 Subject: [PATCH] mb/system76: Enable S0ix for darp8/darp9 The newer batch of these boards do not de-assert VW PLTRST# on S3 resume, causes the units to not power on in the EC code. Switch them to S0ix by default, but leave S3 available. Signed-off-by: Tim Crawford --- src/mainboard/system76/adl/variants/darp8/overridetree.cb | 2 ++ src/mainboard/system76/rpl/variants/darp9/overridetree.cb | 2 ++ 2 files changed, 4 insertions(+) diff --git a/src/mainboard/system76/adl/variants/darp8/overridetree.cb b/src/mainboard/system76/adl/variants/darp8/overridetree.cb index 560dc47698..196a7bc2a4 100644 --- a/src/mainboard/system76/adl/variants/darp8/overridetree.cb +++ b/src/mainboard/system76/adl/variants/darp8/overridetree.cb @@ -1,4 +1,6 @@ chip soc/intel/alderlake + register "s0ix_enable" = "1" + register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ .tdp_pl1_override = 20, .tdp_pl2_override = 56, diff --git a/src/mainboard/system76/rpl/variants/darp9/overridetree.cb b/src/mainboard/system76/rpl/variants/darp9/overridetree.cb index 0e4c1a9049..25aa8739f4 100644 --- a/src/mainboard/system76/rpl/variants/darp9/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/darp9/overridetree.cb @@ -1,4 +1,6 @@ chip soc/intel/alderlake + register "s0ix_enable" = "1" + register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{ .tdp_pl1_override = 20, .tdp_pl2_override = 56,