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mb/prodrive/atlas: Update pcie config for i225

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Enable clk 1, LTR & AER for PCIe-to-i225 bridge.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I9593f5d0b70f3d231fd1a8f4758b924645392d63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64902
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lean Sheng Tan
2022-06-02 18:34:44 +02:00
committed by Martin L Roth
parent e4998d1cd2
commit de498a2fff
1 changed files with 4 additions and 3 deletions
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7
src/mainboard/prodrive/atlas/devicetree.cb
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@@ -55,7 +55,7 @@ chip soc/intel/alderlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled,
}" }"
# Enable PCH PCIE RP 5, 6, 7, 8, 9, 10 using free running CLK (0x80) # Enable PCH PCIE RP 5, 6, 7, 8, 9 using free running CLK (0x80)
# Clock source is shared hence marked as free running. # Clock source is shared hence marked as free running.
register "pch_pcie_rp[PCH_RP(5)]" = "{ register "pch_pcie_rp[PCH_RP(5)]" = "{
.flags = PCIE_RP_CLK_SRC_UNUSED, .flags = PCIE_RP_CLK_SRC_UNUSED,
@@ -72,12 +72,13 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(9)]" = "{ register "pch_pcie_rp[PCH_RP(9)]" = "{
.flags = PCIE_RP_CLK_SRC_UNUSED, .flags = PCIE_RP_CLK_SRC_UNUSED,
}" }"
# Enable PCIe-to-i225 bridge using clk 1
register "pch_pcie_rp[PCH_RP(10)]" = "{ register "pch_pcie_rp[PCH_RP(10)]" = "{
.flags = PCIE_RP_CLK_SRC_UNUSED, .clk_src = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_DISABLE, .pcie_rp_aspm = ASPM_DISABLE,
}" }"
register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING" register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING"
register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING"
# Enable CPU PCIE RP 1, 2, 3 using using free running CLK (0x80) # Enable CPU PCIE RP 1, 2, 3 using using free running CLK (0x80)
# Clock source is shared hence marked as free running. # Clock source is shared hence marked as free running.