Documentation: x86 device tree processing and memory map
Add documentation on: * FSP Silicon Init * How to start the x86 device tree processing for ramstage * Disabling the PCI devices * Generic PCI device drivers * Memory map support TEST=None Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
@@ -94,6 +94,24 @@
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</li>
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</ol>
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</li>
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<li>
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Implement the .init routine for the
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<a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a>
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structure which calls FSP SiliconInit
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</li>
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<li>
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Start ramstage's
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<a target="_blank" href="SoC/soc.html#DeviceTree">device tree processing</a>
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to display the PCI vendor and device IDs
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</li>
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<li>
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Disable the
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<a target="_blank" href="Board/board.html#DisablePciDevices">PCI devices</a>
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</li>
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<li>
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Implement the
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<a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a>
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</li>
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</ol>
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@@ -129,6 +147,31 @@
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Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
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</td>
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</tr>
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<tr>
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<td>Memory Map</td>
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<td>
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Implement a device driver for the
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<a target="_blank" href="SoC/soc.html#MemoryMap">north cluster</a>
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</td>
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<td>coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td>
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</tr>
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<tr>
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<td>PCI Device Support</td>
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<td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td>
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<td>The device is detected by coreboot and usable by the payload</td>
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</tr>
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<tr>
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<td>Ramstage state machine</td>
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<td>
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Implement the chip and domain operations to start the
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<a target="_blank" href="SoC/soc.html#DeviceTree">device tree</a>
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processing
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</td>
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<td>
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During the BS_DEV_ENUMERATE state, ramstage now display the device IDs
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for the PCI devices on the bus.
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</td>
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</tr>
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<tr bgcolor="#c0ffc0">
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@@ -136,6 +179,19 @@
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<th>Where</th>
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<th>Testing</th>
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</tr>
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<tr>
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<td>Device Tree</td>
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<td>
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<a target="_blank" href="SoC/soc.html#DeviceTree">List</a> PCI vendor and device IDs by starting
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the device tree processing<br>
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<a target="_blank" href="Board/board.html#DisablePciDevices">Disable</a> PCI devices<br>
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Enable: Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a>
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<td>
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List: BS_DEV_ENUMERATE state displays PCI vendor and device IDs<br>
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Disable: BS_DEV_ENUMERATE state shows the devices as disabled<br>
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Enable: BS_DEV_ENUMERATE state shows the device as on and the device works for the payload
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</td>
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</tr>
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<tr>
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<td>DRAM</td>
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<td>
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@@ -208,11 +264,36 @@
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</ul>
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</td>
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</tr>
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<tr>
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<td>SiliconInit</td>
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<td>
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Implement the .init routine for the
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<a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> structure
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</td>
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<td>During BS_DEV_INIT_CHIPS state, SiliconInit gets called and returns 0x00000000</td>
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</tr>
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<tr>
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<td>FspNotify</td>
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<td>
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The code which calls FspNotify is located in
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src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/fsp_util.c;hb=HEAD#l182">fsp_util.c</a>.
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The fsp_notify_boot_state_callback routine is called three times as specified
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by the BOOT_STATE_INIT_ENTRY macros below the routine.
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</td>
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<td>
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The FspNotify routines are called during:
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<ul>
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<li>BS_DEV_RESOURCES - on exit</li>
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<li>BS_PAYLOAD_LOAD - on exit</li>
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<li>BS_OS_RESUME - on entry (S3 resume)</li>
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</ul>
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</td>
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</tr>
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</table>
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<hr>
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<p>Modified: 31 January 2016</p>
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<p>Modified: 15 February 2016</p>
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</body>
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</html>
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