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Changes by Richard Smith and Peter Stuge from the LinuxBIOS symposium 2006.

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With CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0, 1 million outb():s are used
for timer calibration, which takes about one second.

All EPIA-M boards have timer2 so we use it to boot faster.

Only some EPIA boards have the Nehemiah CPU with timer2 so we default to IO
calibration but add the TSC options so that they can be set in Config.lb.

src/mainboard/via/epia*/reset.c is dead code (entire file within #if 0) so we
set HAVE_HARD_RESET=0 for both boards.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Peter Stuge
2007-05-10 23:50:27 +00:00
committed by Stefan Reinauer
parent ddf845f620
commit deabf510bf
5 changed files with 14 additions and 88 deletions
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5
targets/via/epia/Config.lb
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@@ -1,6 +1,11 @@
# Sample config file for EPIA
# This will make a target directory of ./epia
## uncomment these three lines if you have a Nehemiah CPU to boot 1s faster
#option CONFIG_UDELAY_IO=0
#option CONFIG_UDELAY_TSC=1
#option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
target epia
mainboard via/epia
option MAXIMUM_CONSOLE_LOGLEVEL=9