From df0396149aba5171d64b9fbab0856dc9f07b1c15 Mon Sep 17 00:00:00 2001 From: Xi Chen Date: Thu, 18 Aug 2022 11:23:26 +0800 Subject: [PATCH] soc/mediatek/mt8188: Support 4 channel DRAM in DPM init flow TEST=build pass BUG=b:236331724 Signed-off-by: Xi Chen Change-Id: Ia68aca1d1e8729739246157904727123e5d001e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66968 Reviewed-by: Yidi Lin Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8188/Kconfig | 1 + src/soc/mediatek/mt8188/Makefile.inc | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/soc/mediatek/mt8188/Kconfig b/src/soc/mediatek/mt8188/Kconfig index bc42fede1f..e42f6a38e8 100644 --- a/src/soc/mediatek/mt8188/Kconfig +++ b/src/soc/mediatek/mt8188/Kconfig @@ -11,6 +11,7 @@ config SOC_MEDIATEK_MT8188 select CACHE_MRC_SETTINGS select MEDIATEK_BLOB_FAST_INIT select USE_CBMEM_DRAM_INFO + select DPM_FOUR_CHANNEL if SOC_MEDIATEK_MT8188 diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index 6f4255204c..ee677a3895 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -30,6 +30,8 @@ romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c ramstage-y += ../common/auxadc.c ramstage-y += ../common/dfd.c +ramstage-y += ../common/dpm.c +ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c ramstage-y += ../common/emi.c ramstage-y += ../common/mcu.c ramstage-y += ../common/mcupm.c