mainboard/opencellular/rotundu: Enable TPM 1.2 support
* Enable support for all variants. Change-Id: Ibdd43d8cff23d3fa1154e2b72aa6095682783fe5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Philipp Deppenwiese
parent
660dd00079
commit
df1a065215
@ -27,6 +27,8 @@ config BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
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select HAVE_ACPI_RESUME
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select USE_BLOBS
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select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM1
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if BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU
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@ -36,7 +36,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
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gnvs->s5u1 = 0;
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/* TPM Present */
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gnvs->tpmp = 0;
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gnvs->tpmp = 1;
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/* Enable DPTF */
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gnvs->dpte = 0;
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@ -75,7 +75,11 @@ chip soc/intel/fsp_baytrail
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device pci 1e.3 on end # 8086 0F0A - HSUART 1
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device pci 1e.4 off end # 8086 0F0C - HSUART 2
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device pci 1e.5 off end # 8086 0F0E - SPI
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device pci 1f.0 on end # 8086 0F1C - LPC bridge
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device pci 1f.0 on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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end # 8086 0F1C - LPC bridge
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device pci 1f.3 on end # 8086 0F12 - SMBus 0
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end
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end
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@ -75,7 +75,11 @@ chip soc/intel/fsp_baytrail
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device pci 1e.3 on end # 8086 0F0A - HSUART 1
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device pci 1e.4 off end # 8086 0F0C - HSUART 2
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device pci 1e.5 off end # 8086 0F0E - SPI
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device pci 1f.0 on end # 8086 0F1C - LPC bridge
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device pci 1f.0 on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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end # 8086 0F1C - LPC bridge
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device pci 1f.3 on end # 8086 0F12 - SMBus 0
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end
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end
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