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mb/google/trulo/var/orisa: Fill in gpio.h

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Fill ec pins in gpio.h and configure GPE0 DW2 in overridetree according to schematic_20240614.

BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I9de842a8a66632314d5fdf6444005d34338a1100
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83155
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
This commit is contained in:
Amanda Huang 2024-06-22 11:10:53 +08:00 committed by Eric Lai
parent 7c05c61b0b
commit df30d9199e
2 changed files with 13 additions and 1 deletions
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13
src/mainboard/google/brya/variants/orisa/include/variant/gpio.h
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@ -3,9 +3,20 @@
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <baseboard/gpio.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
/* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI
/* EC wake is EC_SOC_WAKE_ODL which is routed to GPP_F17 */
#define GPE_EC_WAKE GPE0_DW2_17
/* WP signal to PCH */
#define GPIO_PCH_WP GPP_E3
/* EC in RW or RO */
#define GPIO_EC_IN_RW GPP_F18
/* GPIO IRQ for tight timestamps, MKBP interrupts */
#define EC_SYNC_IRQ GPD2_IRQ
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_H18
#endif

1
src/mainboard/google/brya/variants/orisa/overridetree.cb
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@ -14,6 +14,7 @@ chip soc/intel/alderlake
# GPE configuration
register "pmc_gpe0_dw1" = "GPP_B"
register "pmc_gpe0_dw2" = "GPP_F"
# S0ix enable
register "s0ix_enable" = "1"