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MCP55: Add TINY_BOOTBLOCK support.

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Also, move CONFIG_HT_CHAIN_END_UNITID_BASE #ifdef block to mcp55.h to make
the build work (but this is a good idea anyway, as it's used in
multiple files).

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
2010-11-25 09:03:55 +00:00
parent 48ae6086da
commit df323fcefd
17 changed files with 47 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/southbridge/nvidia/mcp55/Kconfig
View File

@@ -2,9 +2,14 @@ config SOUTHBRIDGE_NVIDIA_MCP55
bool
select HAVE_USBDEBUG
select IOAPIC
select TINY_BOOTBLOCK
if SOUTHBRIDGE_NVIDIA_MCP55
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/nvidia/mcp55/bootblock.c"
config ID_SECTION_OFFSET
hex
default 0x80

26
src/southbridge/nvidia/mcp55/bootblock.c Normal file
View File

@@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
static void bootblock_southbridge_init(void)
{
mcp55_enable_rom();
}

2
src/southbridge/nvidia/mcp55/chip.h
View File

@@ -22,6 +22,8 @@
#ifndef MCP55_CHIP_H
#define MCP55_CHIP_H
#include <device/device.h>
struct southbridge_nvidia_mcp55_config
{
unsigned int ide0_enable : 1;

12
src/southbridge/nvidia/mcp55/mcp55.h
View File

@@ -22,13 +22,21 @@
#ifndef MCP55_H
#define MCP55_H
#include "chip.h"
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
#ifndef __PRE_RAM__
#include "chip.h"
void mcp55_enable(device_t dev);
extern struct pci_operations mcp55_pci_ops;
#else
#if !defined(__ROMCC__)
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
#endif
void mcp55_enable_usbdebug(unsigned int port);
#endif
#endif
#endif /* MCP55_H */

9
src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
View File

@@ -21,11 +21,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
#include <stdint.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include "mcp55.h"
static void mcp55_enable_rom(void)
{

6
src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
View File

@@ -28,12 +28,6 @@
#include <device/pci_def.h>
#include "mcp55.h"
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
void set_debug_port(unsigned int port)
{
u32 dword;