From df6bc335f51bc2016da6421019f5c85e6e597206 Mon Sep 17 00:00:00 2001
From: Usha P <usha.p@intel.com>
Date: Mon, 16 Jan 2023 15:03:13 +0530
Subject: [PATCH] mb/intel/mtlrvp: Enable S0ix

This patch enables S0ix for MTL-P RVP platform

BUG=None
TEST=Able to enter low power idle S0 on MTL-P RVP

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Id84f21d81197e44d6dd0dd8888c80848aa3679e0
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71994
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
---
 .../intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb     | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index b69fddd186..e7ad2e8e03 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -39,6 +39,9 @@ chip soc/intel/meteorlake
 	# Enable CNVi BT
 	register "cnvi_bt_core" = "true"
 
+	# Enable S0ix
+	register "s0ix_enable" = "1"
+
 	# Enable EDP in PortA
 	register "ddi_port_A_config" = "1"
 	# Enable HDMI in Port B