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soc/intel/mtl: enable FSP uGOP config in MTL for eSOL

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This patch updates the platform-specific Meteor Lake early
sign-of-life config (SOC_INTEL_METEORLAKE_SIGN_OF_LIFE) with a generic
ChromeOS eSOL config (CHROMEOS_ENABLE_ESOL) which uses the Intel FSP
uGOP driver as an underlying technology for rendering eSOL screen.

This patch does not change the binary or the system behaviour.

BUG=b:352651132
TEST=Able to build google/rex and checked the config in output.

Change-Id: Ib4589f52080229b1c83915b51272a042b7ac32cd
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83769
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jayvik Desai 2024-08-05 21:16:49 +05:30 committed by Subrata Banik
parent 95d03996d9
commit dfa830e530
2 changed files with 2 additions and 11 deletions
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11
src/soc/intel/meteorlake/Kconfig
View File

@ -20,6 +20,7 @@ config SOC_INTEL_METEORLAKE
select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
select FSP_M_XIP select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
select FSP_UGOP_EARLY_SIGN_OF_LIFE if !SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON
select FSP_USES_CB_DEBUG_EVENT_HANDLER select FSP_USES_CB_DEBUG_EVENT_HANDLER
select FSPS_HAS_ARCH_UPD select FSPS_HAS_ARCH_UPD
select GENERIC_GPIO_LIB select GENERIC_GPIO_LIB
@ -457,16 +458,6 @@ config SOC_INTEL_COMMON_BLOCK_ACPI_SLP_S0_FREQ_HZ
help help
slp_s0_residency granularity in 122us ticks (i.e. ~8.2KHz) in Meteor Lake. slp_s0_residency granularity in 122us ticks (i.e. ~8.2KHz) in Meteor Lake.
config SOC_INTEL_METEORLAKE_SIGN_OF_LIFE
bool
default y if !SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON
depends on MAINBOARD_HAS_CHROMEOS
select VBT_CBFS_COMPRESSION_DEFAULT_LZ4
help
Enable the FSP-M Sign-of-Life feature to display a
configurable text message on screen during memory training
and CSME update.
config SOC_PHYSICAL_ADDRESS_WIDTH config SOC_PHYSICAL_ADDRESS_WIDTH
int int
default 42 default 42

2
src/soc/intel/meteorlake/romstage/fsp_params.c
View File

@ -511,7 +511,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
soc_memory_init_params(m_cfg, config); soc_memory_init_params(m_cfg, config);
if (CONFIG(SOC_INTEL_METEORLAKE_SIGN_OF_LIFE)) if (CONFIG(CHROMEOS_ENABLE_ESOL))
fill_fspm_sign_of_life(m_cfg, arch_upd); fill_fspm_sign_of_life(m_cfg, arch_upd);
mainboard_memory_init_params(mupd); mainboard_memory_init_params(mupd);