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Enable S0iX

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Change-Id: Iba1828a385456a1a5a4e998af9b22e312e298119
This commit is contained in:
Jeremy Soller
2020-11-13 19:58:42 -07:00
parent 247a002d4a
commit dfaccb9009
2 changed files with 6 additions and 6 deletions
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6
src/mainboard/system76/galp5/devicetree.cb
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@@ -16,8 +16,8 @@ chip soc/intel/tigerlake
# Enable Enhanced Intel SpeedStep # Enable Enhanced Intel SpeedStep
register "eist_enable" = "1" register "eist_enable" = "1"
# Disable s0ix # Enable s0ix, required for TGL-U
register "s0ix_enable" = "0" register "s0ix_enable" = "1"
# CPU (soc/intel/tigerlake/cpu.c) # CPU (soc/intel/tigerlake/cpu.c)
# Power limits # Power limits
@@ -46,7 +46,7 @@ chip soc/intel/tigerlake
register "gen4_dec" = "0x00fc0F01" register "gen4_dec" = "0x00fc0F01"
# Finalize (soc/intel/tigerlake/finalize.c) # Finalize (soc/intel/tigerlake/finalize.c)
# PM Timer Disabled # PM Timer Disabled, saves power
register "PmTimerDisabled" = "1" register "PmTimerDisabled" = "1"
# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)

6
src/mainboard/system76/lemp10/devicetree.cb
View File

@@ -16,8 +16,8 @@ chip soc/intel/tigerlake
# Enable Enhanced Intel SpeedStep # Enable Enhanced Intel SpeedStep
register "eist_enable" = "1" register "eist_enable" = "1"
# Disable s0ix # Enable s0ix, required for TGL-U
register "s0ix_enable" = "0" register "s0ix_enable" = "1"
# CPU (soc/intel/tigerlake/cpu.c) # CPU (soc/intel/tigerlake/cpu.c)
# Power limits # Power limits
@@ -46,7 +46,7 @@ chip soc/intel/tigerlake
register "gen4_dec" = "0x00fc0F01" register "gen4_dec" = "0x00fc0F01"
# Finalize (soc/intel/tigerlake/finalize.c) # Finalize (soc/intel/tigerlake/finalize.c)
# PM Timer Disabled # PM Timer Disabled, saves power
register "PmTimerDisabled" = "1" register "PmTimerDisabled" = "1"
# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)