Various minor cosmetics and coding style fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
c72ff11281
commit
dfb3c130d5
@ -38,10 +38,11 @@
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#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
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/* TODO: Not needed? */
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void udelay(int usecs)
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{
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int i;
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for(i = 0; i < usecs; i++)
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for (i = 0; i < usecs; i++)
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outb(i&0xff, 0x80);
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}
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@ -57,16 +58,12 @@ static void main(unsigned long bist)
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static const struct mem_controller memctrl[] = {
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{
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.d0 = PCI_DEV(0, 0, 0),
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.channel0 = {
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(0xa << 3) | 0,
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(0xa << 3) | 1,
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},
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.channel0 = {0x50, 0x51},
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}
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};
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if (bist == 0) {
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if (bist == 0)
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early_mtrr_init();
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}
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enable_smbus();
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@ -74,33 +71,18 @@ static void main(unsigned long bist)
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uart_init();
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console_init();
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/* Halt if there was a built in self test failure */
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/* Halt if there was a built in self test failure. */
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report_bist_failure(bist);
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//enable_shadow_ram();
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/* dump_spd_registers(&memctrl[0]); */
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//dump_spd_registers(&memctrl[0]);
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/* sdram_initialize runs out of registers */
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//sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
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/* sdram_initialize() runs out of registers. */
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/* sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); */
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sdram_set_registers(memctrl);
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sdram_set_spd_registers(memctrl);
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sdram_enable(0, memctrl);
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/* Check whether RAM is working.
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*
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* Do _not_ check the area from 640 KB - 1 MB, as that's not really
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* RAM, but rather reserved for various other things:
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*
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* - 640 KB - 768 KB: Video Buffer Area
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* - 768 KB - 896 KB: Expansion Area
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* - 896 KB - 960 KB: Extended System BIOS Area
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* - 960 KB - 1 MB: Memory (BIOS Area) - System BIOS Area
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*
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* Trying to check these areas will fail.
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*/
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/* TODO: This is currently hardcoded to check 64 MB. */
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//ram_check(0x00000000, 0x0009ffff); /* 0 - 640 KB */
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//ram_check(0x00100000, 0x007c0000); /* 1 MB - 64 MB */
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/* Check RAM. */
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/* ram_check(0, 640 * 1024); */
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}
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@ -4,4 +4,3 @@
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struct chip_operations mainboard_asus_mew_vm_ops = {
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CHIP_NAME("ASUS MEW-VM Mainboard")
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};
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@ -18,8 +18,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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struct northbridge_intel_i82810_config
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{
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struct northbridge_intel_i82810_config {
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};
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extern struct chip_operations northbridge_intel_i82810_ops;
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@ -47,7 +47,7 @@
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#define SID 0x2e /* Subsystem Identification */
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#define CAPPTR 0x34 /* Capabilities Pointer */
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/* TODO: Descriptions */
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/* TODO: Descriptions. */
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#define GMCHCFG 0x50
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#define PAM 0x51
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#define DRP 0x52
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@ -62,12 +62,14 @@ static void pci_domain_read_resources(device_t dev)
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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resource->base = 0x400;
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resource->limit = 0xffffUL;
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resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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resource->flags =
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IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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/* Initialize the system wide memory resources constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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resource->limit = 0xffffffffULL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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resource->flags =
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IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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}
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static void ram_resource(device_t dev, unsigned long index,
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@ -79,9 +81,9 @@ static void ram_resource(device_t dev, unsigned long index,
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return;
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}
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resource = new_resource(dev, index);
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resource->base = ((resource_t)basek) << 10;
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resource->size = ((resource_t)sizek) << 10;
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resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
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resource->base = ((resource_t) basek) << 10;
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resource->size = ((resource_t) sizek) << 10;
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resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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}
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@ -101,7 +103,8 @@ static uint32_t find_pci_tolm(struct bus *bus)
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struct resource *min;
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uint32_t tolm;
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min = 0;
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search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
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search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
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&min);
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tolm = 0xffffffffUL;
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if (min && tolm > min->base) {
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tolm = min->base;
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@ -205,8 +208,7 @@ static void enable_dev(struct device *dev)
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if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
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dev->ops = &pci_domain_ops;
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pci_set_method(dev);
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}
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else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
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} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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}
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@ -98,7 +98,8 @@ static void do_ram_command(const struct mem_controller *ctrl, uint32_t command,
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DIMM-independant configuration functions.
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-----------------------------------------------------------------------------*/
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static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_offset)
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static void spd_set_dram_size(const struct mem_controller *ctrl,
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uint32_t row_offset)
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{
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/* The variables drp and dimm_size have to be ints since all the
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* SMBus-related functions return ints, and its just easier this way.
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@ -107,8 +108,7 @@ static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_of
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drp = 0x00;
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for (i = 0; i < DIMM_SOCKETS; i++)
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{
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for (i = 0; i < DIMM_SOCKETS; i++) {
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/* First check if a DIMM is actually present. */
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if (smbus_read_byte(ctrl->channel0[i], 2) == 4) {
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print_debug("Found DIMM in slot ");
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@ -126,37 +126,45 @@ static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_of
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* side. This will fail if the DIMM uses a
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* non-supported DRAM tech, and can't be used until
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* buffers are done dynamically.
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* Note: the factory BIOS just dies if it spots
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* this :D
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* Note: the factory BIOS just dies if it spots this :D
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*/
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if(dimm_size > 32) {
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if (dimm_size > 32) {
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print_err("DIMM row sizes larger than 128MB not"
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"supported on i810\r\n");
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print_err("Attempting to treat as 128MB DIMM\r\n");
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print_err
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("Attempting to treat as 128MB DIMM\r\n");
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dimm_size = 32;
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}
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/* Set the row offset, in KBytes (should this be Kbits?) */
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/* Note that this offset is the start of the next row. */
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/* Set the row offset, in KBytes (should this be
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* Kbits?). Note that this offset is the start of the
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* next row.
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*/
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row_offset = (dimm_size * 4 * 1024);
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/* This is the way I was doing this, it's provided mainly
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* as an alternative to the "new" way.
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/* This is the way I was doing this, it's provided
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* mainly as an alternative to the "new" way.
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*/
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#if 0
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#if 0
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/* 8MB */
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if(dimm_size == 0x2) dimm_size = 0x1;
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if (dimm_size == 0x2)
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dimm_size = 0x1;
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/* 16MB */
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else if(dimm_size == 0x4) dimm_size = 0x4;
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else if (dimm_size == 0x4)
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dimm_size = 0x4;
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/* 32MB */
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else if(dimm_size == 0x8) dimm_size = 0x7;
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else if (dimm_size == 0x8)
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dimm_size = 0x7;
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/* 64 MB */
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else if(dimm_size == 0x10) dimm_size = 0xa;
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else if (dimm_size == 0x10)
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dimm_size = 0xa;
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/* 128 MB */
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else if(dimm_size == 0x20) dimm_size = 0xd;
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else print_debug("Ram Size not supported\r\n");
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#endif
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else if (dimm_size == 0x20)
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dimm_size = 0xd;
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else
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print_debug("Ram Size not supported\r\n");
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#endif
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/* This array is provided in raminit.h, because it got
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* extremely messy. The above way is cleaner, but
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@ -169,8 +177,9 @@ static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_of
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print_debug("\r\n");
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/* If the DIMM is dual-sided, the DRP value is +2 */
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/* TODO: Figure out asymetrical configurations */
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if ((smbus_read_byte(ctrl->channel0[i], 127) | 0xf) == 0xff) {
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/* TODO: Figure out asymetrical configurations. */
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if ((smbus_read_byte(ctrl->channel0[i], 127) | 0xf) ==
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0xff) {
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print_debug("DIMM is dual-sided\r\n");
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dimm_size += 2;
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}
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@ -179,7 +188,7 @@ static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_of
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print_debug_hex8(i);
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print_debug("\r\n");
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/* If there's no DIMM in the slot, set the value to 0. */
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/* If there's no DIMM in the slot, set value to 0. */
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dimm_size = 0x00;
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}
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@ -21,7 +21,7 @@
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#ifndef NORTHBRIDGE_INTEL_I82810_RAMINIT_H
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#define NORTHBRIDGE_INTEL_I82810_RAMINIT_H
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/* The i810 supports max 2 dual-sided DIMMs. */
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/* The 82810 supports max. 2 dual-sided DIMMs. */
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#define DIMM_SOCKETS 2
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struct mem_controller {
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@ -29,9 +29,6 @@ struct mem_controller {
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uint16_t channel0[DIMM_SOCKETS];
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};
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#endif /* NORTHBRIDGE_INTEL_I82810_RAMINIT_H */
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/* The following table has been bumped over to this header to avoid clutter in
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* raminit.c. It's used to translate the value read from SPD Byte 31 to a value
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* the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most
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@ -40,7 +37,7 @@ struct mem_controller {
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* this table is necessary.
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*/
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/* TODO: Find a better way of doing this */
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/* TODO: Find a better way of doing this. */
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static const uint8_t translate_spd_to_i82810[] = {
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/* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB
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@ -86,5 +83,7 @@ static const uint8_t translate_spd_to_i82810[] = {
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, /* 0x31-3f Invalid */
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0x0f, /* 0x40 256/0 or 256 */
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/* Anything larger is not supported by the i810 */
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/* Anything larger is not supported by the 82810. */
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};
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#endif /* NORTHBRIDGE_INTEL_I82810_RAMINIT_H */
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@ -19,19 +19,18 @@
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*/
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#ifndef IGNORE_I82801XX_DEVICE_LIST
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#warning "The i82801xx code currently supports, on a testing/experimental basis,"
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#warning "these devices:"
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#warning "i82801aa, i82801ab, i82801ba, i82801ca, i82801db, i82801dbm, i82801eb,"
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#warning "and i82801er."
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#warning "Using this without modification on any other i82801 version will probably"
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#warning "work until ram init, but will fail after that"
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#warning "The i82801xx code currently supports, on a testing/experimental"
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#warning "basis, these devices:"
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#warning "i82801aa, i82801ab, i82801ba, i82801ca, i82801db, i82801dbm,"
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#warning "i82801eb, and i82801er."
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#warning "Using this without modification on any other i82801 version will"
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#warning "probably work until RAM init, but will fail after that."
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#endif
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#ifndef SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
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#define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
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struct southbridge_intel_i82801xx_config
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{
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struct southbridge_intel_i82801xx_config {
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};
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extern struct chip_operations southbridge_intel_i82801xx_ops;
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@ -22,7 +22,7 @@ static void check_cmos_failed(void)
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{
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uint8_t byte;
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byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
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if( byte & RTC_FAILED) {
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if (byte & RTC_FAILED) {
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//clear bit 1 and bit 2
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byte = cmos_read(RTC_BOOT_BYTE);
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byte &= 0x0c;
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@ -2,7 +2,7 @@
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2005 Digital Design Corporation
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* (Written by Steven J. Magnani <steve@digidescorp.com> for Digital Design Corp)
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* (Written by Steven J. Magnani <steve@digidescorp.com> for Digital Design)
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* Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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@ -30,25 +30,24 @@ void i82801xx_enable(device_t dev)
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unsigned int index = 0;
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uint16_t cur_disable_mask, new_disable_mask;
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// All 82801 devices should be on bus 0
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unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc
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/* All 82801 devices should be on bus 0. */
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unsigned int devfn = PCI_DEVFN(0x1f, 0); // LPC
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device_t lpc_dev = dev_find_slot(0, devfn); // 0
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if (!lpc_dev)
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return;
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/* We're going to assume, perhaps incorrectly, that if a function exists
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it can be disabled. Workarounds for ICH variants that don't follow this
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should be done by checking the device ID */
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/* We're going to assume, perhaps incorrectly, that if a function
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* exists it can be disabled. Workarounds for ICH variants that don't
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* follow this should be done by checking the device ID.
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*/
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if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
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index = PCI_FUNC(dev->path.u.pci.devfn);
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} else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
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index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
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}
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/* Function 0 is a bit of an exception */
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if(index == 0)
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{
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/* Function 0 is a bit of an exception. */
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if (index == 0) {
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index = 14;
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}
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cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
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@ -18,8 +18,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef I82801XX_H
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#define I82801XX_H
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#ifndef SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
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#define SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
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#ifndef __ROMCC__
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#include "chip.h"
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@ -59,31 +59,32 @@ extern void i82801xx_enable(device_t dev);
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#define MTT 0x70
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#define PCI_MAST_STS 0x82
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// GEN_PMCON_3 bits
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/* GEN_PMCON_3 bits */
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#define RTC_BATTERY_DEAD (1 << 2)
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#define RTC_POWER_FAILED (1 << 1)
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#define SLEEP_AFTER_POWER_FAIL (1 << 0)
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// PCI Configuration Space (D31:F1)
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#define IDE_TIM_PRI 0x40 // IDE timings, primary
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#define IDE_TIM_SEC 0x42 // IDE timings, secondary
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/* PCI Configuration Space (D31:F1) */
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#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
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#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
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// IDE_TIM bits
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/* IDE_TIM bits */
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#define IDE_DECODE_ENABLE (1 << 15)
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// PCI Configuration Space (D31:F3)
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/* PCI Configuration Space (D31:F3) */
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#define SMB_BASE 0x20
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#define HOSTC 0x40
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// HOSTC bits
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/* HOSTC bits */
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#define I2C_EN (1 << 2)
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#define SMB_SMI_EN (1 << 1)
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#define HST_EN (1 << 0)
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// SMBus IO bits
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||||
/* TODO: Does it matter where we put the SMBus IO base, as long as we keep
|
||||
consistent and don't interfere with anything else? */
|
||||
//#define SMBUS_IO_BASE 0x1000
|
||||
/* SMBus I/O bits.
|
||||
* TODO: Does it matter where we put the SMBus IO base, as long as we keep
|
||||
* consistent and don't interfere with anything else?
|
||||
*/
|
||||
/* #define SMBUS_IO_BASE 0x1000 */
|
||||
#define SMBUS_IO_BASE 0x0f00
|
||||
|
||||
#define SMBHSTSTAT 0x0
|
||||
@ -100,7 +101,7 @@ extern void i82801xx_enable(device_t dev);
|
||||
|
||||
#define SMBUS_TIMEOUT (10 * 1000 * 100)
|
||||
|
||||
//HPET, if present
|
||||
/* HPET, if present */
|
||||
#define HPET_ADDR 0xfed0000
|
||||
|
||||
#endif /* I82801XX_H */
|
||||
#endif /* SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H */
|
||||
|
||||
@ -34,7 +34,7 @@ static struct device_operations ac97_ops = {
|
||||
.enable = i82801xx_enable,
|
||||
};
|
||||
|
||||
/* i82801aa */
|
||||
/* 82801AA */
|
||||
static struct pci_driver i82801aa_ac97_audio __pci_driver = {
|
||||
.ops = &ac97_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
@ -47,7 +47,7 @@ static struct pci_driver i82801aa_ac97_modem __pci_driver = {
|
||||
.device = 0x2416,
|
||||
};
|
||||
|
||||
/* i82801ab */
|
||||
/* 82801AB */
|
||||
static struct pci_driver i82801ab_ac97_audio __pci_driver = {
|
||||
.ops = &ac97_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
@ -60,7 +60,7 @@ static struct pci_driver i82801ab_ac97_modem __pci_driver = {
|
||||
.device = 0x2426,
|
||||
};
|
||||
|
||||
/* i82801ba */
|
||||
/* 82801BA */
|
||||
static struct pci_driver i82801ba_ac97_audio __pci_driver = {
|
||||
.ops = &ac97_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
@ -73,7 +73,7 @@ static struct pci_driver i82801ba_ac97_modem __pci_driver = {
|
||||
.device = 0x2446,
|
||||
};
|
||||
|
||||
/* i82801ca */
|
||||
/* 82801CA */
|
||||
static struct pci_driver i82801ca_ac97_audio __pci_driver = {
|
||||
.ops = &ac97_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
@ -86,7 +86,7 @@ static struct pci_driver i82801ca_ac97_modem __pci_driver = {
|
||||
.device = 0x2486,
|
||||
};
|
||||
|
||||
/* i82801db & i82801dbm */
|
||||
/* 82801DB & 82801DBM */
|
||||
static struct pci_driver i82801db_ac97_audio __pci_driver = {
|
||||
.ops = &ac97_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
@ -99,7 +99,7 @@ static struct pci_driver i82801db_ac97_modem __pci_driver = {
|
||||
.device = 0x24c6,
|
||||
};
|
||||
|
||||
/* i82801eb & i82801er */
|
||||
/* 82801EB & 82801ER */
|
||||
static struct pci_driver i82801ex_ac97_audio __pci_driver = {
|
||||
.ops = &ac97_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
|
||||
@ -29,30 +29,35 @@ static void enable_smbus(void)
|
||||
device_t dev;
|
||||
uint16_t device_id;
|
||||
|
||||
/* Set the SMBus device staticly */
|
||||
/* Set the SMBus device staticly. */
|
||||
dev = PCI_DEV(0x0, 0x1f, 0x3);
|
||||
|
||||
/* Check to make sure we've got the right device */
|
||||
/* Check to make sure we've got the right device. */
|
||||
device_id = pci_read_config16(dev, 0x2);
|
||||
|
||||
/* Clear bits 7-4, since those are the only bits that vary between models */
|
||||
/* Clear bits 7-4 (the only bits that vary between models). */
|
||||
device_id &= 0xff0f;
|
||||
|
||||
if(device_id != 0x2403)
|
||||
{
|
||||
if (device_id != 0x2403) {
|
||||
die("Device not found, Corey probably screwed up!");
|
||||
}
|
||||
|
||||
/* Set SMBus I/O base */
|
||||
pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
|
||||
/* Set SMBus enable */
|
||||
/* Set SMBus I/O base. */
|
||||
pci_write_config32(dev, SMB_BASE,
|
||||
SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
|
||||
|
||||
/* Set SMBus enable. */
|
||||
pci_write_config8(dev, HOSTC, HST_EN);
|
||||
/* Set SMBus I/O space enable */
|
||||
|
||||
/* Set SMBus I/O space enable. */
|
||||
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
|
||||
/* Disable interrupt generation */
|
||||
|
||||
/* Disable interrupt generation. */
|
||||
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
|
||||
/* Clear any lingering errors, so transactions can run */
|
||||
|
||||
/* Clear any lingering errors, so transactions can run. */
|
||||
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
|
||||
print_debug("SMBus controller enabled\r\n");
|
||||
}
|
||||
|
||||
@ -61,14 +66,16 @@ static inline int smbus_read_byte(unsigned device, unsigned address)
|
||||
return do_smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
|
||||
static void smbus_write_byte(unsigned device, unsigned address,
|
||||
unsigned char val)
|
||||
{
|
||||
print_err("Unimplemented smbus_write_byte() called\r\n");
|
||||
return;
|
||||
}
|
||||
|
||||
static inline int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
|
||||
unsigned data1, unsigned data2)
|
||||
static inline int smbus_write_block(unsigned device, unsigned length,
|
||||
unsigned cmd, unsigned data1,
|
||||
unsigned data2)
|
||||
{
|
||||
return do_smbus_write_block(device, length, cmd, data1, data2);
|
||||
}
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
* Copyright (C) 2005 Tyan Computer
|
||||
* (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
|
||||
* Copyright (C) 2005 Digital Design Corporation
|
||||
* (Written by Steven J. Magnani <steve@digidescorp.com> for Digital Design Corp)
|
||||
* (Written by Steven J. Magnani <steve@digidescorp.com> for Digital Design)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
@ -29,8 +29,8 @@
|
||||
|
||||
static void ide_init(struct device *dev)
|
||||
{
|
||||
/* TODO: Needs to be tested for compatibility with ICH5(R) */
|
||||
/* Enable ide devices so the linux ide driver will work */
|
||||
/* TODO: Needs to be tested for compatibility with ICH5(R). */
|
||||
/* Enable IDE devices so the Linux IDE driver will work. */
|
||||
uint16_t ideTimingConfig;
|
||||
int enable_primary = 1;
|
||||
int enable_secondary = 1;
|
||||
@ -38,7 +38,7 @@ static void ide_init(struct device *dev)
|
||||
ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
|
||||
ideTimingConfig &= ~IDE_DECODE_ENABLE;
|
||||
if (enable_primary) {
|
||||
/* Enable primary ide interface */
|
||||
/* Enable primary IDE interface. */
|
||||
ideTimingConfig |= IDE_DECODE_ENABLE;
|
||||
printk_debug("IDE0 ");
|
||||
}
|
||||
@ -47,7 +47,7 @@ static void ide_init(struct device *dev)
|
||||
ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
|
||||
ideTimingConfig &= ~IDE_DECODE_ENABLE;
|
||||
if (enable_secondary) {
|
||||
/* Enable secondary ide interface */
|
||||
/* Enable secondary IDE interface. */
|
||||
ideTimingConfig |= IDE_DECODE_ENABLE;
|
||||
printk_debug("IDE1 ");
|
||||
}
|
||||
@ -63,49 +63,49 @@ static struct device_operations ide_ops = {
|
||||
.enable = i82801xx_enable,
|
||||
};
|
||||
|
||||
/* i82801aa */
|
||||
/* 82801AA */
|
||||
static struct pci_driver i82801aa_ide __pci_driver = {
|
||||
.ops = &ide_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2411,
|
||||
};
|
||||
|
||||
/* i82801ab */
|
||||
/* 82801AB */
|
||||
static struct pci_driver i82801ab_ide __pci_driver = {
|
||||
.ops = &ide_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2421,
|
||||
};
|
||||
|
||||
/* i82801ba */
|
||||
/* 82801BA */
|
||||
static struct pci_driver i82801ba_ide __pci_driver = {
|
||||
.ops = &ide_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x244b,
|
||||
};
|
||||
|
||||
/* i82801ca */
|
||||
/* 82801CA */
|
||||
static struct pci_driver i82801ca_ide __pci_driver = {
|
||||
.ops = &ide_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x248b,
|
||||
};
|
||||
|
||||
/* i82801db */
|
||||
/* 82801DB */
|
||||
static struct pci_driver i82801db_ide __pci_driver = {
|
||||
.ops = &ide_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x24cb,
|
||||
};
|
||||
|
||||
/* i82801dbm */
|
||||
/* 82801DBM */
|
||||
static struct pci_driver i82801dbm_ide __pci_driver = {
|
||||
.ops = &ide_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x24ca,
|
||||
};
|
||||
|
||||
/* i82801eb & i82801er */
|
||||
/* 82801EB & 82801ER */
|
||||
static struct pci_driver i82801ex_ide __pci_driver = {
|
||||
.ops = &ide_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* from i82801dbm, needs to be fixed to support everything the i82801er does */
|
||||
/* From 82801DBM, needs to be fixed to support everything the 82801ER does. */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
@ -34,7 +34,7 @@
|
||||
|
||||
#define NMI_OFF 0
|
||||
|
||||
void i82801xx_enable_ioapic( struct device *dev)
|
||||
void i82801xx_enable_ioapic(struct device *dev)
|
||||
{
|
||||
uint32_t reg32;
|
||||
volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000;
|
||||
@ -54,7 +54,7 @@ void i82801xx_enable_ioapic( struct device *dev)
|
||||
*ioapic_index = 0;
|
||||
reg32 = *ioapic_data;
|
||||
printk_debug("Southbridge APIC ID = %x\n", reg32);
|
||||
if(reg32 != (1 << 25))
|
||||
if (reg32 != (1 << 25))
|
||||
die("APIC Error\n");
|
||||
|
||||
/* TODO: From i82801ca, needed/useful on other ICH? */
|
||||
@ -62,33 +62,38 @@ void i82801xx_enable_ioapic( struct device *dev)
|
||||
*ioapic_data = 1; // Use Processor System Bus to deliver interrupts
|
||||
}
|
||||
|
||||
void i82801xx_enable_serial_irqs( struct device *dev)
|
||||
void i82801xx_enable_serial_irqs(struct device *dev)
|
||||
{
|
||||
/* set packet length and toggle silent mode bit */
|
||||
pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
|
||||
pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0));
|
||||
/* TODO: Explain/#define the real meaning of these magic numbers ^^^ */
|
||||
/* Set packet length and toggle silent mode bit. */
|
||||
pci_write_config8(dev, SERIRQ_CNTL,
|
||||
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
|
||||
pci_write_config8(dev, SERIRQ_CNTL,
|
||||
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
|
||||
/* TODO: Explain/#define the real meaning of these magic numbers. */
|
||||
}
|
||||
|
||||
void i82801xx_lpc_route_dma( struct device *dev, uint8_t mask)
|
||||
void i82801xx_lpc_route_dma(struct device *dev, uint8_t mask)
|
||||
{
|
||||
uint16_t reg16;
|
||||
int i;
|
||||
|
||||
reg16 = pci_read_config16(dev, PCI_DMA_CFG);
|
||||
reg16 &= 0x300;
|
||||
for(i = 0; i < 8; i++) {
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (i == 4)
|
||||
continue;
|
||||
reg16 |= ((mask & (1 << i))? 3:1) << (i * 2);
|
||||
reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
|
||||
}
|
||||
pci_write_config16(dev, PCI_DMA_CFG, reg16);
|
||||
}
|
||||
|
||||
/* TODO: Needs serious cleanup/comments. */
|
||||
void i82801xx_rtc_init(struct device *dev)
|
||||
{//todo:needs serious cleanup/comments
|
||||
{
|
||||
uint8_t reg8;
|
||||
uint32_t reg32;
|
||||
int rtc_failed;
|
||||
|
||||
reg8 = pci_read_config8(dev, GEN_PMCON_3);
|
||||
rtc_failed = reg8 & RTC_BATTERY_DEAD;
|
||||
if (rtc_failed) {
|
||||
@ -100,7 +105,6 @@ void i82801xx_rtc_init(struct device *dev)
|
||||
rtc_init(rtc_failed);
|
||||
}
|
||||
|
||||
|
||||
void i82801xx_1f0_misc(struct device *dev)
|
||||
{
|
||||
/* TODO: break this down into smaller functions */
|
||||
@ -143,20 +147,20 @@ static void enable_hpet(struct device *dev)
|
||||
|
||||
reg32 = pci_read_config32(dev, GEN_CNTL);
|
||||
reg32 |= (1 << 17); /* Enable HPET */
|
||||
/*Bits [16:15]Memory Address Range
|
||||
00 FED0_0000h - FED0_03FFh
|
||||
01 FED0_1000h - FED0_13FFh
|
||||
10 FED0_2000h - FED0_23FFh
|
||||
11 FED0_3000h - FED0_33FFh*/
|
||||
|
||||
/*
|
||||
* Bits [16:15] Memory Address Range
|
||||
* 00 FED0_0000h - FED0_03FFh
|
||||
* 01 FED0_1000h - FED0_13FFh
|
||||
* 10 FED0_2000h - FED0_23FFh
|
||||
* 11 FED0_3000h - FED0_33FFh
|
||||
*/
|
||||
reg32 &= ~(3 << 15); /* Clear it */
|
||||
reg32 |= (code << 15);
|
||||
/* reg32 is never written to anywhere?? */
|
||||
/* reg32 is never written to anywhere? */
|
||||
printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static void lpc_init(struct device *dev)
|
||||
{
|
||||
uint8_t byte;
|
||||
@ -170,13 +174,14 @@ static void lpc_init(struct device *dev)
|
||||
|
||||
/* TODO: Find out if this is being used/works */
|
||||
#ifdef SUSPICIOUS_LOOKING_CODE
|
||||
/* The ICH-4 datasheet does not mention this configuration register. */
|
||||
/* This code may have been inherited (incorrectly) from code for
|
||||
the AMD 766 southbridge, which *does* support this functionality. */
|
||||
/* The ICH-4 datasheet does not mention this configuration register.
|
||||
* This code may have been inherited (incorrectly) from code for
|
||||
* the AMD 766 southbridge, which *does* support this functionality.
|
||||
*/
|
||||
|
||||
/* Posted memory write enable */
|
||||
byte = pci_read_config8(dev, 0x46);
|
||||
pci_write_config8(dev, 0x46, byte | (1<<0));
|
||||
pci_write_config8(dev, 0x46, byte | (1 << 0));
|
||||
#endif
|
||||
|
||||
/* power after power fail */
|
||||
@ -185,8 +190,8 @@ static void lpc_init(struct device *dev)
|
||||
* 0 == S0 Full On
|
||||
* 1 == S5 Soft Off
|
||||
*/
|
||||
pci_write_config8(dev, GEN_PMCON_3, pwr_on?0:1);
|
||||
printk_info("Set power %s if power fails\n", pwr_on?"on":"off");
|
||||
pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
|
||||
printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off");
|
||||
|
||||
/* Set up NMI on errors */
|
||||
byte = inb(0x61);
|
||||
@ -198,7 +203,7 @@ static void lpc_init(struct device *dev)
|
||||
nmi_option = NMI_OFF;
|
||||
get_option(&nmi_option, "nmi");
|
||||
if (nmi_option) {
|
||||
byte &= ~(1 << 7); /* set NMI */
|
||||
byte &= ~(1 << 7); /* Set NMI */
|
||||
outb(byte, 0x70);
|
||||
}
|
||||
|
||||
@ -224,10 +229,12 @@ static void i82801xx_lpc_read_resources(device_t dev)
|
||||
|
||||
/* Add an extra subtractive resource for both memory and I/O */
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
||||
res->flags =
|
||||
IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
||||
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
||||
res->flags =
|
||||
IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
||||
}
|
||||
|
||||
static void i82801xx_lpc_enable_resources(device_t dev)
|
||||
@ -281,7 +288,7 @@ static struct pci_driver i82801dbm_lpc __pci_driver = {
|
||||
.device = 0x24cc,
|
||||
};
|
||||
|
||||
/* i82801eb and er */
|
||||
/* 82801EB and 82801ER */
|
||||
static struct pci_driver i82801ex_lpc __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
|
||||
@ -66,7 +66,7 @@ static struct pci_driver i82801ab_pci __pci_driver = {
|
||||
.device = 0x2428,
|
||||
};
|
||||
|
||||
/* i82801ba, ca, db, eb, and er */
|
||||
/* 82801BA, 82801CA, 82801DB, 82801EB, and 82801ER */
|
||||
static struct pci_driver i82801misc_pci __pci_driver = {
|
||||
.ops = &pci_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
|
||||
@ -22,6 +22,6 @@
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
/* Try rebooting through port 0xcf9 */
|
||||
outb((1 << 2)|(1 << 1), 0xcf9);
|
||||
/* Try rebooting through port 0xcf9. */
|
||||
outb((1 << 2) | (1 << 1), 0xcf9);
|
||||
}
|
||||
|
||||
@ -26,8 +26,9 @@
|
||||
#include <device/pci_ops.h>
|
||||
#include "i82801xx.h"
|
||||
|
||||
/* TODO: set dynamically, if the user only wants one sata channel or none at all */
|
||||
|
||||
/* TODO: Set dynamically, if the user only wants one SATA channel or none
|
||||
* at all.
|
||||
*/
|
||||
static void sata_init(struct device *dev)
|
||||
{
|
||||
/* SATA configuration */
|
||||
@ -42,16 +43,16 @@ static void sata_init(struct device *dev)
|
||||
pci_write_config16(dev, 0x48, 0x000f);
|
||||
pci_write_config16(dev, 0x4a, 0x1111);
|
||||
|
||||
/* 66 mhz */
|
||||
/* 66 MHz */
|
||||
pci_write_config16(dev, 0x54, 0xf00f);
|
||||
|
||||
/* Combine ide - sata configuration */
|
||||
/* Combine IDE - SATA configuration */
|
||||
pci_write_config8(dev, 0x90, 0x0);
|
||||
|
||||
/* port 0 & 1 enable */
|
||||
/* Port 0 & 1 enable */
|
||||
pci_write_config8(dev, 0x92, 0x33);
|
||||
|
||||
/* initialize SATA */
|
||||
/* Initialize SATA. */
|
||||
pci_write_config16(dev, 0xa0, 0x0018);
|
||||
pci_write_config32(dev, 0xa4, 0x00000264);
|
||||
pci_write_config16(dev, 0xa0, 0x0040);
|
||||
@ -67,14 +68,14 @@ static struct device_operations sata_ops = {
|
||||
.enable = i82801xx_enable,
|
||||
};
|
||||
|
||||
/* i82801eb */
|
||||
/* 82801EB */
|
||||
static struct pci_driver i82801eb_sata_driver __pci_driver = {
|
||||
.ops = &sata_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x24d1,
|
||||
};
|
||||
|
||||
/* i82801er */
|
||||
/* 82801ER */
|
||||
static struct pci_driver i82801er_sata_driver __pci_driver = {
|
||||
.ops = &sata_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
|
||||
@ -50,45 +50,44 @@ static struct device_operations smbus_ops = {
|
||||
.ops_smbus_bus = &lops_smbus_bus,
|
||||
};
|
||||
|
||||
/* i82801aa */
|
||||
/* 82801AA */
|
||||
static struct pci_driver smbus_driver __pci_driver = {
|
||||
.ops = &smbus_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2413,
|
||||
};
|
||||
|
||||
/* i82801ab */
|
||||
/* 82801AB */
|
||||
static struct pci_driver smbus_driver __pci_driver = {
|
||||
.ops = &smbus_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2423,
|
||||
};
|
||||
|
||||
/* i82801ba */
|
||||
/* 82801BA */
|
||||
static struct pci_driver smbus_driver __pci_driver = {
|
||||
.ops = &smbus_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2443,
|
||||
};
|
||||
|
||||
/* i82801ca */
|
||||
/* 82801CA */
|
||||
static struct pci_driver smbus_driver __pci_driver = {
|
||||
.ops = &smbus_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2483,
|
||||
};
|
||||
|
||||
/* i82801db and i82801dbm */
|
||||
/* 82801DB and 82801DBM */
|
||||
static struct pci_driver smbus_driver __pci_driver = {
|
||||
.ops = &smbus_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x24c3,
|
||||
};
|
||||
|
||||
/* i82801eb and i82801er */
|
||||
/* 82801EB and 82801ER */
|
||||
static struct pci_driver smbus_driver __pci_driver = {
|
||||
.ops = &smbus_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x24d3,
|
||||
};
|
||||
|
||||
|
||||
@ -34,8 +34,8 @@ static int smbus_wait_until_ready(void)
|
||||
if (--loops == 0)
|
||||
break;
|
||||
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
} while(byte & 1);
|
||||
return loops?0:-1;
|
||||
} while (byte & 1);
|
||||
return loops ? 0 : -1;
|
||||
}
|
||||
|
||||
static int smbus_wait_until_done(void)
|
||||
@ -47,8 +47,8 @@ static int smbus_wait_until_done(void)
|
||||
if (--loops == 0)
|
||||
break;
|
||||
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
} while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
|
||||
return loops?0:-1;
|
||||
} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
|
||||
return loops ? 0 : -1;
|
||||
}
|
||||
|
||||
static int smbus_wait_until_blk_done(void)
|
||||
@ -60,8 +60,8 @@ static int smbus_wait_until_blk_done(void)
|
||||
if (--loops == 0)
|
||||
break;
|
||||
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
} while((byte & (1 << 7)) == 0);
|
||||
return loops?0:-1;
|
||||
} while ((byte & (1 << 7)) == 0);
|
||||
return loops ? 0 : -1;
|
||||
}
|
||||
|
||||
static int do_smbus_read_byte(unsigned device, unsigned address)
|
||||
@ -80,15 +80,17 @@ static int do_smbus_read_byte(unsigned device, unsigned address)
|
||||
/* Set the command/address... */
|
||||
outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD);
|
||||
/* Set up for a byte data read */
|
||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), (SMBUS_IO_BASE + SMBHSTCTL));
|
||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2),
|
||||
(SMBUS_IO_BASE + SMBHSTCTL));
|
||||
/* Clear any lingering errors, so the transaction will run */
|
||||
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
|
||||
/* Clear the data byte...*/
|
||||
/* Clear the data byte... */
|
||||
outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
|
||||
|
||||
/* Start the command */
|
||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
|
||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
|
||||
SMBUS_IO_BASE + SMBHSTCTL);
|
||||
|
||||
/* Poll for transaction completion */
|
||||
if (smbus_wait_until_done() < 0) {
|
||||
@ -132,7 +134,7 @@ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd,
|
||||
/* Setup transaction */
|
||||
/* Obtain ownership */
|
||||
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
for(stat = 0; (stat & 0x40) == 0; ) {
|
||||
for (stat = 0; (stat & 0x40) == 0;) {
|
||||
stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
}
|
||||
/* Clear the done bit */
|
||||
@ -156,7 +158,7 @@ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd,
|
||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40,
|
||||
SMBUS_IO_BASE + SMBHSTCTL);
|
||||
|
||||
for(i = 0;i < length; i++) {
|
||||
for (i = 0; i < length; i++) {
|
||||
|
||||
/* Poll for transaction completion */
|
||||
if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
|
||||
@ -164,7 +166,7 @@ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd,
|
||||
}
|
||||
|
||||
/* Load the next byte */
|
||||
if(i > 3)
|
||||
if (i > 3)
|
||||
byte = (data2 >> (i % 4)) & 0x0ff;
|
||||
else
|
||||
byte = (data1 >> (i)) & 0x0ff;
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
|
||||
static void usb_init(struct device *dev)
|
||||
{
|
||||
/* TODO: Any init needed? Some ports have it, others don't */
|
||||
/* TODO: Any init needed? Some ports have it, others don't. */
|
||||
}
|
||||
|
||||
static struct device_operations usb_ops = {
|
||||
@ -39,21 +39,21 @@ static struct device_operations usb_ops = {
|
||||
.enable = i82801xx_enable,
|
||||
};
|
||||
|
||||
/* i82801aa */
|
||||
/* 82801AA */
|
||||
static struct pci_driver i82801aa_usb_1 __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2412,
|
||||
};
|
||||
|
||||
/* i82801ab */
|
||||
/* 82801AB */
|
||||
static struct pci_driver i82801ab_usb_1 __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2422,
|
||||
};
|
||||
|
||||
/* i82801ba */
|
||||
/* 82801BA */
|
||||
static struct pci_driver i82801ba_usb_1 __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
@ -66,7 +66,7 @@ static struct pci_driver i82801ba_usb_2 __pci_driver = {
|
||||
.device = 0x2444,
|
||||
};
|
||||
|
||||
/* i82801ca */
|
||||
/* 82801CA */
|
||||
static struct pci_driver i82801ca_usb_1 __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
@ -85,7 +85,7 @@ static struct pci_driver i82801ca_usb_3 __pci_driver = {
|
||||
.device = 0x2487,
|
||||
};
|
||||
|
||||
/* i82801db and i82801dbm */
|
||||
/* 82801DB and 82801DBM */
|
||||
static struct pci_driver i82801db_usb_1 __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
@ -104,7 +104,7 @@ static struct pci_driver i82801db_usb_3 __pci_driver = {
|
||||
.device = 0x24c7,
|
||||
};
|
||||
|
||||
/* i82801eb and i82801er */
|
||||
/* 82801EB and 82801ER */
|
||||
static struct pci_driver i82801ex_usb_1 __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
|
||||
@ -33,22 +33,26 @@ static void usb_ehci_init(struct device *dev)
|
||||
|
||||
printk_debug("EHCI: Setting up controller.. ");
|
||||
cmd = pci_read_config32(dev, PCI_COMMAND);
|
||||
pci_write_config32(dev, PCI_COMMAND,
|
||||
cmd | PCI_COMMAND_MASTER);
|
||||
pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
|
||||
|
||||
printk_debug("done.\n");
|
||||
}
|
||||
|
||||
static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
||||
static void usb_ehci_set_subsystem(device_t dev, unsigned vendor,
|
||||
unsigned device)
|
||||
{
|
||||
uint8_t access_cntl;
|
||||
|
||||
access_cntl = pci_read_config8(dev, 0x80);
|
||||
/* Enable writes to protected registers */
|
||||
|
||||
/* Enable writes to protected registers. */
|
||||
pci_write_config8(dev, 0x80, access_cntl | 1);
|
||||
/* Write the subsystem vendor and device id */
|
||||
|
||||
/* Write the subsystem vendor and device ID. */
|
||||
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
((device & 0xffff) << 16) | (vendor & 0xffff));
|
||||
/* Restore protection */
|
||||
|
||||
/* Restore protection. */
|
||||
pci_write_config8(dev, 0x80, access_cntl);
|
||||
}
|
||||
|
||||
@ -66,14 +70,14 @@ static struct device_operations usb_ehci_ops = {
|
||||
.ops_pci = &lops_pci,
|
||||
};
|
||||
|
||||
/* i82801db and i82801dbm */
|
||||
/* 82801DB and 82801DBM */
|
||||
static struct pci_driver i82801db_usb_ehci __pci_driver = {
|
||||
.ops = &usb_ehci_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x24cd,
|
||||
};
|
||||
|
||||
/* i82801eb and i82801er */
|
||||
/* 82801EB and 82801ER */
|
||||
static struct pci_driver i82801ex_usb_ehci __pci_driver = {
|
||||
.ops = &usb_ehci_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
|
||||
@ -17,35 +17,38 @@
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
|
||||
/* TODO: I'm fairly sure the same functionality is provided elsewhere */
|
||||
/* TODO: I'm fairly sure the same functionality is provided elsewhere. */
|
||||
|
||||
void watchdog_off(void)
|
||||
{
|
||||
device_t dev;
|
||||
unsigned long value,base;
|
||||
unsigned long value, base;
|
||||
|
||||
/* turn off the ICH5 watchdog */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
|
||||
/* Turn off the ICH5 watchdog. */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
|
||||
|
||||
/* Enable I/O space */
|
||||
/* Enable I/O space. */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 10);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
/* Get TCO base */
|
||||
|
||||
/* Get TCO base. */
|
||||
base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
|
||||
/* Disable the watchdog timer */
|
||||
|
||||
/* Disable the watchdog timer. */
|
||||
value = inw(base + 0x08);
|
||||
value |= 1 << 11;
|
||||
outw(value, base + 0x08);
|
||||
/* Clear TCO timeout status */
|
||||
|
||||
/* Clear TCO timeout status. */
|
||||
outw(0x0008, base + 0x04);
|
||||
outw(0x0002, base + 0x06);
|
||||
|
||||
printk_debug("ICH Watchdog disabled\r\n");
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -1,6 +1,3 @@
|
||||
# Config file for asus mew-vm board
|
||||
# This will make a target directory of ./mew-vm
|
||||
|
||||
target mew-vm
|
||||
mainboard asus/mew-vm
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user