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intel/gma: Don't bluntly enable I/O

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The allocator should take care of this.

Change-Id: I4ec88ebe23b4dcab069f764decc8b9b0c6e6a142
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40726
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber
2020-04-26 19:26:36 +02:00
parent 826094f65c
commit dfdf102000
9 changed files with 11 additions and 13 deletions
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2
src/northbridge/intel/gm45/gma.c
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@@ -154,7 +154,7 @@ static void gma_func0_init(struct device *dev)
/* IGD needs to be Bus Master */ /* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config32(dev, PCI_COMMAND, reg32);
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);

2
src/northbridge/intel/haswell/gma.c
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@@ -464,7 +464,7 @@ static void gma_func0_init(struct device *dev)
/* IGD needs to be Bus Master */ /* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config32(dev, PCI_COMMAND, reg32);
/* Init graphics power management */ /* Init graphics power management */

8
src/northbridge/intel/i945/gma.c
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@@ -674,8 +674,7 @@ static void gma_func0_init(struct device *dev)
/* IGD needs to be Bus Master */ /* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
| PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
@@ -717,10 +716,9 @@ static void gma_func1_init(struct device *dev)
u32 reg32; u32 reg32;
u8 val; u8 val;
/* IGD needs to be Bus Master, also enable IO access */ /* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
if (get_option(&val, "tft_brightness") == CB_SUCCESS) if (get_option(&val, "tft_brightness") == CB_SUCCESS)
pci_write_config8(dev, 0xf4, val); pci_write_config8(dev, 0xf4, val);

2
src/northbridge/intel/ironlake/gma.c
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@@ -141,7 +141,7 @@ static void gma_func0_init(struct device *dev)
/* IGD needs to be Bus Master */ /* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config32(dev, PCI_COMMAND, reg32);
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);

2
src/northbridge/intel/pineview/gma.c
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@@ -224,7 +224,7 @@ static void gma_func0_init(struct device *dev)
/* IGD needs to be Bus Master */ /* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config32(dev, PCI_COMMAND, reg32);
if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {

2
src/northbridge/intel/sandybridge/gma.c
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@@ -591,7 +591,7 @@ static void gma_func0_init(struct device *dev)
/* IGD needs to be Bus Master */ /* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config32(dev, PCI_COMMAND, reg32);
/* Init graphics power management */ /* Init graphics power management */

2
src/northbridge/intel/x4x/gma.c
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@@ -28,7 +28,7 @@ static void gma_func0_init(struct device *dev)
/* IGD needs to be Bus Master */ /* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config32(dev, PCI_COMMAND, reg32);
/* configure GMBUSFREQ */ /* configure GMBUSFREQ */

2
src/soc/intel/broadwell/igd.c
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@@ -498,7 +498,7 @@ static void igd_init(struct device *dev)
/* IGD needs to be Bus Master */ /* IGD needs to be Bus Master */
u32 reg32 = pci_read_config32(dev, PCI_COMMAND); u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config32(dev, PCI_COMMAND, reg32);
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);

2
src/soc/intel/common/block/graphics/graphics.c
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@@ -47,7 +47,7 @@ static void gma_init(struct device *const dev)
/* IGD needs to Bus Master */ /* IGD needs to Bus Master */
u32 reg32 = pci_read_config32(dev, PCI_COMMAND); u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config32(dev, PCI_COMMAND, reg32);
if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {