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a single place for the romstage stack for copy_and_run.

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geode lx and amd opteron don't use this yet.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2010-04-25 21:43:29 +00:00
committed by Stefan Reinauer
parent 5f5436f935
commit e08c29e0e7
8 changed files with 44 additions and 61 deletions
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12
src/cpu/intel/model_106cx/cache_as_ram.inc
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@@ -21,6 +21,7 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
@@ -256,16 +257,7 @@ __main:
movl %ebp, %esi
/* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This
* makes sure that we stay completely within the 1M-64K of memory that we
* preserve for suspend/resume.
*/
#ifndef HIGH_MEMORY_SAVE
#warning Need a central place for HIGH_MEMORY_SAVE
#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 )
#endif
movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp
movl $ROMSTAGE_STACK, %esp
movl %esp, %ebp
pushl %esi
call copy_and_run