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soc/intel/common: move common memmap functionality from skl,icl,cnl,apl

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This moves common memmap functionality from skl,icl,cnl,apl to the common tree.

Change-Id: I45ddfabeac806ad5ff62da97ec1409c6bb9e89ac
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36410
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner
2019-10-28 18:55:14 +01:00
committed by Patrick Georgi
parent a1dbcb9332
commit e0ad1fa7c8
6 changed files with 51 additions and 104 deletions
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24
src/soc/intel/cannonlake/memmap.c
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@@ -31,12 +31,6 @@
#include "chip.h"
void smm_region(uintptr_t *start, size_t *size)
{
*start = sa_get_tseg_base();
*size = sa_get_tseg_size();
}
static bool is_ptt_enable(void)
{
if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) ==
@@ -261,21 +255,3 @@ void *cbmem_top(void)
return (void *)(uintptr_t)ebda_cfg.tolum_base;
}
void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
/*
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
* Instruct postcar to cache 16 megs under cbmem top which is
* a safe bet to cover ramstage.
*/
top_of_ram = (uintptr_t) cbmem_top();
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
top_of_ram -= 16*MiB;
postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */
postcar_enable_tseg_cache(pcf);
}