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soc/intel/denverton_ns: Allow including microcode

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Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: Iaa295c74e9c470d5830e22d0b0c73013c7333293
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39266
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer
2020-03-03 22:39:02 +01:00
committed by Patrick Georgi
parent 6a8cde4927
commit e0b74a142c
2 changed files with 3 additions and 0 deletions
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1
src/soc/intel/denverton_ns/Kconfig
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@ -53,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC select UDELAY_TSC
select UDK_2015_BINDING select UDK_2015_BINDING
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select SUPPORT_CPU_UCODE_IN_CBFS
config MMCONF_BASE_ADDRESS config MMCONF_BASE_ADDRESS
hex hex

2
src/soc/intel/denverton_ns/Makefile.inc
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@ -92,4 +92,6 @@ $(call strip_quotes,$(CONFIG_FSP_T_CBFS))-options := -b $(CONFIG_FSP_T_ADDR) --x
$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) --xip $(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) --xip
$(call strip_quotes,$(CONFIG_FSP_S_CBFS))-options := -b $(CONFIG_FSP_S_ADDR) --xip $(call strip_quotes,$(CONFIG_FSP_S_CBFS))-options := -b $(CONFIG_FSP_S_ADDR) --xip
cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5f-01
endif ## CONFIG_SOC_INTEL_DENVERTON_NS endif ## CONFIG_SOC_INTEL_DENVERTON_NS