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drivers/generic/bayhub_lv2: remove unnecessary configs

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coreboot sets up CLK_PM, ASPM, and L1ss automatically based on related
bits in "Link Capability Register" and "L1 PM Substates Capabilities
Register". coreboot overrides these configs even if the driver sets
them. Therefore, setting up CLK_PM, ASPM, and L1ss in the driver is
redundant and useless.

BUG=b:177955523
BRANCH=zork
TEST="lspci -vvvv" prints are identical with and without this patch;
LV2_LINK_CTRL(0x90) is 0x00110102 with and without this patch.

Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I17c19f4271da426ac2b926b948378dc88131e95a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Victor Ding
2021-02-18 07:25:08 +00:00
committed by Patrick Georgi
parent 9d1bf811fe
commit e0c2c06ba1
2 changed files with 1 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/drivers/generic/bayhub_lv2/lv2.c
View File

@@ -28,21 +28,15 @@ static void lv2_enable(struct device *dev)
pci_update_config32(dev, LV2_PCR_HEX_FC, LV2_ASPM_L1_TIMER_MASK, LV2_ASPM_L1_TIMER); pci_update_config32(dev, LV2_PCR_HEX_FC, LV2_ASPM_L1_TIMER_MASK, LV2_ASPM_L1_TIMER);
pci_or_config32(dev, LV2_PCR_HEX_A8, LV2_LTR_ENABLE); pci_or_config32(dev, LV2_PCR_HEX_A8, LV2_LTR_ENABLE);
pci_write_config32(dev, LV2_PCR_HEX_234, LV2_MAX_LATENCY_SETTING); pci_write_config32(dev, LV2_PCR_HEX_234, LV2_MAX_LATENCY_SETTING);
pci_update_config32(dev, LV2_PCR_HEX_248, LV2_L1_SUBSTATE_SETTING_MASK,
LV2_L1_SUBSTATE_SETTING);
pci_update_config32(dev, LV2_PCR_HEX_3F4, LV2_L1_SUBSTATE_OPTIMISE_MASK, pci_update_config32(dev, LV2_PCR_HEX_3F4, LV2_L1_SUBSTATE_OPTIMISE_MASK,
LV2_L1_SUBSTATE_OPTIMISE); LV2_L1_SUBSTATE_OPTIMISE);
pci_or_config32(dev, LV2_LINK_CTRL, LV2_LINK_CTRL_CLKREQ);
pci_update_config32(dev, LV2_PCR_HEX_300, LV2_TUNING_WINDOW_MASK, LV2_TUNING_WINDOW); pci_update_config32(dev, LV2_PCR_HEX_300, LV2_TUNING_WINDOW_MASK, LV2_TUNING_WINDOW);
pci_update_config32(dev, LV2_PCR_HEX_304, LV2_DRIVER_STRENGTH_MASK, pci_update_config32(dev, LV2_PCR_HEX_304, LV2_DRIVER_STRENGTH_MASK,
LV2_DRIVER_STRENGTH); LV2_DRIVER_STRENGTH);
pci_update_config32(dev, LV2_PCR_HEX_308, LV2_RESET_DMA_DISABLE_MASK, pci_update_config32(dev, LV2_PCR_HEX_308, LV2_RESET_DMA_DISABLE_MASK,
LV2_RESET_DMA_DISABLE); LV2_RESET_DMA_DISABLE);
pci_update_config32(dev, LV2_LINK_CTRL, LV2_LINK_CTRL_L1_L0_MASK,
LV2_LINK_CTRL_L1_ENABLE);
pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_ON | LV2_PROTECT_LOCK_ON); pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_ON | LV2_PROTECT_LOCK_ON);
printk(BIOS_INFO, "BayHub LV2: Power-saving enabled (link_ctrl=%#x)\n", printk(BIOS_INFO, "BayHub LV2: Power-saving enabled\n");
pci_read_config32(dev, LV2_LINK_CTRL));
} }
static struct device_operations lv2_ops = { static struct device_operations lv2_ops = {

7
src/drivers/generic/bayhub_lv2/lv2.h
View File

@@ -21,9 +21,6 @@ enum {
LV2_PCI_PM_L1_TIMER_MASK = 0x0FFFFFFF, LV2_PCI_PM_L1_TIMER_MASK = 0x0FFFFFFF,
LV2_PCR_HEX_234 = 0x234, LV2_PCR_HEX_234 = 0x234,
LV2_MAX_LATENCY_SETTING = 0x10011001, LV2_MAX_LATENCY_SETTING = 0x10011001,
LV2_PCR_HEX_248 = 0x248,
LV2_L1_SUBSTATE_SETTING = 0x0000000A,
LV2_L1_SUBSTATE_SETTING_MASK = 0xFFFFFFF0,
LV2_PCR_HEX_3F4 = 0x3F4, LV2_PCR_HEX_3F4 = 0x3F4,
LV2_L1_SUBSTATE_OPTIMISE = 0x0000000A, LV2_L1_SUBSTATE_OPTIMISE = 0x0000000A,
LV2_L1_SUBSTATE_OPTIMISE_MASK = 0xFFFFFFF0, LV2_L1_SUBSTATE_OPTIMISE_MASK = 0xFFFFFFF0,
@@ -36,8 +33,4 @@ enum {
LV2_PCR_HEX_308 = 0x308, LV2_PCR_HEX_308 = 0x308,
LV2_RESET_DMA_DISABLE = 0x00C00000, LV2_RESET_DMA_DISABLE = 0x00C00000,
LV2_RESET_DMA_DISABLE_MASK = 0xFF3FFFFF, LV2_RESET_DMA_DISABLE_MASK = 0xFF3FFFFF,
LV2_LINK_CTRL = 0x90,
LV2_LINK_CTRL_L1_ENABLE = BIT(1),
LV2_LINK_CTRL_L1_L0_MASK = 0xFFFFFFFC,
LV2_LINK_CTRL_CLKREQ = BIT(8),
}; };