soc/amd/sabrina/i2c: handle all I2C pads as I23C pad type

Contradicting the PPR #57243 version 1.56, the I2C3 pad control register
in the MISC ACPIMMIO region is the same new I23C pad type as the
corresponding registers for I2C0..2 and not the older I2C pad control
register type used on Picasso and Cezanne. All I2C pads being of the new
I23C type is in line with the GPIOMUX settings for the pins used by
I2C0..3 that can alternatively connect the pins to an I3C controller.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I51b0ddf8ba2ccfee823e3d4d26a77b11825b1029
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63233
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held
2022-03-31 01:29:32 +02:00
parent 3363db0173
commit e0c738c3df
2 changed files with 1 additions and 7 deletions

View File

@@ -53,7 +53,6 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_I2C
select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL
select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL
select SOC_AMD_COMMON_BLOCK_IOMMU
select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct

View File

@@ -39,12 +39,7 @@ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
if (bus >= ARRAY_SIZE(config->i2c_pad))
return;
/* The I/O pads of I2C0..2 are the new I23C pads and the I/O pads of I2C3 still are the
same I2C pads as in Picasso and Cezanne. */
if (bus <= 2)
fch_i23c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]);
else
fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]);
}
const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)