Sync addw2 and gaze15 with oryp6

Change-Id: Ifb117d95d98c42a8ed0004e66b822df947e610ba

src/mainboard/system76/addw2/acpi/dgpu.asl

@@ -24,45 +24,183 @@
 
 #define DGPU_RST_N GPP_F22
 #define DGPU_PWR_EN GPP_F23
+#define DGPU_GC6 GPP_C12
 
-Scope (\_SB.PCI0.PEGP.DEV0)
+Device (\_SB.PCI0.PEGP.DEV0)
 {
+	Name(_ADR, 0x00000000)
+	Name (LTRE, 0)
+
+	// Memory mapped PCI express registers
+	// Not sure what this stuff is, but it is used to get into GC6
+	OperationRegion (RPCX, SystemMemory, 0xE0008000, 0x1000)
+	Field (RPCX, ByteAcc, NoLock, Preserve)
+	{
+		PVID,   16,
+		PDID,   16,
+		CMDR,   8,
+		Offset (0x19),
+		PRBN,   8,
+		Offset (0x84),
+		D0ST,   2,
+		Offset (0xAA),
+		CEDR,   1,
+		Offset (0xAC),
+			,   4,
+		CMLW,   6,
+		Offset (0xB0),
+		ASPM,   2,
+			,   2,
+		P0LD,   1,
+		RTLK,   1,
+		Offset (0xC9),
+			,   2,
+		LREN,   1,
+		Offset (0x11A),
+			,   1,
+		VCNP,   1,
+		Offset (0x214),
+		Offset (0x216),
+		P0LS,   4,
+		Offset (0x248),
+			,   7,
+		Q0L2,   1,
+		Q0L0,   1,
+		Offset (0x504),
+		Offset (0x506),
+		PCFG,   2,
+		Offset (0x508),
+		TREN,   1,
+		Offset (0xC20),
+			,   4,
+		P0AP,   2,
+		Offset (0xC38),
+			,   3,
+		P0RM,   1,
+		Offset (0xC74),
+		P0LT,   4,
+		Offset (0xD0C),
+			,   20,
+		LREV,   1
+	}
+
+	Name (_STA, 0xF)
+
 	Method (_ON)
 	{
 		Debug = "PEGP.DEV0._ON"
-		If (! GTXS (DGPU_PWR_EN)) {
+
-			Debug = "DGPU reset start"
+		If (_STA != 0xF) {
-			CTXS (DGPU_RST_N)
+			Debug = "  If DGPU_PWR_EN low"
-			Debug = "DGPU power enable"
+			If (! GTXS (DGPU_PWR_EN)) {
-			STXS (DGPU_PWR_EN)
+				Debug = "  DGPU_PWR_EN high"
-			Sleep (4)
+				STXS (DGPU_PWR_EN)
-			Debug = "DGPU reset finish"
+
-			STXS (DGPU_RST_N)
+				Debug = "  Sleep 16"
-			Sleep (50)
+				Sleep (16)
+			}
+
+			Debug = "  DGPU_RST_N high"
+			STXS(DGPU_RST_N)
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  Q0L0 = 1"
+			Q0L0 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L0"
+			Local0 = 0
+			While (Q0L0) {
+				If ((Local0 > 4)) {
+					Debug = "  While Q0L0 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 0"
+			P0RM = 0
+
+			Debug = "  P0AP = 0"
+			P0AP = 0
+
+			Debug = Concatenate("  LREN = ", ToHexString(LTRE))
+			LREN = LTRE
+
+			Debug = "  CEDR = 1"
+			CEDR = 1
+
+			Debug = "  CMDR |= 7"
+			CMDR |= 7
+
+			//TODO: restore subsystem ID
+
+			Debug = "  _STA = 0xF"
+			_STA = 0xF
 		}
 	}
 
 	Method (_OFF)
 	{
 		Debug = "PEGP.DEV0._OFF"
-		If (GTXS (DGPU_PWR_EN)) {
-			Debug = "DGPU reset start"
-			CTXS (DGPU_RST_N)
-			Sleep (4)
-			Debug = "DGPU power disable"
-			CTXS (DGPU_PWR_EN)
-			Sleep (50)
-		}
-	}
 
-	Method (_STA)
+		If (_STA != 0x5) {
-	{
+			Debug = Concatenate("  LTRE = ", ToHexString(LREN))
-		If (GTXS (DGPU_PWR_EN)) {
+			LTRE = LREN
-			Debug = "PEGP.DEV0._STA F"
+
-			Return (0xF)
+			Debug = "  Q0L2 = 1"
-		} Else {
+			Q0L2 = 1
-			Debug = "PEGP.DEV0._STA 5"
+
-			Return (0x5)
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L2"
+			Local0 = Zero
+			While (Q0L2) {
+				If ((Local0 > 4)) {
+					Debug = "  While Q0L2 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 1"
+			P0RM = 1
+
+			Debug = "  P0AP = 3"
+			P0AP = 3
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  DGPU_RST_N low"
+			CTXS(DGPU_RST_N)
+
+			Debug = "  While DGPU_GC6 low"
+			Local0 = Zero
+			While (! GRXS(DGPU_GC6)) {
+				If ((Local0 > 4)) {
+					Debug = "  While DGPU_GC6 low timeout"
+
+					Debug = "  DGPU_PWR_EN low"
+					CTXS (DGPU_PWR_EN)
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  _STA = 0x5"
+			_STA = 0x5
 		}
 	}
 }

src/mainboard/system76/addw2/acpi/pegp.asl

@@ -4,40 +4,7 @@
 Device (PEGP)
 {
 	Name (_ADR, 0x00010000)
-
+	Name (_STA, 0xF)
-	OperationRegion (PEGC, PCI_Config, 0x00, 0x0100)
-	Field (PEGC, AnyAcc, NoLock, Preserve)
-	{
-	Offset (0x04),	// Device Command; Primary Status
-		PCMR, 8,	// SC, BM, Mem and I/O bitmask
-/*	Offset (0x4a),	// Device Control; Device Status
-		CEDR, 1,	// Correctable Error Detected	*/
-	Offset (0x50),	// Link Control; Link Status
-		ASPM, 2,	// ASPM Control
-		    , 2,
-		LNKD, 1,	// Link Disable
-		RTRL, 1,	// Retrain Link
-		    , 21,
-		LNKT, 1,	// Link Training
-	Offset (0x69),	// Device Control 2; Device Status 2
-		    , 2,
-		LREN, 1,	// LTR Enable
-/*	Offset (0x80),	// MSI Control
-		    , 16,
-		MSIE, 1,	// MSI enable	*/
-	Offset (0xa4),	// Power Management
-		PMST, 2,	// Power State
-/*	Offset (0x328),
-		    , 19,
-		LNKS, 4,	// Link Status?	*/
-	}
-
-	OperationRegion (PCAP, PCI_Config, 0x40, 0x14)
-	Field (PCAP, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x10),
-		LCTL, 16,	// Link Control
-	}
 
 	PowerResource (PWRR, 0, 0)
 	{
@@ -46,18 +13,19 @@ Device (PEGP)
 		Method (_ON)
 		{
 			Debug = "PEGP.PWRR._ON"
-			\_SB.PCI0.PEGP._ON ()
+			If (_STA != 1) {
-			PCMR = 0x07	// Bus Master, Memory and I/O space enabled
+				\_SB.PCI0.PEGP._ON ()
-			PMST = 0	// Power state: D0
+				_STA = 1
-//			MSIE = 1	// Enable MSI interrupts
+			}
-			_STA = 1
 		}
 
 		Method (_OFF)
 		{
 			Debug = "PEGP.PWRR._OFF"
-			\_SB.PCI0.PEGP._OFF ()
+			If (_STA != 0) {
-			_STA = 0
+				\_SB.PCI0.PEGP._OFF ()
+				_STA = 0
+			}
 		}
 	}
 
@@ -68,97 +36,37 @@ Device (PEGP)
 	Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR })
 	Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR })
 
+	Name (_PSC, 0)
+
 	Method (_PS0)
 	{
 		Debug = "PEGP._PS0"
-		LNKD = 0
+		_PSC = 0
-		RTRL = 1
-
-		Local1 = 0x32
-		While (Local1)
-		{
-			Sleep (2)
-			If (LNKT == 0)
-			{
-				Break
-			}
-
-			Local1--
-		}
 	}
 
 	Method (_PS3)
 	{
 		Debug = "PEGP._PS3"
-		LNKD = 1
+		_PSC = 3
-	}
-
-	Method (_PSC, 0, Serialized)
-	{
-		If (LNKD == 1)
-		{
-		    Debug = "PEGP._PSC 3"
-			Return (3)
-		}
-		Else
-		{
-		    Debug = "PEGP._PSC 0"
-			Return (0)
-		}
 	}
 
 	Method (_ON)
 	{
 		Debug = "PEGP._ON"
-		If (^DEV0.ONOF == 0)
+		If (_STA != 0xF)
 		{
-			^DEV0.ONOF = 1
 			^DEV0._ON ()
-			LREN = ^DEV0.LTRE	// Restore LTR enable bit
+			_STA = 0xF
-//			CEDR = 1
-			// Restore the Link Control register
-			LCTL = ((^DEV0.ELCT & 0x43) | (LCTL & 0xFFBC))
-			//Notify (\_SB.PCI0, 0)	// Bus Check
 		}
 	}
 
 	Method (_OFF)
 	{
 		Debug = "PEGP._OFF"
-		If (^DEV0.ONOF == 1)
+		If (_STA != 0x5)
 		{
-			^DEV0.ONOF = 0
-			^DEV0.ELCT = LCTL	// Save the Link Control register
-			^DEV0.LTRE = LREN	// Save LTR enable bit
 			^DEV0._OFF ()
-			//Notify (\_SB.PCI0, 0)	// Bus Check
+			_STA = 0x5
 		}
 	}
-
-	Method (_STA)
-	{
-		If (^DEV0.ONOF)
-		{
-		    Debug = "PEGP._STA F"
-			Return (0xF)
-		}
-		Else
-		{
-		    Debug = "PEGP._STA 5"
-			Return (0x5)
-		}
-	}
-
-	Device (DEV0)
-	{
-		Name(_ADR, 0x00000000)
-		Name (ONOF, 1)
-		Name (ELCT, 0)
-		Name (LTRE, 0)
-	}
-
-	Device (DEV1)
-	{
-		Name(_ADR, 0x00000001)
-	}
 }

src/mainboard/system76/addw2/devicetree.cb

@@ -188,9 +188,17 @@ chip soc/intel/cannonlake
 	#register "satapwroptimize" = "1"
 
 	# Power
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 11:10
+	# WARNING: must then be mapped from FSP value to PCH value
 	register "PchPmSlpS3MinAssert" = "3" # 50ms
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 5:4
+	# WARNING: must then be mapped from FSP value to PCH value
 	register "PchPmSlpS4MinAssert" = "1" # 1s
-	register "PchPmSlpSusMinAssert" = "2" # 500ms
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 19:18
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpSusMinAssert" = "4" # 4s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 17:16
+	# WARNING: must then be mapped from FSP value to PCH value
 	register "PchPmSlpAMinAssert" = "4" # 2s
 
 	# Thermal

src/mainboard/system76/addw2/gpio.h

@@ -93,7 +93,7 @@ static const struct pad_config gpio_table[] = {
 		PAD_CFG_GPI(GPP_C9, NONE, DEEP),
 		PAD_CFG_GPI(GPP_C10, NONE, DEEP),
 		PAD_CFG_GPI(GPP_C11, NONE, DEEP), // TBT_DET#
-		PAD_CFG_GPI(GPP_C12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH
 		PAD_CFG_GPI(GPP_C13, NONE, PLTRST),
 		PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP),
 		PAD_CFG_GPI(GPP_C15, NONE, DEEP),

src/mainboard/system76/gaze15/acpi/dgpu.asl

@@ -24,45 +24,183 @@
 
 #define DGPU_RST_N GPP_F22
 #define DGPU_PWR_EN GPP_F23
+#define DGPU_GC6 GPP_K21
 
-Scope (\_SB.PCI0.PEGP.DEV0)
+Device (\_SB.PCI0.PEGP.DEV0)
 {
+	Name(_ADR, 0x00000000)
+	Name (LTRE, 0)
+
+	// Memory mapped PCI express registers
+	// Not sure what this stuff is, but it is used to get into GC6
+	OperationRegion (RPCX, SystemMemory, 0xE0008000, 0x1000)
+	Field (RPCX, ByteAcc, NoLock, Preserve)
+	{
+		PVID,   16,
+		PDID,   16,
+		CMDR,   8,
+		Offset (0x19),
+		PRBN,   8,
+		Offset (0x84),
+		D0ST,   2,
+		Offset (0xAA),
+		CEDR,   1,
+		Offset (0xAC),
+			,   4,
+		CMLW,   6,
+		Offset (0xB0),
+		ASPM,   2,
+			,   2,
+		P0LD,   1,
+		RTLK,   1,
+		Offset (0xC9),
+			,   2,
+		LREN,   1,
+		Offset (0x11A),
+			,   1,
+		VCNP,   1,
+		Offset (0x214),
+		Offset (0x216),
+		P0LS,   4,
+		Offset (0x248),
+			,   7,
+		Q0L2,   1,
+		Q0L0,   1,
+		Offset (0x504),
+		Offset (0x506),
+		PCFG,   2,
+		Offset (0x508),
+		TREN,   1,
+		Offset (0xC20),
+			,   4,
+		P0AP,   2,
+		Offset (0xC38),
+			,   3,
+		P0RM,   1,
+		Offset (0xC74),
+		P0LT,   4,
+		Offset (0xD0C),
+			,   20,
+		LREV,   1
+	}
+
+	Name (_STA, 0xF)
+
 	Method (_ON)
 	{
 		Debug = "PEGP.DEV0._ON"
-		If (! GTXS (DGPU_PWR_EN)) {
+
-			Debug = "DGPU reset start"
+		If (_STA != 0xF) {
-			CTXS (DGPU_RST_N)
+			Debug = "  If DGPU_PWR_EN low"
-			Debug = "DGPU power enable"
+			If (! GTXS (DGPU_PWR_EN)) {
-			STXS (DGPU_PWR_EN)
+				Debug = "  DGPU_PWR_EN high"
-			Sleep (4)
+				STXS (DGPU_PWR_EN)
-			Debug = "DGPU reset finish"
+
-			STXS (DGPU_RST_N)
+				Debug = "  Sleep 16"
-			Sleep (50)
+				Sleep (16)
+			}
+
+			Debug = "  DGPU_RST_N high"
+			STXS(DGPU_RST_N)
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  Q0L0 = 1"
+			Q0L0 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L0"
+			Local0 = 0
+			While (Q0L0) {
+				If ((Local0 > 4)) {
+					Debug = "  While Q0L0 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 0"
+			P0RM = 0
+
+			Debug = "  P0AP = 0"
+			P0AP = 0
+
+			Debug = Concatenate("  LREN = ", ToHexString(LTRE))
+			LREN = LTRE
+
+			Debug = "  CEDR = 1"
+			CEDR = 1
+
+			Debug = "  CMDR |= 7"
+			CMDR |= 7
+
+			//TODO: restore subsystem ID
+
+			Debug = "  _STA = 0xF"
+			_STA = 0xF
 		}
 	}
 
 	Method (_OFF)
 	{
 		Debug = "PEGP.DEV0._OFF"
-		If (GTXS (DGPU_PWR_EN)) {
-			Debug = "DGPU reset start"
-			CTXS (DGPU_RST_N)
-			Sleep (4)
-			Debug = "DGPU power disable"
-			CTXS (DGPU_PWR_EN)
-			Sleep (50)
-		}
-	}
 
-	Method (_STA)
+		If (_STA != 0x5) {
-	{
+			Debug = Concatenate("  LTRE = ", ToHexString(LREN))
-		If (GTXS (DGPU_PWR_EN)) {
+			LTRE = LREN
-			Debug = "PEGP.DEV0._STA F"
+
-			Return (0xF)
+			Debug = "  Q0L2 = 1"
-		} Else {
+			Q0L2 = 1
-			Debug = "PEGP.DEV0._STA 5"
+
-			Return (0x5)
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L2"
+			Local0 = Zero
+			While (Q0L2) {
+				If ((Local0 > 4)) {
+					Debug = "  While Q0L2 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 1"
+			P0RM = 1
+
+			Debug = "  P0AP = 3"
+			P0AP = 3
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  DGPU_RST_N low"
+			CTXS(DGPU_RST_N)
+
+			Debug = "  While DGPU_GC6 low"
+			Local0 = Zero
+			While (! GRXS(DGPU_GC6)) {
+				If ((Local0 > 4)) {
+					Debug = "  While DGPU_GC6 low timeout"
+
+					Debug = "  DGPU_PWR_EN low"
+					CTXS (DGPU_PWR_EN)
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  _STA = 0x5"
+			_STA = 0x5
 		}
 	}
 }

src/mainboard/system76/gaze15/acpi/pegp.asl

@@ -4,40 +4,7 @@
 Device (PEGP)
 {
 	Name (_ADR, 0x00010000)
-
+	Name (_STA, 0xF)
-	OperationRegion (PEGC, PCI_Config, 0x00, 0x0100)
-	Field (PEGC, AnyAcc, NoLock, Preserve)
-	{
-	Offset (0x04),	// Device Command; Primary Status
-		PCMR, 8,	// SC, BM, Mem and I/O bitmask
-/*	Offset (0x4a),	// Device Control; Device Status
-		CEDR, 1,	// Correctable Error Detected	*/
-	Offset (0x50),	// Link Control; Link Status
-		ASPM, 2,	// ASPM Control
-		    , 2,
-		LNKD, 1,	// Link Disable
-		RTRL, 1,	// Retrain Link
-		    , 21,
-		LNKT, 1,	// Link Training
-	Offset (0x69),	// Device Control 2; Device Status 2
-		    , 2,
-		LREN, 1,	// LTR Enable
-/*	Offset (0x80),	// MSI Control
-		    , 16,
-		MSIE, 1,	// MSI enable	*/
-	Offset (0xa4),	// Power Management
-		PMST, 2,	// Power State
-/*	Offset (0x328),
-		    , 19,
-		LNKS, 4,	// Link Status?	*/
-	}
-
-	OperationRegion (PCAP, PCI_Config, 0x40, 0x14)
-	Field (PCAP, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x10),
-		LCTL, 16,	// Link Control
-	}
 
 	PowerResource (PWRR, 0, 0)
 	{
@@ -46,18 +13,19 @@ Device (PEGP)
 		Method (_ON)
 		{
 			Debug = "PEGP.PWRR._ON"
-			\_SB.PCI0.PEGP._ON ()
+			If (_STA != 1) {
-			PCMR = 0x07	// Bus Master, Memory and I/O space enabled
+				\_SB.PCI0.PEGP._ON ()
-			PMST = 0	// Power state: D0
+				_STA = 1
-//			MSIE = 1	// Enable MSI interrupts
+			}
-			_STA = 1
 		}
 
 		Method (_OFF)
 		{
 			Debug = "PEGP.PWRR._OFF"
-			\_SB.PCI0.PEGP._OFF ()
+			If (_STA != 0) {
-			_STA = 0
+				\_SB.PCI0.PEGP._OFF ()
+				_STA = 0
+			}
 		}
 	}
 
@@ -68,97 +36,37 @@ Device (PEGP)
 	Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR })
 	Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR })
 
+	Name (_PSC, 0)
+
 	Method (_PS0)
 	{
 		Debug = "PEGP._PS0"
-		LNKD = 0
+		_PSC = 0
-		RTRL = 1
-
-		Local1 = 0x32
-		While (Local1)
-		{
-			Sleep (2)
-			If (LNKT == 0)
-			{
-				Break
-			}
-
-			Local1--
-		}
 	}
 
 	Method (_PS3)
 	{
 		Debug = "PEGP._PS3"
-		LNKD = 1
+		_PSC = 3
-	}
-
-	Method (_PSC, 0, Serialized)
-	{
-		If (LNKD == 1)
-		{
-		    Debug = "PEGP._PSC 3"
-			Return (3)
-		}
-		Else
-		{
-		    Debug = "PEGP._PSC 0"
-			Return (0)
-		}
 	}
 
 	Method (_ON)
 	{
 		Debug = "PEGP._ON"
-		If (^DEV0.ONOF == 0)
+		If (_STA != 0xF)
 		{
-			^DEV0.ONOF = 1
 			^DEV0._ON ()
-			LREN = ^DEV0.LTRE	// Restore LTR enable bit
+			_STA = 0xF
-//			CEDR = 1
-			// Restore the Link Control register
-			LCTL = ((^DEV0.ELCT & 0x43) | (LCTL & 0xFFBC))
-			//Notify (\_SB.PCI0, 0)	// Bus Check
 		}
 	}
 
 	Method (_OFF)
 	{
 		Debug = "PEGP._OFF"
-		If (^DEV0.ONOF == 1)
+		If (_STA != 0x5)
 		{
-			^DEV0.ONOF = 0
-			^DEV0.ELCT = LCTL	// Save the Link Control register
-			^DEV0.LTRE = LREN	// Save LTR enable bit
 			^DEV0._OFF ()
-			//Notify (\_SB.PCI0, 0)	// Bus Check
+			_STA = 0x5
 		}
 	}
-
-	Method (_STA)
-	{
-		If (^DEV0.ONOF)
-		{
-		    Debug = "PEGP._STA F"
-			Return (0xF)
-		}
-		Else
-		{
-		    Debug = "PEGP._STA 5"
-			Return (0x5)
-		}
-	}
-
-	Device (DEV0)
-	{
-		Name(_ADR, 0x00000000)
-		Name (ONOF, 1)
-		Name (ELCT, 0)
-		Name (LTRE, 0)
-	}
-
-	Device (DEV1)
-	{
-		Name(_ADR, 0x00000001)
-	}
 }

src/mainboard/system76/gaze15/devicetree.cb

@@ -177,9 +177,17 @@ chip soc/intel/cannonlake
 	#register "satapwroptimize" = "1"
 
 	# Power
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 11:10
+	# WARNING: must then be mapped from FSP value to PCH value
 	register "PchPmSlpS3MinAssert" = "3" # 50ms
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 5:4
+	# WARNING: must then be mapped from FSP value to PCH value
 	register "PchPmSlpS4MinAssert" = "1" # 1s
-	register "PchPmSlpSusMinAssert" = "2" # 500ms
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 19:18
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpSusMinAssert" = "4" # 4s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 17:16
+	# WARNING: must then be mapped from FSP value to PCH value
 	register "PchPmSlpAMinAssert" = "4" # 2s
 
 	# Thermal

src/mainboard/system76/gaze15/gpio.h

@@ -246,7 +246,7 @@ static const struct pad_config gpio_table[] = {
 		PAD_CFG_GPI(GPP_K18, NONE, DEEP),
 		PAD_CFG_GPI(GPP_K19, NONE, DEEP),
 		PAD_CFG_TERM_GPO(GPP_K20, 1, NONE, DEEP),
-		PAD_CFG_GPI(GPP_K21, NONE, PLTRST),
+		PAD_CFG_GPI(GPP_K21, NONE, PLTRST), // GC6_FB_EN_PCH
 		PAD_CFG_GPI(GPP_K22, NONE, DEEP),
 		PAD_CFG_GPI(GPP_K23, NONE, DEEP),
 };