From e119d86ca87937d45e67d00da722c28ac7ceaa9e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 3 Aug 2019 21:28:40 +0300 Subject: [PATCH] intel/fsp_rangeley: Rename raminit.c to memmap.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use a name consistent with the more recent soc/intel. Change-Id: I704d7cb637e4e12039ade99f57e10af794c8be97 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34698 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: David Guckian --- src/northbridge/intel/fsp_rangeley/Makefile.inc | 4 ++-- src/northbridge/intel/fsp_rangeley/{raminit.c => memmap.c} | 0 2 files changed, 2 insertions(+), 2 deletions(-) rename src/northbridge/intel/fsp_rangeley/{raminit.c => memmap.c} (100%) diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc index f9bf0507dc..a2f80546d7 100644 --- a/src/northbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/northbridge/intel/fsp_rangeley/Makefile.inc @@ -18,12 +18,12 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY),y) subdirs-y += fsp ramstage-y += northbridge.c -ramstage-y += raminit.c +ramstage-y += memmap.c ramstage-y += acpi.c ramstage-y += port_access.c -romstage-y += raminit.c +romstage-y += memmap.c romstage-y += ../../../arch/x86/walkcbfs.S romstage-y += port_access.c diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/memmap.c similarity index 100% rename from src/northbridge/intel/fsp_rangeley/raminit.c rename to src/northbridge/intel/fsp_rangeley/memmap.c