Remove AMD special case for LAPIC based udelay()

- Optionally override FSB clock detection in generic
  LAPIC code with constant value.
- Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz
- compile LAPIC code for romstage, too
- Remove #include ".../apic_timer.c" in AMD based mainboards
- Remove custom udelay implementation from intel northbridges' romstages

Future work:
- remove the compile time special case
  (requires some cpuid based switching)
- drop northbridge udelay implementations (i945, i5000) if
  not required anymore (eg. can SMM use the LAPIC timer?)

Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1618
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/arch/x86/include/arch/cpu.h

@@ -138,6 +138,7 @@ static inline unsigned int cpuid_edx(unsigned int op)
 #define X86_VENDOR_SIS       10
 #define X86_VENDOR_UNKNOWN 0xff
 
+#if !defined(__ROMCC__)
 #if !defined(__PRE_RAM__)
 #include <device/device.h>
 
@@ -157,6 +158,10 @@ struct cpu_driver {
 
 struct device;
 struct cpu_driver *find_cpu_driver(struct device *cpu);
+#else
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#endif
 
 struct cpu_info {
 	device_t cpu;

src/cpu/amd/agesa/Kconfig

@@ -26,6 +26,7 @@ config CPU_AMD_AGESA
         default y if CPU_AMD_AGESA_FAMILY15_TN
         default n
 	select TSC_SYNC_LFENCE
+	select UDELAY_LAPIC
 
 if CPU_AMD_AGESA
 
@@ -44,6 +45,10 @@ config XIP_ROM_SIZE
 	  In order to execute romstage in place on the flash rom,
 	  more space is required to be set as write through caching.
 
+config UDELAY_LAPIC_FIXED_FSB
+	int
+	default 200
+
 source src/cpu/amd/agesa/family10/Kconfig
 source src/cpu/amd/agesa/family12/Kconfig
 source src/cpu/amd/agesa/family14/Kconfig

src/cpu/amd/agesa/Makefile.inc

@@ -24,5 +24,4 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
 
 romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c
 ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c
-ramstage-y += apic_timer.c
 cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc

src/cpu/amd/agesa/apic_timer.c

@@ -1,59 +0,0 @@
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- * ***************************************************************************
- *
- */
-
-#include <stdint.h>
-#include <delay.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
-
-/* NOTE: We use the APIC TIMER register is to hold flags for AP init during
- * pre-memory init (__PRE_RAM__). Don't use init_timer() and  udelay is
- * redirected to udelay_tsc().
- */
-
-
-void init_timer(void)
-{
-	/* Set the apic timer to no interrupts and periodic mode */
-	lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
-
-	/* Set the divider to 1, no divider */
-	lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
-
-	/* Set the initial counter to 0xffffffff */
-	lapic_write(LAPIC_TMICT, 0xffffffff);
-
-}
-
-
-void udelay(u32 usecs)
-{
-	u32 start, value, ticks;
-	/* Calculate the number of ticks to run, our FSB runs a 200Mhz */
-	ticks = usecs * 200;
-	start = lapic_read(LAPIC_TMCCT);
-	do {
-		value = lapic_read(LAPIC_TMCCT);
-	} while((start - value) < ticks);
-
-}

src/cpu/amd/model_10xxx/Kconfig

@@ -4,6 +4,7 @@ config CPU_AMD_MODEL_10XXX
 	select SSE2
 	select MMCONF_SUPPORT_DEFAULT
 	select TSC_SYNC_LFENCE
+	select UDELAY_LAPIC
 
 if CPU_AMD_MODEL_10XXX
 config CPU_ADDR_BITS
@@ -56,6 +57,10 @@ config SET_FIDVID_CORE_RANGE
 
 endif	# SET_FIDVID
 
+config UDELAY_LAPIC_FIXED_FSB
+	int
+	default 200
+
 config UPDATE_CPU_MICROCODE
 	bool
 	default y

src/cpu/amd/model_10xxx/Makefile.inc

@@ -1,4 +1,3 @@
 ramstage-y += model_10xxx_init.c
 ramstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c
-ramstage-y += apic_timer.c
 ramstage-y += processor_name.c

src/cpu/amd/model_10xxx/apic_timer.c

@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <stdint.h>
-#include <delay.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
-
-/* NOTE: We use the APIC TIMER register is to hold flags for AP init during
- * pre-memory init (__PRE_RAM__). Don't use init_timer() and  udelay is
- * redirected to udelay_tsc().
- */
-
-
-void init_timer(void)
-{
-	/* Set the apic timer to no interrupts and periodic mode */
-	lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
-
-	/* Set the divider to 1, no divider */
-	lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
-
-	/* Set the initial counter to 0xffffffff */
-	lapic_write(LAPIC_TMICT, 0xffffffff);
-
-}
-
-
-void udelay(u32 usecs)
-{
-	u32 start, value, ticks;
-	/* Calculate the number of ticks to run, our FSB runs a 200Mhz */
-	ticks = usecs * 200;
-	start = lapic_read(LAPIC_TMCCT);
-	do {
-		value = lapic_read(LAPIC_TMCCT);
-	} while((start - value) < ticks);
-
-}

src/cpu/amd/model_fxx/Kconfig

@@ -4,6 +4,7 @@ config CPU_AMD_MODEL_FXX
 	select SSE
 	select SSE2
 	select TSC_SYNC_LFENCE
+	select UDELAY_LAPIC
 
 if CPU_AMD_MODEL_FXX
 config UDELAY_IO
@@ -23,6 +24,10 @@ config HW_SCRUBBER
 	bool
 	default n
 
+config UDELAY_LAPIC_FIXED_FSB
+	int
+	default 200
+
 if SET_FIDVID
 config SET_FIDVID_DEBUG
 	bool

src/cpu/amd/model_fxx/Makefile.inc

@@ -1,6 +1,5 @@
 # no conditionals here. If you include this file from a socket, then you get all the binaries.
 ramstage-y += model_fxx_init.c
-ramstage-y += apic_timer.c
 ramstage-y += model_fxx_update_microcode.c
 ramstage-y += processor_name.c
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += powernow_acpi.c

src/cpu/amd/model_fxx/apic_timer.c

@@ -1,29 +0,0 @@
-#include <stdint.h>
-#include <delay.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
-
-void init_timer(void)
-{
-	/* Set the apic timer to no interrupts and periodic mode */
-	lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
-
-	/* Set the divider to 1, no divider */
-	lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
-
-	/* Set the initial counter to 0xffffffff */
-	lapic_write(LAPIC_TMICT, 0xffffffff);
-
-}
-
-void udelay(unsigned usecs)
-{
-	uint32_t start, value, ticks;
-	/* Calculate the number of ticks to run, our FSB runs a 200Mhz */
-	ticks = usecs * 200;
-	start = lapic_read(LAPIC_TMCCT);
-	do {
-		value = lapic_read(LAPIC_TMCCT);
-	} while((start - value) < ticks);
-
-}

src/cpu/x86/Kconfig

@@ -11,6 +11,9 @@ config UDELAY_LAPIC
 	bool
 	default n
 
+config UDELAY_LAPIC_FIXED_FSB
+	int
+
 config UDELAY_TSC
 	bool
 	default n

src/cpu/x86/lapic/Makefile.inc

@@ -1,5 +1,6 @@
 ramstage-y += lapic.c
 ramstage-y += lapic_cpu_init.c
 ramstage-y += secondary.S
+romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
 ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
 ramstage-y += boot_cpu.c

src/cpu/x86/lapic/apic_timer.c

@@ -20,7 +20,9 @@
 
 #include <stdint.h>
 #include <delay.h>
+#include <arch/io.h>
 #include <arch/cpu.h>
+#include <cpu/x86/car.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
 
@@ -28,7 +30,15 @@
  * memory init.
  */
 
-static u32 timer_fsb = 0;
+#if CONFIG_UDELAY_LAPIC_FIXED_FSB
+static const u32 timer_fsb = CONFIG_UDELAY_LAPIC_FIXED_FSB;
+
+static int set_timer_fsb(void)
+{
+	return 0;
+}
+#else
+static u32 timer_fsb CAR_GLOBAL = 0;
 
 static int set_timer_fsb(void)
 {
@@ -60,6 +70,7 @@ static int set_timer_fsb(void)
 
 	return 0;
 }
+#endif
 
 void init_timer(void)
 {

src/mainboard/amd/dbm690t/romstage.c

@@ -33,7 +33,6 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/amd/mahogany/romstage.c

@@ -34,7 +34,6 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/amd/pistachio/romstage.c

@@ -28,7 +28,6 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/amd/serengeti_cheetah/ap_romstage.c

@@ -14,7 +14,6 @@
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 
 #include "lib/delay.c"
 

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -15,7 +15,6 @@
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include <reset.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "cpu/x86/bist.h"
 #include "lib/delay.c"

src/mainboard/arima/hdama/romstage.c

@@ -10,7 +10,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"

src/mainboard/asrock/939a785gmh/romstage.c

@@ -34,7 +34,6 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <spd.h>
 #include "cpu/x86/lapic/boot_cpu.c"

src/mainboard/asus/a8n_e/romstage.c

@@ -40,7 +40,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"

src/mainboard/asus/a8v-e_deluxe/romstage.c

@@ -35,7 +35,6 @@ unsigned int get_sbdn(unsigned bus);
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/asus/a8v-e_se/romstage.c

@@ -35,7 +35,6 @@ unsigned int get_sbdn(unsigned bus);
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/asus/k8v-x/romstage.c

@@ -35,7 +35,6 @@ unsigned int get_sbdn(unsigned bus);
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/asus/m2n-e/romstage.c

@@ -37,7 +37,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <lib.h>
 #include <spd.h>

src/mainboard/asus/m2v-mx_se/romstage.c

@@ -40,7 +40,6 @@ unsigned int get_sbdn(unsigned bus);
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"

src/mainboard/asus/m2v/romstage.c

@@ -40,7 +40,6 @@ unsigned int get_sbdn(unsigned bus);
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"

src/mainboard/broadcom/blast/romstage.c

@@ -11,7 +11,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c

@@ -39,7 +39,6 @@
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 
 #include "lib/delay.c"
 

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -40,7 +40,6 @@
 #include "southbridge/sis/sis966/sis966.h"
 #include "southbridge/sis/sis966/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/gigabyte/m57sli/ap_romstage.c

@@ -37,7 +37,6 @@
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 
 #include "lib/delay.c"
 

src/mainboard/gigabyte/m57sli/romstage.c

@@ -37,7 +37,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/hp/dl145_g1/romstage.c

@@ -8,10 +8,10 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
+#include <delay.h>
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/early_serial.c"

src/mainboard/hp/dl145_g3/romstage.c

@@ -42,7 +42,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/hp/dl165_g6_fam10/romstage.c

@@ -44,7 +44,6 @@
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
 #include <spd.h>
-#include "cpu/amd/model_10xxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

src/mainboard/ibm/e325/romstage.c

@@ -11,7 +11,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"

src/mainboard/ibm/e326/romstage.c

@@ -11,7 +11,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"

src/mainboard/iwill/dk8_htx/romstage.c

@@ -14,7 +14,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "cpu/x86/bist.h"
 #include "lib/delay.c"

src/mainboard/iwill/dk8s2/romstage.c

@@ -14,7 +14,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "cpu/x86/bist.h"
 #include "lib/delay.c"

src/mainboard/iwill/dk8x/romstage.c

@@ -14,7 +14,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "cpu/x86/bist.h"
 #include "lib/delay.c"

src/mainboard/kontron/kt690/romstage.c

@@ -34,7 +34,6 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <spd.h>
 #include "cpu/x86/lapic/boot_cpu.c"

src/mainboard/msi/ms7135/romstage.c

@@ -38,7 +38,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"

src/mainboard/msi/ms7260/ap_romstage.c

@@ -34,7 +34,6 @@
 #include "console/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 /* #include "cpu/x86/lapic/boot_cpu.c" */
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/msi/ms7260/romstage.c

@@ -37,7 +37,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <lib.h>
 #include <spd.h>

src/mainboard/msi/ms9185/romstage.c

@@ -36,7 +36,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <reset.h>
 #include "cpu/x86/lapic/boot_cpu.c"

src/mainboard/msi/ms9282/romstage.c

@@ -34,7 +34,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -37,7 +37,6 @@
 #include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

src/mainboard/newisys/khepri/romstage.c

@@ -18,7 +18,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"

src/mainboard/nvidia/l1_2pvv/ap_romstage.c

@@ -36,7 +36,6 @@
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 
 #include "lib/delay.c"
 

src/mainboard/nvidia/l1_2pvv/romstage.c

@@ -38,7 +38,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/siemens/sitemp_g1p1/romstage.c

@@ -40,7 +40,6 @@
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
 #include "cpu/x86/lapic/boot_cpu.c"

src/mainboard/sunw/ultra40/romstage.c

@@ -13,7 +13,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/supermicro/h8dme/ap_romstage.c

@@ -37,7 +37,6 @@
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 
 #include "lib/delay.c"
 

src/mainboard/supermicro/h8dme/romstage.c

@@ -35,7 +35,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/supermicro/h8dmr/ap_romstage.c

@@ -37,7 +37,6 @@
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 
 #include "lib/delay.c"
 

src/mainboard/supermicro/h8dmr/romstage.c

@@ -38,7 +38,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -37,7 +37,6 @@
 #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#include "cpu/amd/model_10xxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -37,7 +37,6 @@
 #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#include "cpu/amd/model_10xxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

src/mainboard/technexion/tim5690/romstage.c

@@ -33,7 +33,6 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <spd.h>
 #include "cpu/x86/lapic/boot_cpu.c"

src/mainboard/technexion/tim8690/romstage.c

@@ -33,7 +33,6 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <spd.h>
 #include "cpu/x86/lapic/boot_cpu.c"

src/mainboard/tyan/s2850/romstage.c

@@ -13,7 +13,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"

src/mainboard/tyan/s2875/romstage.c

@@ -13,7 +13,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"

src/mainboard/tyan/s2880/romstage.c

@@ -13,7 +13,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"

src/mainboard/tyan/s2881/romstage.c

@@ -12,7 +12,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"

src/mainboard/tyan/s2882/romstage.c

@@ -13,7 +13,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"

src/mainboard/tyan/s2885/romstage.c

@@ -12,7 +12,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"

src/mainboard/tyan/s2891/romstage.c

@@ -13,7 +13,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/tyan/s2892/romstage.c

@@ -13,7 +13,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/tyan/s2895/romstage.c

@@ -13,7 +13,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/tyan/s2912/ap_romstage.c

@@ -33,7 +33,6 @@
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 
 #include "lib/delay.c"
 

src/mainboard/tyan/s2912/romstage.c

@@ -38,7 +38,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

src/mainboard/tyan/s2912_fam10/romstage.c

@@ -37,7 +37,6 @@
 #include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#include "cpu/amd/model_10xxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

src/mainboard/tyan/s4880/romstage.c

@@ -12,7 +12,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"

src/mainboard/tyan/s4882/romstage.c

@@ -11,7 +11,6 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"

src/northbridge/intel/i5000/Makefile.inc

@@ -18,5 +18,5 @@
 #
 
 ramstage-y += northbridge.c
-romstage-y += raminit.c udelay.c
+romstage-y += raminit.c
 cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S

src/northbridge/intel/i945/Makefile.inc

@@ -21,7 +21,6 @@ ramstage-y += northbridge.c
 ramstage-y += gma.c
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
 
-romstage-y += udelay.c
 romstage-y += raminit.c
 romstage-y += early_init.c
 romstage-y += errata.c

src/northbridge/intel/sandybridge/Makefile.inc

@@ -23,7 +23,6 @@ ramstage-y += gma.c
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
 ramstage-y += mrccache.c
 
-romstage-y += udelay.c
 romstage-y += raminit.c
 romstage-y += mrccache.c
 romstage-y += early_init.c