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Clean up #ifs

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Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +

Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +

Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +

Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +

(and some manual changes to fix false positives)

Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
This commit is contained in:
Patrick Georgi
2012-05-05 15:29:32 +02:00
committed by Stefan Reinauer
parent fe4221848f
commit e166782f39
337 changed files with 702 additions and 702 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/x86/boot/acpi.c
View File

@ -550,7 +550,7 @@ void acpi_write_hest(acpi_hest_t *hest)
header->checksum = acpi_checksum((void *)hest, header->length);
}
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
void suspend_resume(void)
{
void *wake_vec;

2
src/arch/x86/boot/coreboot_table.c
View File

@ -324,7 +324,7 @@ static void lb_strings(struct lb_header *header)
}
#if CONFIG_WRITE_HIGH_TABLES == 1
#if CONFIG_WRITE_HIGH_TABLES
static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header)
{
struct lb_record *rec;

6
src/arch/x86/boot/tables.c
View File

@ -71,7 +71,7 @@ struct lb_memory *write_tables(void)
low_table_start = 0;
low_table_end = 0x500;
#if CONFIG_GENERATE_PIRQ_TABLE == 1
#if CONFIG_GENERATE_PIRQ_TABLE
#define MAX_PIRQ_TABLE_SIZE (4 * 1024)
post_code(0x9a);
@ -97,7 +97,7 @@ struct lb_memory *write_tables(void)
#endif
#if CONFIG_GENERATE_MP_TABLE == 1
#if CONFIG_GENERATE_MP_TABLE
#define MAX_MP_TABLE_SIZE (4 * 1024)
post_code(0x9b);
@ -120,7 +120,7 @@ struct lb_memory *write_tables(void)
}
#endif /* CONFIG_GENERATE_MP_TABLE */
#if CONFIG_GENERATE_ACPI_TABLES == 1
#if CONFIG_GENERATE_ACPI_TABLES
#define MAX_ACPI_SIZE (45 * 1024)
post_code(0x9c);

2
src/arch/x86/include/arch/acpi.h
View File

@ -27,7 +27,7 @@
#ifndef __ASM_ACPI_H
#define __ASM_ACPI_H
#if CONFIG_GENERATE_ACPI_TABLES==1
#if CONFIG_GENERATE_ACPI_TABLES
#include <stdint.h>

2
src/arch/x86/include/arch/pci_ops.h
View File

@ -4,7 +4,7 @@
extern const struct pci_bus_operations pci_cf8_conf1;
extern const struct pci_bus_operations pci_cf8_conf2;
#if CONFIG_MMCONF_SUPPORT==1
#if CONFIG_MMCONF_SUPPORT
extern const struct pci_bus_operations pci_ops_mmconf;
#endif

2
src/arch/x86/include/arch/pciconf.h
View File

@ -5,7 +5,7 @@
#define PCI_CONF_REG_INDEX 0xcf8
#define PCI_CONF_REG_DATA 0xcfc
#if CONFIG_PCI_IO_CFG_EXT == 0
#if !CONFIG_PCI_IO_CFG_EXT
#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where))
#else
#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where & 0xff) | ((where & 0xf00)<<16) )

4
src/arch/x86/include/arch/pirq_routing.h
View File

@ -1,7 +1,7 @@
#ifndef ARCH_PIRQ_ROUTING_H
#define ARCH_PIRQ_ROUTING_H
#if CONFIG_GENERATE_PIRQ_TABLE==1
#if CONFIG_GENERATE_PIRQ_TABLE
#include <stdint.h>
#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
@ -39,7 +39,7 @@ extern const struct irq_routing_table intel_irq_routing_table;
unsigned long copy_pirq_routing_table(unsigned long start);
unsigned long write_pirq_routing_table(unsigned long start);
#if CONFIG_PIRQ_ROUTE==1
#if CONFIG_PIRQ_ROUTE
void pirq_routing_irqs(unsigned long start);
void pirq_assign_irqs(const unsigned char pIntAtoD[4]);
#else

12
src/arch/x86/include/arch/romcc_io.h
View File

@ -65,7 +65,7 @@ typedef unsigned device_t; /* pci and pci_mmio need to have different ways to ha
static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where)
{
unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0
#if !CONFIG_PCI_IO_CFG_EXT
addr = (dev>>4) | where;
#else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0
@ -94,7 +94,7 @@ static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t d
static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where)
{
unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0
#if !CONFIG_PCI_IO_CFG_EXT
addr = (dev>>4) | where;
#else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@ -125,7 +125,7 @@ static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t
static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where)
{
unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0
#if !CONFIG_PCI_IO_CFG_EXT
addr = (dev>>4) | where;
#else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@ -155,7 +155,7 @@ static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t
static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value)
{
unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0
#if !CONFIG_PCI_IO_CFG_EXT
addr = (dev>>4) | where;
#else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@ -186,7 +186,7 @@ static inline __attribute__((always_inline)) void pci_write_config8(device_t dev
static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value)
{
unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0
#if !CONFIG_PCI_IO_CFG_EXT
addr = (dev>>4) | where;
#else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@ -217,7 +217,7 @@ static inline __attribute__((always_inline)) void pci_write_config16(device_t de
static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value)
{
unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0
#if !CONFIG_PCI_IO_CFG_EXT
addr = (dev>>4) | where;
#else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);

2
src/arch/x86/lib/cbfs_and_run.c
View File

@ -50,7 +50,7 @@ void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset)
cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset);
}
#if CONFIG_AP_CODE_IN_CAR == 1
#if CONFIG_AP_CODE_IN_CAR
void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr)
{
cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ap", ret_addr);

2
src/arch/x86/lib/exception.c
View File

@ -365,7 +365,7 @@ void x86_exception(struct eregs *info);
void x86_exception(struct eregs *info)
{
#if CONFIG_GDB_STUB == 1
#if CONFIG_GDB_STUB
int signo;
memcpy(gdb_stub_registers, info, 8*sizeof(uint32_t));
gdb_stub_registers[PC] = info->eip;

2
src/arch/x86/lib/pci_ops_conf1.c
View File

@ -8,7 +8,7 @@
* Functions for accessing PCI configuration space with type 1 accesses
*/
#if CONFIG_PCI_IO_CFG_EXT == 0
#if !CONFIG_PCI_IO_CFG_EXT
#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | \
(devfn << 8) | (where & ~3))
#else

4
src/boot/hardwaremain.c
View File

@ -113,13 +113,13 @@ void hardwaremain(int boot_complete)
timestamps[5] = rdtsc();
#endif
#if CONFIG_WRITE_HIGH_TABLES == 1
#if CONFIG_WRITE_HIGH_TABLES
cbmem_initialize();
#if CONFIG_CONSOLE_CBMEM
cbmemc_reinit();
#endif
#endif
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
suspend_resume();
post_code(0x8a);
#endif

4
src/cpu/amd/agesa/family10/model_10_init.c
View File

@ -61,7 +61,7 @@ static void model_10_init(device_t dev)
u8 i;
msr_t msr;
#if CONFIG_LOGICAL_CPUS == 1
#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
@ -88,7 +88,7 @@ static void model_10_init(device_t dev)
// init_processor_name();
#if CONFIG_LOGICAL_CPUS == 1
#if CONFIG_LOGICAL_CPUS
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {

4
src/cpu/amd/agesa/family12/model_12_init.c
View File

@ -63,7 +63,7 @@ static void model_12_init(device_t dev)
u8 i;
msr_t msr;
#if CONFIG_LOGICAL_CPUS == 1
#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
@ -94,7 +94,7 @@ static void model_12_init(device_t dev)
// init_processor_name();
#if CONFIG_LOGICAL_CPUS == 1
#if CONFIG_LOGICAL_CPUS
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {

6
src/cpu/amd/agesa/family14/model_14_init.c
View File

@ -61,7 +61,7 @@ static void model_14_init(device_t dev)
{
u32 i;
msr_t msr;
#if CONFIG_LOGICAL_CPUS == 1
#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
printk(BIOS_DEBUG, "Model 14 Init.\n");
@ -94,7 +94,7 @@ static void model_14_init(device_t dev)
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
if (acpi_slp_type == 3)
restore_mtrr();
#endif
@ -112,7 +112,7 @@ static void model_14_init(device_t dev)
/* Enable the local cpu apics */
setup_lapic();
#if CONFIG_LOGICAL_CPUS == 1
#if CONFIG_LOGICAL_CPUS
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {

4
src/cpu/amd/agesa/family15/model_15_init.c
View File

@ -59,7 +59,7 @@ static void model_15_init(device_t dev)
u8 i;
msr_t msr;
int msrno;
#if CONFIG_LOGICAL_CPUS == 1
#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
@ -95,7 +95,7 @@ static void model_15_init(device_t dev)
/* Enable the local cpu apics */
setup_lapic();
#if CONFIG_LOGICAL_CPUS == 1
#if CONFIG_LOGICAL_CPUS
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {

10
src/cpu/amd/car/post_cache_as_ram.c
View File

@ -29,7 +29,7 @@ static void inline __attribute__((always_inline)) memcopy(void *dest, const voi
: "memory", "cc");
}
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
static inline void *backup_resume(void) {
unsigned long high_ram_base;
@ -83,7 +83,7 @@ static void vErrata343(void)
static void post_cache_as_ram(void)
{
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
void *resume_backup_memory;
#endif
#if 1
@ -108,7 +108,7 @@ static void post_cache_as_ram(void)
#error "You need to set CONFIG_RAMTOP greater than 1M"
#endif
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
resume_backup_memory = backup_resume();
#endif
@ -142,7 +142,7 @@ static void post_cache_as_ram(void)
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache();
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
/* now copy the rest of the area, using the WB method because we already
run normal RAM */
if (resume_backup_memory) {
@ -154,7 +154,7 @@ static void post_cache_as_ram(void)
print_debug("Clearing initial memory region: ");
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
#else

2
src/cpu/amd/dualcore/dualcore.c
View File

@ -17,7 +17,7 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid)
static inline uint8_t set_apicid_cpuid_lo(void)
{
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set
#endif

10
src/cpu/amd/model_10xxx/init_cpus.c
View File

@ -33,7 +33,7 @@ static void prep_fid_change(void);
static void init_fidvid_stage2(u32 apicid, u32 nodeid);
void cpuSetAMDMSR(void);
#if CONFIG_PCI_IO_CFG_EXT == 1
#if CONFIG_PCI_IO_CFG_EXT
static void set_EnableCf8ExtCfg(void)
{
// set the NB_CFG[46]=1;
@ -112,7 +112,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
j * (nb_cfg_54 ? 1 : 64);
#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0)
#if CONFIG_LIFT_BSP_APIC_ID == 0
#if !CONFIG_LIFT_BSP_APIC_ID
if ((i != 0) || (j != 0)) /* except bsp */
#endif
ap_apicid += CONFIG_APIC_ID_OFFSET;
@ -267,7 +267,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
if (id.coreid == 0) {
set_apicid_cpuid_lo(); /* only set it on core0 */
set_EnableCf8ExtCfg(); /* only set it on core0 */
#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
#if CONFIG_ENABLE_APIC_EXT_ID
enable_apic_ext_id(id.nodeid);
#endif
}
@ -277,7 +277,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0)
u32 initial_apicid = get_initial_apicid();
#if CONFIG_LIFT_BSP_APIC_ID == 0
#if !CONFIG_LIFT_BSP_APIC_ID
if (initial_apicid != 0) // other than bsp
#endif
{
@ -289,7 +289,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
lapic_write(LAPIC_ID, dword);
}
#if CONFIG_LIFT_BSP_APIC_ID == 1
#if CONFIG_LIFT_BSP_APIC_ID
bsp_apicid += CONFIG_APIC_ID_OFFSET;
#endif

4
src/cpu/amd/model_10xxx/model_10xxx_init.c
View File

@ -63,7 +63,7 @@ static void model_10xxx_init(device_t dev)
u8 i;
msr_t msr;
struct node_core_id id;
#if CONFIG_LOGICAL_CPUS == 1
#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
@ -92,7 +92,7 @@ static void model_10xxx_init(device_t dev)
/* Set the processor name string */
init_processor_name();
#if CONFIG_LOGICAL_CPUS == 1
#if CONFIG_LOGICAL_CPUS
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {

14
src/cpu/amd/model_fxx/init_cpus.c
View File

@ -40,7 +40,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
3);
if (nb_cfg_54) {
if (j == 0) { // if it is single core, we need to increase siblings for apic calculation
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
e0_later_single_core = is_e0_later_in_bsp(i); // single core
#else
e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
@ -72,8 +72,8 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
i * (nb_cfg_54 ? (siblings + 1) : 1) +
j * (nb_cfg_54 ? 1 : 8);
#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
#if CONFIG_LIFT_BSP_APIC_ID == 0
#if CONFIG_ENABLE_APIC_EXT_ID
#if !CONFIG_LIFT_BSP_APIC_ID
if ((i != 0) || (j != 0)) /* except bsp */
#endif
ap_apicid += CONFIG_APIC_ID_OFFSET;
@ -215,7 +215,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
core0 is done at first --- use wait_all_core0_started */
if (id.coreid == 0) {
set_apicid_cpuid_lo(); /* only set it on core0 */
#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
#if CONFIG_ENABLE_APIC_EXT_ID
enable_apic_ext_id(id.nodeid);
#endif
}
@ -223,10 +223,10 @@ static u32 init_cpus(u32 cpu_init_detectedx)
enable_lapic();
// init_timer(); // We need TMICT to pass msg for FID/VID change
#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
#if CONFIG_ENABLE_APIC_EXT_ID
u32 initial_apicid = get_initial_apicid();
#if CONFIG_LIFT_BSP_APIC_ID == 0
#if !CONFIG_LIFT_BSP_APIC_ID
if (initial_apicid != 0) // other than bsp
#endif
{
@ -238,7 +238,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
lapic_write(LAPIC_ID, dword);
}
#if CONFIG_LIFT_BSP_APIC_ID == 1
#if CONFIG_LIFT_BSP_APIC_ID
bsp_apicid += CONFIG_APIC_ID_OFFSET;
#endif

20
src/cpu/amd/model_fxx/model_fxx_init.c
View File

@ -39,7 +39,7 @@ void cpus_ready_for_init(void)
}
#endif
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
int is_e0_later_in_bsp(int nodeid)
{
uint32_t val;
@ -67,7 +67,7 @@ int is_e0_later_in_bsp(int nodeid)
}
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT
int is_cpu_f0_in_bsp(int nodeid)
{
uint32_t dword;
@ -298,7 +298,7 @@ static void init_ecc_memory(unsigned node_id)
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
unsigned long hole_startk = 0;
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
if (!is_cpu_pre_e0()) {
#endif
@ -307,7 +307,7 @@ static void init_ecc_memory(unsigned node_id)
if (val & 1) {
hole_startk = ((val & (0xff << 24)) >> 10);
}
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
}
#endif
#endif
@ -370,7 +370,7 @@ static void init_ecc_memory(unsigned node_id)
static inline void k8_errata(void)
{
msr_t msr;
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
if (is_cpu_pre_c0()) {
/* Erratum 63... */
msr = rdmsr(HWCR_MSR);
@ -437,14 +437,14 @@ static inline void k8_errata(void)
#endif
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
/* I can't touch this msr on early buggy cpus */
if (!is_cpu_pre_b3())
#endif
{
msr = rdmsr(NB_CFG_MSR);
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
/* D0 later don't need it */
/* Erratum 86 Disable data masking on C0 and
@ -523,7 +523,7 @@ static void model_fxx_init(device_t dev)
/* Enable the local cpu apics */
setup_lapic();
#if CONFIG_LOGICAL_CPUS == 1
#if CONFIG_LOGICAL_CPUS
u32 siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
@ -570,7 +570,7 @@ static struct device_operations cpu_dev_ops = {
};
static struct cpu_device_id cpu_table[] = {
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
{ X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */
{ X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */
{ X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */
@ -612,7 +612,7 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT
/*
* AMD F0 support.
*

8
src/cpu/amd/model_fxx/model_fxx_update_microcode.c
View File

@ -27,13 +27,13 @@
static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
#include "microcode_rev_c.h"
#include "microcode_rev_d.h"
#include "microcode_rev_e.h"
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT
// #include "microcode_rev_f.h"
#endif
/* Dummy terminator */
@ -45,7 +45,7 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
static unsigned id_mapping_table[] = {
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
0x0f48, 0x0048,
0x0f58, 0x0048,
@ -68,7 +68,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
0x20fb1, 0x0210,
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT
#endif

2
src/cpu/amd/model_fxx/powernow_acpi.c
View File

@ -632,7 +632,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
return 0;
}
#if CONFIG_MAX_PHYSICAL_CPUS==1
#if CONFIG_MAX_PHYSICAL_CPUS
/* IRT 80us RVO = 50mV PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */
control = (3 << 30) | (2 << 28) | (2 << 20) | (0 << 18) | (5 << 11);
#else

12
src/cpu/amd/model_fxx/processor_name.c
View File

@ -42,7 +42,7 @@
* your mainboard will not be posted on the AMD Recommended Motherboard Website
*/
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
static const char *processor_names[]={
/* 0x00 */ "AMD Engineering Sample",
/* 0x01-0x03 */ NULL, NULL, NULL,
@ -113,7 +113,7 @@ static inline void wrmsr_amd(unsigned index, msr_t msr)
int init_processor_name(void)
{
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
u32 EightBitBrandId;
#endif
u32 BrandId;
@ -127,7 +127,7 @@ int init_processor_name(void)
char program_string[48];
unsigned int *program_values = (unsigned int *)program_string;
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
/* Find out which CPU brand it is */
EightBitBrandId = cpuid_ebx(0x00000001) & 0xff;
BrandId = cpuid_ebx(0x80000001) & 0xffff;
@ -151,7 +151,7 @@ int init_processor_name(void)
processor_name_string = "AMD Processor model unknown";
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT
u32 Socket;
u32 CmpCap;
u32 PwrLmt;
@ -407,7 +407,7 @@ int init_processor_name(void)
for (i=0; i<47; i++) { // 48 -1
if(program_string[i] == program_string[i+1]) {
switch (program_string[i]) {
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
case 'X': ModelNumber = 22+ NN; break;
case 'Y': ModelNumber = 38 + (2*NN); break;
case 'Z':
@ -416,7 +416,7 @@ int init_processor_name(void)
case 'V': ModelNumber = 9 + NN; break;
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT
case 'R': ModelNumber = NN - 1; break;
case 'P': ModelNumber = 26 + NN; break;
case 'T': ModelNumber = 15 + (CmpCap * 10) + NN; break;

4
src/cpu/amd/mtrr/amd_mtrr.c
View File

@ -6,7 +6,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
#if CONFIG_GFXUMA == 1
#if CONFIG_GFXUMA
extern uint64_t uma_memory_size;
#endif
@ -163,7 +163,7 @@ void amd_setup_mtrrs(void)
* has been deducted from the size of memory below 4GB.
* When setting TOM, include UMA DRAM
*/
#if CONFIG_GFXUMA == 1
#if CONFIG_GFXUMA
msr.lo += uma_memory_size;
#endif
wrmsr(TOP_MEM, msr);

2
src/cpu/intel/hyperthreading/intel_sibling.c
View File

@ -7,7 +7,7 @@
#include <smp/spinlock.h>
#include <assert.h>
#if CONFIG_SERIAL_CPU_INIT==0
#if !CONFIG_SERIAL_CPU_INIT
#error Intel hyper-threading requires serialized cpu init
#endif

26
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@ -16,7 +16,7 @@
#include <cpu/cpu.h>
#include <cpu/intel/speedstep.h>
#if CONFIG_SMP == 1
#if CONFIG_SMP
/* This is a lot more paranoid now, since Linux can NOT handle
* being told there is a CPU when none exists. So any errors
* will return 0, meaning no CPU.
@ -29,7 +29,7 @@ static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
}
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
char *lowmem_backup;
char *lowmem_backup_ptr;
int lowmem_backup_size;
@ -49,7 +49,7 @@ static void copy_secondary_start_to_1m_below(void)
start_eip = get_valid_start_eip((unsigned long)_secondary_start);
code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
/* need to save it for RAM resume */
lowmem_backup_size = code_size;
lowmem_backup = malloc(code_size);
@ -277,7 +277,7 @@ int start_cpu(device_t cpu)
return result;
}
#if CONFIG_AP_IN_SIPI_WAIT == 1
#if CONFIG_AP_IN_SIPI_WAIT
/**
* Sending INIT IPI to self is equivalent of asserting #INIT with a bit of delay.
@ -384,7 +384,7 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat
void secondary_cpu_init(void)
{
atomic_inc(&active_cpus);
#if CONFIG_SERIAL_CPU_INIT == 1
#if CONFIG_SERIAL_CPU_INIT
spin_lock(&start_cpu_lock);
#endif
@ -399,7 +399,7 @@ void secondary_cpu_init(void)
writecr4(cr4_val);
#endif
cpu_initialize();
#if CONFIG_SERIAL_CPU_INIT == 1
#if CONFIG_SERIAL_CPU_INIT
spin_unlock(&start_cpu_lock);
#endif
@ -417,7 +417,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
if (cpu->path.type != DEVICE_PATH_APIC) {
continue;
}
#if CONFIG_SERIAL_CPU_INIT == 0
#if !CONFIG_SERIAL_CPU_INIT
if(cpu==bsp_cpu) {
continue;
}
@ -436,7 +436,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
cpu->path.apic.apic_id);
}
#if CONFIG_SERIAL_CPU_INIT == 1
#if CONFIG_SERIAL_CPU_INIT
udelay(10);
#endif
}
@ -502,7 +502,7 @@ void initialize_cpus(struct bus *cpu_bus)
/* Find the device structure for the boot cpu */
info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
#if CONFIG_SMP == 1
#if CONFIG_SMP
copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
#endif
@ -512,8 +512,8 @@ void initialize_cpus(struct bus *cpu_bus)
cpus_ready_for_init();
#if CONFIG_SMP == 1
#if CONFIG_SERIAL_CPU_INIT == 0
#if CONFIG_SMP
#if !CONFIG_SERIAL_CPU_INIT
/* start all aps at first, so we can init ECC all together */
start_other_cpus(cpu_bus, info->cpu);
#endif
@ -522,8 +522,8 @@ void initialize_cpus(struct bus *cpu_bus)
/* Initialize the bootstrap processor */
cpu_initialize();
#if CONFIG_SMP == 1
#if CONFIG_SERIAL_CPU_INIT == 1
#if CONFIG_SMP
#if CONFIG_SERIAL_CPU_INIT
start_other_cpus(cpu_bus, info->cpu);
#endif

8
src/devices/device.c
View File

@ -536,7 +536,7 @@ static void allocate_resources(struct bus *bus, struct resource *bridge,
}
}
#if CONFIG_PCI_64BIT_PREF_MEM == 1
#if CONFIG_PCI_64BIT_PREF_MEM
#define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM)
#else
#define MEM_MASK (IORESOURCE_MEM)
@ -676,7 +676,7 @@ static void avoid_fixed_resources(struct device *dev)
}
}
#if CONFIG_VGA_BRIDGE_SETUP == 1
#if CONFIG_VGA_BRIDGE_SETUP
device_t vga_pri = 0;
static void set_vga_bridge_bits(void)
{
@ -725,7 +725,7 @@ static void set_vga_bridge_bits(void)
if (!vga)
vga = vga_first;
#if CONFIG_ONBOARD_VGA_IS_PRIMARY == 1
#if CONFIG_ONBOARD_VGA_IS_PRIMARY
if (vga_onboard) /* Will use onboard VGA as primary. */
#else
if (!vga) /* Will use last add-on adapter as primary. */
@ -935,7 +935,7 @@ void dev_configure(void)
struct device *root;
struct device *child;
#if CONFIG_VGA_BRIDGE_SETUP == 1
#if CONFIG_VGA_BRIDGE_SETUP
set_vga_bridge_bits();
#endif

6
src/devices/hypertransport.c
View File

@ -103,9 +103,9 @@ static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
/* AMD K8 unsupported 1GHz? */
if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) {
#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
#if CONFIG_K8_HT_FREQ_1G_SUPPORT
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
/* Only e0 later suupport 1GHz HT. */
if (is_cpu_pre_e0())
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
@ -351,7 +351,7 @@ static void ht_collapse_early_enumeration(struct bus *bus,
} while ((ctrl & (1 << 5)) == 0);
/* Actually, only for one HT device HT chain, and unitid is 0. */
#if CONFIG_HT_CHAIN_UNITID_BASE == 0
#if !CONFIG_HT_CHAIN_UNITID_BASE
if (offset_unitid)
return;
#endif

26
src/devices/pci_device.c
View File

@ -33,22 +33,22 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <delay.h>
#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
#include <device/hypertransport.h>
#endif
#if CONFIG_PCIX_PLUGIN_SUPPORT == 1
#if CONFIG_PCIX_PLUGIN_SUPPORT
#include <device/pcix.h>
#endif
#if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
#if CONFIG_PCIEXP_PLUGIN_SUPPORT
#include <device/pciexp.h>
#endif
#if CONFIG_AGP_PLUGIN_SUPPORT == 1
#if CONFIG_AGP_PLUGIN_SUPPORT
#include <device/agp.h>
#endif
#if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
#if CONFIG_CARDBUS_PLUGIN_SUPPORT
#include <device/cardbus.h>
#endif
#if CONFIG_PC80_SYSTEM == 1
#if CONFIG_PC80_SYSTEM
#include <pc80/i8259.h>
#endif
#if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN
@ -748,17 +748,17 @@ static struct device_operations *get_pci_bridge_ops(device_t dev)
{
unsigned int pos;
#if CONFIG_PCIX_PLUGIN_SUPPORT == 1
#if CONFIG_PCIX_PLUGIN_SUPPORT
pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
if (pos) {
printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev));
return &default_pcix_ops_bus;
}
#endif
#if CONFIG_AGP_PLUGIN_SUPPORT == 1
#if CONFIG_AGP_PLUGIN_SUPPORT
/* How do I detect a PCI to AGP bridge? */
#endif
#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
pos = 0;
while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
u16 flags;
@ -771,7 +771,7 @@ static struct device_operations *get_pci_bridge_ops(device_t dev)
}
}
#endif
#if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
#if CONFIG_PCIEXP_PLUGIN_SUPPORT
pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
if (pos) {
u16 flags;
@ -860,7 +860,7 @@ static void set_pci_ops(struct device *dev)
goto bad;
dev->ops = get_pci_bridge_ops(dev);
break;
#if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
#if CONFIG_CARDBUS_PLUGIN_SUPPORT
case PCI_HEADER_TYPE_CARDBUS:
dev->ops = &default_cardbus_ops_bus;
break;
@ -1256,7 +1256,7 @@ unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
return max;
}
#if CONFIG_PC80_SYSTEM == 1
#if CONFIG_PC80_SYSTEM
/**
* Assign IRQ numbers.
*
@ -1305,7 +1305,7 @@ void pci_assign_irqs(unsigned bus, unsigned slot,
printk(BIOS_DEBUG, " Readback = %d\n", irq);
#endif
#if CONFIG_PC80_SYSTEM == 1
#if CONFIG_PC80_SYSTEM
/* Change to level triggered. */
i8259_configure_irq_trigger(pIntAtoD[line - 1],
IRQ_LEVEL_TRIGGERED);

2
src/devices/pci_rom.c
View File

@ -151,7 +151,7 @@ struct rom_header *pci_rom_load(struct device *dev,
* devices have a mismatch between the hardware and the ROM.
*/
if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) {
#if CONFIG_MULTIPLE_VGA_ADAPTERS == 0
#if !CONFIG_MULTIPLE_VGA_ADAPTERS
extern device_t vga_pri; /* Primary VGA device (device.c). */
if (dev != vga_pri) return NULL; /* Only one VGA supported. */
#endif

6
src/drivers/ati/ragexl/atyfb.h
View File

@ -8,7 +8,7 @@
#define max(x,y) (x>=y)?x:y
#if CONFIG_CONSOLE_BTEXT==1
#if CONFIG_CONSOLE_BTEXT
/*
* Elements of the hardware specific atyfb_par structure
*/
@ -73,7 +73,7 @@ union aty_pll {
* The hardware parameters for each card
*/
struct atyfb_par {
#if CONFIG_CONSOLE_BTEXT==1
#if CONFIG_CONSOLE_BTEXT
struct crtc crtc;
#endif
union aty_pll pll;
@ -97,7 +97,7 @@ struct aty_cursor {
};
#endif
struct fb_info_aty {
#if CONFIG_CONSOLE_BTEXT==1
#if CONFIG_CONSOLE_BTEXT
#if PLL_CRTC_DECODE==1
struct fb_info fb_info;
#endif

2
src/drivers/ati/ragexl/mach64_ct.c
View File

@ -284,7 +284,7 @@ int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
aty_calc_pll_ct(info, &pll->ct);
return 0;
}
#if CONFIG_CONSOLE_BTEXT==1
#if CONFIG_CONSOLE_BTEXT
#if PLL_CRTC_DECODE==1
u32 aty_pll_ct_to_var(const struct fb_info_aty *info,
const union aty_pll *pll)

18
src/drivers/ati/ragexl/xlinit.c
View File

@ -28,7 +28,7 @@
// Hence do only remove this if you fix the code.
#define CONFIG_CONSOLE_BTEXT 0
#if CONFIG_CONSOLE_BTEXT==1
#if CONFIG_CONSOLE_BTEXT
#define PLL_CRTC_DECODE 0
#define SUPPORT_8_BPP_ABOVE 0
@ -393,7 +393,7 @@ static char m64n_xl_33[] = "3D RAGE (XL PCI-33MHz)";
static char m64n_xl_66[] = "3D RAGE (XL PCI-66MHz)";
#if CONFIG_CONSOLE_BTEXT==1
#if CONFIG_CONSOLE_BTEXT
static void aty_set_crtc(const struct fb_info_aty *info,
const struct crtc *crtc);
static int aty_var_to_crtc(const struct fb_info_aty *info,
@ -455,7 +455,7 @@ static struct {
/* 3D RAGE XL PCI-33/BGA */
{ 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
};
#if CONFIG_CONSOLE_BTEXT==1
#if CONFIG_CONSOLE_BTEXT
static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk)
{
int i, size;
@ -502,7 +502,7 @@ static void ati_ragexl_init(device_t dev)
#endif
int pll, mclk, xclk;
#if CONFIG_CONSOLE_BTEXT==1
#if CONFIG_CONSOLE_BTEXT
#if 0
int gtb_memsize, k;
@ -532,7 +532,7 @@ static void ati_ragexl_init(device_t dev)
res = res->next;
}
#if CONFIG_CONSOLE_BTEXT==1
#if CONFIG_CONSOLE_BTEXT
info->frame_buffer = res->base;
#endif /* CONFIG_CONSOLE_BTEXT */
@ -548,7 +548,7 @@ static void ati_ragexl_init(device_t dev)
#endif
#if CONFIG_CONSOLE_BTEXT==1
#if CONFIG_CONSOLE_BTEXT
info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0);
#endif
@ -581,7 +581,7 @@ found:
mclk = 63;
}
#endif
#if CONFIG_CONSOLE_BTEXT==1
#if CONFIG_CONSOLE_BTEXT
aty_calc_mem_refresh(info, type, xclk);
#endif /* CONFIG_CONSOLE_BTEXT */
@ -596,7 +596,7 @@ found:
atyfb_xl_init(info);
#if CONFIG_CONSOLE_BTEXT==1
#if CONFIG_CONSOLE_BTEXT
info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07);
@ -803,7 +803,7 @@ found:
}
#if CONFIG_CONSOLE_BTEXT==1
#if CONFIG_CONSOLE_BTEXT
static int atyfb_decode_var(const struct fb_var_screeninfo *var,
struct atyfb_par *par,

4
src/include/cpu/amd/model_fxx_rev.h
View File

@ -2,7 +2,7 @@
int init_processor_name(void);
#if CONFIG_K8_REV_F_SUPPORT == 0
#if !CONFIG_K8_REV_F_SUPPORT
static inline int is_cpu_rev_a0(void)
{
return (cpuid_eax(1) & 0xfffef) == 0x0f00;
@ -79,7 +79,7 @@ int is_e0_later_in_bsp(int nodeid); //defined model_fxx_init.c
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT
//AMD_F0_SUPPORT
static inline int is_cpu_pre_f0(void)
{

2
src/include/cpu/x86/lapic.h
View File

@ -147,7 +147,7 @@ static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
void setup_lapic(void);
#if CONFIG_SMP == 1
#if CONFIG_SMP
struct device;
int start_cpu(struct device *cpu);
#endif /* CONFIG_SMP */

2
src/include/delay.h
View File

@ -3,7 +3,7 @@
#if !defined( __ROMCC__)
#if CONFIG_HAVE_INIT_TIMER == 1
#if CONFIG_HAVE_INIT_TIMER
void init_timer(void);
#else
#define init_timer() do{} while(0)

2
src/include/reset.h
View File

@ -4,7 +4,7 @@
#if !defined( __ROMCC__ )
/* ROMCC can't do function prototypes... */
#if CONFIG_HAVE_HARD_RESET == 1
#if CONFIG_HAVE_HARD_RESET
void hard_reset(void);
#else
#define hard_reset() do {} while(0)

2
src/include/smp/atomic.h
View File

@ -1,7 +1,7 @@
#ifndef SMP_ATOMIC_H
#define SMP_ATOMIC_H
#if CONFIG_SMP == 1
#if CONFIG_SMP
#include <arch/smp/atomic.h>
#else

2
src/include/smp/spinlock.h
View File

@ -1,7 +1,7 @@
#ifndef SMP_SPINLOCK_H
#define SMP_SPINLOCK_H
#if CONFIG_SMP == 1
#if CONFIG_SMP
#include <arch/smp/spinlock.h>
#else /* !CONFIG_SMP */

2
src/include/watchdog.h
View File

@ -1,7 +1,7 @@
#ifndef WATCHDOG_H
#define WATCHDOG_H
#if CONFIG_USE_WATCHDOG_ON_BOOT == 1
#if CONFIG_USE_WATCHDOG_ON_BOOT
void watchdog_off(void);
#else
#define watchdog_off()

2
src/mainboard/advansus/a785e-i/acpi_tables.c
View File

@ -236,7 +236,7 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_create_facs(facs);
/* FDAT */
#if CONFIG_BOARD_HAS_FADT == 1
#if CONFIG_BOARD_HAS_FADT
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current;

4
src/mainboard/advansus/a785e-i/get_bus_conf.c
View File

@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>
@ -141,7 +141,7 @@ void get_bus_conf(void)
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;

4
src/mainboard/advansus/a785e-i/mainboard.c
View File

@ -84,7 +84,7 @@ static void a785e_i_enable(device_t dev)
printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@ -133,7 +133,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,

2
src/mainboard/advansus/a785e-i/mptable.c
View File

@ -79,7 +79,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else

2
src/mainboard/advansus/a785e-i/platform_cfg.h
View File

@ -36,7 +36,7 @@
* bigger than 1M you have to set the ROM size outside CIMx module and
* before AGESA module get call.
*/
#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M

4
src/mainboard/advansus/a785e-i/romstage.c
View File

@ -160,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* run _early_setup before soft-reset. */
rs780_early_setup();
#if CONFIG_SET_FIDVID == 1
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
post_code(0x39);

4
src/mainboard/amd/bimini_fam10/get_bus_conf.c
View File

@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>
@ -138,7 +138,7 @@ void get_bus_conf(void)
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;

4
src/mainboard/amd/bimini_fam10/mainboard.c
View File

@ -134,7 +134,7 @@ static void bimini_enable(device_t dev)
printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@ -184,7 +184,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,

2
src/mainboard/amd/bimini_fam10/mptable.c
View File

@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else

2
src/mainboard/amd/bimini_fam10/romstage.c
View File

@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();

4
src/mainboard/amd/dbm690t/get_bus_conf.c
View File

@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;

4
src/mainboard/amd/dbm690t/mainboard.c
View File

@ -187,7 +187,7 @@ static void dbm690t_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@ -238,7 +238,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED,

2
src/mainboard/amd/dbm690t/mptable.c
View File

@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else

2
src/mainboard/amd/dbm690t/romstage.c
View File

@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();

4
src/mainboard/amd/dinar/mainboard.c
View File

@ -75,7 +75,7 @@ uint64_t uma_memory_base, uma_memory_size;
static void dinar_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
msr_t msr, msr2;
uint32_t sys_mem;
@ -124,7 +124,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,

4
src/mainboard/amd/dinar/rd890_cfg.h
View File

@ -32,10 +32,10 @@
* [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
*/
#ifndef DEFAULT_HT_PATH
#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1
#if CONFIG_CPU_AMD_AGESA_FAMILY10
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1
#if CONFIG_CPU_AMD_AGESA_FAMILY15
#define DEFAULT_HT_PATH {0x0, 0x1}
#endif
#endif

2
src/mainboard/amd/dinar/sb700_cfg.h
View File

@ -40,7 +40,7 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M

4
src/mainboard/amd/inagua/mainboard.c
View File

@ -80,7 +80,7 @@ static void inagua_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
msr_t msr, msr2;
uint32_t sys_mem;
@ -128,7 +128,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,

2
src/mainboard/amd/inagua/mptable.c
View File

@ -87,7 +87,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else

2
src/mainboard/amd/inagua/platform_cfg.h
View File

@ -37,7 +37,7 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M

4
src/mainboard/amd/mahogany/get_bus_conf.c
View File

@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;

4
src/mainboard/amd/mahogany/mainboard.c
View File

@ -105,7 +105,7 @@ static void mahogany_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@ -154,7 +154,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,

2
src/mainboard/amd/mahogany/mptable.c
View File

@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else

2
src/mainboard/amd/mahogany/romstage.c
View File

@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();

4
src/mainboard/amd/mahogany_fam10/get_bus_conf.c
View File

@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;

4
src/mainboard/amd/mahogany_fam10/mainboard.c
View File

@ -106,7 +106,7 @@ static void mahogany_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@ -155,7 +155,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,

2
src/mainboard/amd/mahogany_fam10/mptable.c
View File

@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else

2
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();

2
src/mainboard/amd/persimmon/agesawrapper.c
View File

@ -515,7 +515,7 @@ agesawrapper_amdinitlate (
return (UINT32)Status;
}
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
UINT32
agesawrapper_amdinitresume (
VOID

4
src/mainboard/amd/persimmon/get_bus_conf.c
View File

@ -51,7 +51,7 @@ u32 sbdn_sb800;
static u32 get_bus_conf_done = 0;
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
extern u8 acpi_slp_type;
#endif
@ -83,7 +83,7 @@ void get_bus_conf(void)
* of each of the write functions called prior to the ACPI write functions, so this
* becomes the best place for this call.
*/
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
if (acpi_slp_type != 3) {
status = agesawrapper_amdinitlate();
if(status)

6
src/mainboard/amd/persimmon/mainboard.c
View File

@ -63,11 +63,11 @@ static void persimmon_enable(device_t dev)
* The mainboard is the first place that we get control in ramstage. Check
* for S3 resume and call the approriate AGESA/CIMx resume functions.
*/
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
acpi_slp_type = acpi_get_sleep_type();
#endif
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
msr_t msr, msr2;
uint32_t sys_mem;
@ -113,7 +113,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,

2
src/mainboard/amd/persimmon/mptable.c
View File

@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else

2
src/mainboard/amd/persimmon/platform_cfg.h
View File

@ -37,7 +37,7 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M

6
src/mainboard/amd/persimmon/romstage.c
View File

@ -51,7 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
void *resume_backup_memory;
#endif
@ -107,7 +107,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
else
printk(BIOS_DEBUG, "passed.\n");
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
if (!acpi_is_wakeup_early()) { /* Check for S3 resume */
#endif
post_code(0x40);
@ -126,7 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
else
printk(BIOS_DEBUG, "passed.\n");
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");

4
src/mainboard/amd/pistachio/get_bus_conf.c
View File

@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;

4
src/mainboard/amd/pistachio/mainboard.c
View File

@ -257,7 +257,7 @@ static void pistachio_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@ -308,7 +308,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED,

2
src/mainboard/amd/pistachio/mptable.c
View File

@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else

2
src/mainboard/amd/pistachio/romstage.c
View File

@ -101,7 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();

4
src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
View File

@ -3,7 +3,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@ -192,7 +192,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;

2
src/mainboard/amd/serengeti_cheetah/mptable.c
View File

@ -4,7 +4,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>

4
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -1,4 +1,4 @@
#if CONFIG_K8_REV_F_SUPPORT == 1
#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,

2
src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
View File

@ -22,7 +22,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif

2
src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
View File

@ -23,7 +23,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>

2
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -255,7 +255,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();

4
src/mainboard/amd/south_station/mainboard.c
View File

@ -82,7 +82,7 @@ static void southstation_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
msr_t msr, msr2;
uint32_t sys_mem;
@ -129,7 +129,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,

2
src/mainboard/amd/south_station/mptable.c
View File

@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else

2
src/mainboard/amd/south_station/platform_cfg.h
View File

@ -37,7 +37,7 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M

4
src/mainboard/amd/tilapia_fam10/get_bus_conf.c
View File

@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;

4
src/mainboard/amd/tilapia_fam10/mainboard.c
View File

@ -281,7 +281,7 @@ static void tilapia_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@ -331,7 +331,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,

2
src/mainboard/amd/tilapia_fam10/mptable.c
View File

@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else

2
src/mainboard/amd/tilapia_fam10/romstage.c
View File

@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();

2
src/mainboard/amd/torpedo/Oem.h
View File

@ -20,7 +20,7 @@
#define BIOS_SIZE 0x04 //04 - 1MB
#endif
#define LEGACY_FREE 0x00
#if CONFIG_ONBOARD_USB30 == 0
#if !CONFIG_ONBOARD_USB30
#define XHCI_SUPPORT 0x01
#endif

4
src/mainboard/amd/torpedo/mainboard.c
View File

@ -58,7 +58,7 @@ uint64_t uma_memory_base, uma_memory_size;
static void torpedo_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
msr_t msr, msr2;
uint32_t sys_mem;
@ -107,7 +107,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,

2
src/mainboard/amd/torpedo/mptable.c
View File

@ -164,7 +164,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin))
#else

6
src/mainboard/amd/torpedo/platform_cfg.h
View File

@ -39,7 +39,7 @@
#define BIOS_SIZE_4M 3
#define BIOS_SIZE_8M 7
#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M
@ -311,7 +311,7 @@
#define INCHIP_USB_CINFIG 0x7F
#define INCHIP_USB_OHCI1_CINFIG 0x01
#define INCHIP_USB_OHCI2_CINFIG 0x01
#if CONFIG_ONBOARD_USB30 == 1
#if CONFIG_ONBOARD_USB30
#define INCHIP_USB_OHCI3_CINFIG 0x00
#else
#define INCHIP_USB_OHCI3_CINFIG 0x01
@ -985,7 +985,7 @@
* @li <b>0</b> - Disable
* @li <b>1</b> - Enable
*/
#if CONFIG_ONBOARD_USB30 == 1
#if CONFIG_ONBOARD_USB30
#define SB_XHCI_SWITCH 0
#else
#define SB_XHCI_SWITCH 1

4
src/mainboard/amd/union_station/mainboard.c
View File

@ -56,7 +56,7 @@ static void unionstation_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
msr_t msr, msr2;
uint32_t sys_mem;
@ -103,7 +103,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,

2
src/mainboard/amd/union_station/mptable.c
View File

@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else

2
src/mainboard/amd/union_station/platform_cfg.h
View File

@ -37,7 +37,7 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M

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