broadcom/cygnus: add secimage and sign bootblock

secimage is a tool which adds a header and signature to the binary
first loaded by the soc. ARM core frequency is set to 1 Ghz.

BUG=chrome-os-partner:36421
BRANCH=broadcom-firmware
TEST=booted b0 board

Change-Id: Ia08600d45c47ee4f08d253980036916e44b0044a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 36284d1b242c26b0b5aac2894f7ed1790da1ef15
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chrome-internal-review.googlesource.com/197155
Original-Reviewed-by: Scott Branden <sbranden@broadcom.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com>
Original-Tested-by: Daisuke Nojiri <dnojiri@google.com>
Original-Change-Id: Iaddd24006b368c8f37e075cb51e151e985029f3b
Original-Reviewed-on: https://chromium-review.googlesource.com/264417
Reviewed-on: http://review.coreboot.org/9914
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

util/broadcom/unauth.cfg

@@ -0,0 +1,20 @@
+// Unauth Header
+//
+// struct UnAuthenticatedHeader_t {
+//	uint32_t Tag;		/* Tag used to locate boot binary in memory */
+//	uint32_t Length;	/* Length of the boot binary */
+//	uint32_t Reserved;	/* Address for the non-authenticated boot.
+//				   The address is aligned to 16 bytes boundary.
+//				   The lower 4 bits are used for ClkConfig:
+//				   Value   Freq
+//				   1       400
+//				   2       1GHz
+//				   3       Max (1.2GHz)
+//				   4       no PLL lock: 200MHz
+//				 */
+//	uint32_t crc;		/* CRC computed on all other fields in this
+//				   structure excluding crc field */
+// };
+Tag=		0xA5A5A5A5
+Length=		0x00000000
+Reserved=  	0x00000002