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soc/intel: Factor out common smbus.h

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Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50942
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2021-02-19 20:08:50 +01:00
parent 19af7bc822
commit e178df27dd
8 changed files with 46 additions and 172 deletions
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21
src/soc/intel/skylake/include/soc/smbus.h
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@@ -3,25 +3,6 @@
#ifndef _SOC_SMBUS_H_
#define _SOC_SMBUS_H_
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
#define TCO_STS_SECOND_TO (1 << 1)
#define TCO_INTRD_DET (1 << 0)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
#define TCO2_CNT 0x0A
#define TCO_INTRD_SEL_MASK (3 << 1)
#define TCO_INTRD_SEL_SMI (1 << 2)
#define TCO_INTRD_SEL_INT (1 << 1)
/*
* Default slave address value for PCH. This value is set to match default
* value set by hardware. It is useful since PCH is able to respond even
* before CPU is up. This is reset by RSMRST# but not by PLTRST#.
*/
#define SMBUS_SLAVE_ADDR 0x44
#include <intelpch/smbus.h>
#endif