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soc/intel/tigerlake: Add devicetree support to change PCH VR settings

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For Tiger Lake platforms, this patch set provides a way to override PCH
external VR settings and ext rail voltage/current through devicetree.
This enables setting of optimal settings for FIVRs for a particular PCH
type.

BUG=None
BRANCH=None
TEST=Build and boot volteer.

Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ic55472d392f27d153656afbe8692be7e243bb374
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41424
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Venkata Krishna Nimmagadda
2020-05-15 00:13:40 -07:00
committed by Tim Wawrzynczak
parent b75d5743af
commit e18f71964d
2 changed files with 63 additions and 0 deletions
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23
src/soc/intel/tigerlake/fsp_params.c
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@@ -262,6 +262,29 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->ITbtPcieRootPortEn[i] = 0;
}
/* PCH FIVR settings override */
if (config->ext_fivr_settings.configure_ext_fivr) {
params->PchFivrExtV1p05RailEnabledStates =
config->ext_fivr_settings.v1p05_enable_bitmap;
params->PchFivrExtV1p05RailSupportedVoltageStates =
config->ext_fivr_settings.v1p05_supported_voltage_bitmap;
params->PchFivrExtVnnRailEnabledStates =
config->ext_fivr_settings.vnn_enable_bitmap;
params->PchFivrExtVnnRailSupportedVoltageStates =
config->ext_fivr_settings.vnn_supported_voltage_bitmap;
/* convert mV to number of 2.5 mV increments */
params->PchFivrExtVnnRailSxVoltage =
(config->ext_fivr_settings.vnn_sx_voltage_mv * 10) / 25;
params->PchFivrExtV1p05RailIccMaximum =
config->ext_fivr_settings.v1p05_icc_max_ma;
}
mainboard_silicon_init_params(params);
}