soc/intel/quark: Switch reference from uart_dev to uart_bdf
Switch from using uart_dev to uart_bdf to better describe the value in use. TEST=Build and run on Galileo Gen2 Change-Id: If5066b93ea8ccce4a5b89ee3984c7413d5358e71 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14938 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
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		| @@ -28,15 +28,15 @@ int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base) | ||||
| 	uint16_t reg16; | ||||
|  | ||||
| 	/* HSUART controller #1 (B0:D20:F5). */ | ||||
| 	device_t uart_dev = PCI_DEV(bus, dev, func); | ||||
| 	pci_devfn_t uart_bdf = PCI_DEV(bus, dev, func); | ||||
|  | ||||
| 	/* Decode BAR0(offset 0x10). */ | ||||
| 	pci_write_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base); | ||||
| 	pci_write_config32(uart_bdf, PCI_BASE_ADDRESS_0, mmio_base); | ||||
|  | ||||
| 	/* Enable MEMBASE at CMD(offset 0x04). */ | ||||
| 	reg16 = pci_read_config16(uart_dev, PCI_COMMAND); | ||||
| 	reg16 = pci_read_config16(uart_bdf, PCI_COMMAND); | ||||
| 	reg16 |= PCI_COMMAND_MEMORY; | ||||
| 	pci_write_config16(uart_dev, PCI_COMMAND, reg16); | ||||
| 	pci_write_config16(uart_bdf, PCI_COMMAND, reg16); | ||||
|  | ||||
| 	return 0; | ||||
| } | ||||
|   | ||||
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