Add proper Slot 1 CPU support code/infrastructure.
Signed-off-by: Keith Hui <buurin@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
33
src/cpu/intel/slot_1/Kconfig
Normal file
33
src/cpu/intel/slot_1/Kconfig
Normal file
@@ -0,0 +1,33 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2010 Keith Hui <buurin@gmail.com>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
config CPU_INTEL_SLOT_1
|
||||
bool
|
||||
|
||||
config DCACHE_RAM_BASE
|
||||
hex
|
||||
default 0xc0000
|
||||
depends on CPU_INTEL_SLOT_1
|
||||
|
||||
config DCACHE_RAM_SIZE
|
||||
hex
|
||||
default 0x01000
|
||||
depends on CPU_INTEL_SLOT_1
|
||||
|
Reference in New Issue
Block a user