sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

intel: update common and FSP cache-as-ram parameters

Browse Source 
Instead of just passing bits, tsc_low, tsc_high, and an
opaque pointer to chipset context those fields are bundled
into a cache_as_ram_params struct. Additionally, a new
struct fsp_car_context is created to hold the FSP
information. These could be combined as the existing
romstage code assumes what the chipset_context values are, but
I'm leaving the concept of "common" alone for the time being.
While working in that area the ABI between assembly and C code
has changed to just pass a single pointer to cache_as_ram_params
struct. Lastly, validate the bootloader cache-as-ram region
with the Kconfig options.

BUG=chrome-os-partner:44676
BRANCH=None
TEST=Built and booted glados.

Original-Change-Id: Ib2a0e38477ef7c15cff1836836cfb55e5dc8a58e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/300190
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>

Change-Id: Ic5a0daa4e2fe5eda0c4d2a45d86baf14ff7b2c6c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11809
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin
2015-09-16 15:18:04 -05:00
committed by Aaron Durbin
parent 8ef9c56602
commit e1ecfc93af
5 changed files with 58 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files

47
src/drivers/intel/fsp1_1/cache_as_ram.inc
View File

@@ -115,53 +115,46 @@ CAR_init_done:
/* Setup bootloader stack */
movl %edx, %esp
/* Save BIST value */
movd %edi, %mm2
/*
* ebp: FSP_INFO_HEADER address
* ecx: Temp RAM base
* edx: Temp RAM top
* edi: BIST value
* esp: Top of stack in temp RAM
* mm0: low 32-bits of TSC value
* mm1: high 32-bits of TSC value
* mm2: BIST value
*/
/* Create fsp_car_context on stack. */
pushl %edx /* bootloader CAR end */
pushl %ecx /* bootloader CAR begin */
pushl %ebp /* FSP_INFO_HEADER */
/* Create cache_as_ram_params on stack */
pushl %esp /* chipset_context -> fsp_car_context */
pushl %edi /* bist */
movd %mm1, %eax
pushl %eax /* tsc[63:32] */
movd %mm0, %eax
pushl %eax /* tsc[31:0] */
pushl %esp /* pointer to cache_as_ram_params */
/* Save FSP_INFO_HEADER location in ebx */
mov %ebp, %ebx
/* Coreboot assumes stack/heap region will be zero */
cld
movl %ecx, %edi
neg %ecx
add %edx, %ecx
/* Only clear up to current stack value. */
add %esp, %ecx
shrl $2, %ecx
xorl %eax, %eax
rep stosl
/* Save FSP_INFO_HEADER location in ebx */
mov %ebp, %ebx
/*
* ebx: FSP_INFO_HEADER address
* esi: Temp RAM base
* esp: Top of stack in temp RAM
* mm0: low 32-bits of TSC value
* mm1: high 32-bits of TSC value
* mm2: BIST value
*/
/* Frame for romstage_main(bist, tsc_low, tsc_hi, fih) */
pushl %ebx
movd %mm1, %eax
pushl %eax
movd %mm0, %eax
pushl %eax
movd %mm2, %eax
pushl %eax
before_romstage:
post_code(0x23)
/* Call romstage.c main function. */
/* Call romstage_main(struct cache_as_ram_params *) */
call romstage_main
/*

7
src/drivers/intel/fsp1_1/include/fsp/util.h
View File

@@ -28,6 +28,13 @@
#include <program_loading.h>
#include <commonlib/region.h>
/* cache-as-ram context for FSP 1.1. */
struct fsp_car_context {
FSP_INFO_HEADER *fih;
uintptr_t bootloader_car_start;
uintptr_t bootloader_car_end;
};
/* find_fsp() should only be called from assembly code. */
FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
/* Set FSP's runtime information. */