intel: update common and FSP cache-as-ram parameters

Instead of just passing bits, tsc_low, tsc_high, and an
opaque pointer to chipset context those fields are bundled
into a cache_as_ram_params struct. Additionally, a new
struct fsp_car_context is created to hold the FSP
information. These could be combined as the existing
romstage code assumes what the chipset_context values are, but
I'm leaving the concept of "common" alone for the time being.
While working in that area the ABI between assembly and C code
has changed to just pass a single pointer to cache_as_ram_params
struct. Lastly, validate the bootloader cache-as-ram region
with the Kconfig options.

BUG=chrome-os-partner:44676
BRANCH=None
TEST=Built and booted glados.

Original-Change-Id: Ib2a0e38477ef7c15cff1836836cfb55e5dc8a58e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/300190
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>

Change-Id: Ic5a0daa4e2fe5eda0c4d2a45d86baf14ff7b2c6c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11809
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/drivers/intel/fsp1_1/cache_as_ram.inc

@@ -115,53 +115,46 @@ CAR_init_done:
 	/* Setup bootloader stack */
 	movl	%edx, %esp
 
-	/* Save BIST value */
-	movd	%edi, %mm2
-
 	/*
 	 * ebp:  FSP_INFO_HEADER address
 	 * ecx:  Temp RAM base
 	 * edx:  Temp RAM top
+	 * edi:  BIST value
 	 * esp:  Top of stack in temp RAM
 	 * mm0:  low 32-bits of TSC value
 	 * mm1:  high 32-bits of TSC value
-	 * mm2:  BIST value
 	 */
 
+	/* Create fsp_car_context on stack. */
+	pushl	%edx	/* bootloader CAR end */
+	pushl	%ecx	/* bootloader CAR begin */
+	pushl	%ebp	/* FSP_INFO_HEADER */
+	/* Create cache_as_ram_params on stack */
+	pushl	%esp	/* chipset_context -> fsp_car_context */
+	pushl	%edi	/* bist */
+	movd	%mm1, %eax
+	pushl	%eax	/* tsc[63:32] */
+	movd	%mm0, %eax
+	pushl	%eax 	/* tsc[31:0] */
+	pushl	%esp	/* pointer to cache_as_ram_params */
+
+	/* Save FSP_INFO_HEADER location in ebx */
+	mov	%ebp, %ebx
+
 	/* Coreboot assumes stack/heap region will be zero */
 	cld
 	movl	%ecx, %edi
 	neg	%ecx
-	add	%edx, %ecx
+	/* Only clear up to current stack value. */
+	add	%esp, %ecx
 	shrl	$2, %ecx
 	xorl	%eax, %eax
 	rep	stosl
 
-	/* Save FSP_INFO_HEADER location in ebx */
-	mov	%ebp, %ebx
-
-	/*
-	 * ebx:  FSP_INFO_HEADER address
-	 * esi:  Temp RAM base
-	 * esp:  Top of stack in temp RAM
-	 * mm0:  low 32-bits of TSC value
-	 * mm1:  high 32-bits of TSC value
-	 * mm2:  BIST value
-	 */
-
-	/* Frame for romstage_main(bist, tsc_low, tsc_hi, fih) */
-	pushl	%ebx
-	movd	%mm1, %eax
-	pushl	%eax
-	movd	%mm0, %eax
-	pushl	%eax
-	movd	%mm2, %eax
-	pushl	%eax
-
 before_romstage:
 	post_code(0x23)
 
-	/* Call romstage.c main function. */
+	/* Call romstage_main(struct cache_as_ram_params *) */
 	call	romstage_main
 
 	/*

src/drivers/intel/fsp1_1/include/fsp/util.h

@@ -28,6 +28,13 @@
 #include <program_loading.h>
 #include <commonlib/region.h>
 
+/* cache-as-ram context for FSP 1.1. */
+struct fsp_car_context {
+	FSP_INFO_HEADER *fih;
+	uintptr_t bootloader_car_start;
+	uintptr_t bootloader_car_end;
+};
+
 /* find_fsp() should only be called from assembly code. */
 FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
 /* Set FSP's runtime information. */

src/soc/intel/common/raminit.c

@@ -57,6 +57,7 @@ void raminit(struct romstage_params *params)
 	unsigned long int data;
 	EFI_PEI_HOB_POINTERS hob_ptr;
 #endif
+	struct fsp_car_context *fsp_car_context;
 
 	/*
 	 * Find and copy the UPD region to the stack so the platform can modify
@@ -68,7 +69,8 @@ void raminit(struct romstage_params *params)
 	 * region in the FSP binary.
 	 */
 	post_code(0x34);
-	fsp_header = params->chipset_context;
+	fsp_car_context = params->chipset_context;
+	fsp_header = fsp_car_context->fih;
 	vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
 					fsp_header->ImageBase);
 	printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr);
@@ -167,7 +169,7 @@ void raminit(struct romstage_params *params)
 	}
 
 	/* Save the FSP runtime parameters. */
-	fsp_set_runtime(params->chipset_context, hob_list_ptr);
+	fsp_set_runtime(fsp_header, hob_list_ptr);
 
 	/* Lookup the FSP_BOOTLOADER_TOLUM_HOB */
 	cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr);

src/soc/intel/common/romstage.c

@@ -32,6 +32,7 @@
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 #include <elog.h>
+#include <fsp/util.h>
 #include <memory_info.h>
 #include <reset.h>
 #include <romstage_handoff.h>
@@ -48,22 +49,22 @@
 #include <vendorcode/google/chromeos/chromeos.h>
 
 /* Entry from cache-as-ram.inc. */
-asmlinkage void *romstage_main(unsigned int bist,
+asmlinkage void *romstage_main(struct cache_as_ram_params *car_params)
-				uint32_t tsc_low, uint32_t tsc_high,
-				void *chipset_context)
 {
 	void *top_of_stack;
 	struct pei_data pei_data;
+	struct fsp_car_context *fsp_car_context;
 	struct romstage_params params = {
-		.bist = bist,
+		.bist = car_params->bist,
 		.pei_data = &pei_data,
-		.chipset_context = chipset_context,
+		.chipset_context = car_params->chipset_context,
 	};
 
+	fsp_car_context = car_params->chipset_context;
 	post_code(0x30);
 
 	/* Save timestamp data */
-	timestamp_init((((uint64_t)tsc_high) << 32) | (uint64_t)tsc_low);
+	timestamp_init(car_params->tsc);
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	memset(&pei_data, 0, sizeof(pei_data));
@@ -76,9 +77,8 @@ asmlinkage void *romstage_main(unsigned int bist,
 	console_init();
 
 	/* Display parameters */
-	printk(BIOS_SPEW, "bist: 0x%08x\n", bist);
+	printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist);
-	printk(BIOS_SPEW, "tsc_low: 0x%08x\n", tsc_low);
+	printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc);
-	printk(BIOS_SPEW, "tsc_hi: 0x%08x\n", tsc_high);
 	printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
 		CONFIG_MMCONF_BASE_ADDRESS);
 	printk(BIOS_INFO, "Using: %s\n",
@@ -88,7 +88,17 @@ asmlinkage void *romstage_main(unsigned int bist,
 
 	/* Display FSP banner */
 	printk(BIOS_DEBUG, "FSP TempRamInit successful\n");
-	print_fsp_info(params.chipset_context);
+	print_fsp_info(fsp_car_context->fih);
+
+	if (fsp_car_context->bootloader_car_start != CONFIG_DCACHE_RAM_BASE ||
+	    fsp_car_context->bootloader_car_end !=
+			(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) {
+		printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n",
+			CONFIG_DCACHE_RAM_BASE,
+			CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE,
+			(long)fsp_car_context->bootloader_car_start,
+			(long)fsp_car_context->bootloader_car_end);
+	}
 
 	/* Get power state */
 	params.power_state = fill_power_state();

src/soc/intel/common/romstage.h

@@ -29,6 +29,12 @@
 #include <soc/pei_data.h>
 #include <soc/pm.h>		/* chip_power_state */
 
+struct cache_as_ram_params {
+	uint64_t tsc;
+	uint32_t bist;
+	void *chipset_context;
+};
+
 struct romstage_params {
 	unsigned long bist;
 	struct chipset_power_state *power_state;
@@ -85,8 +91,7 @@ void report_memory_config(void);
 void report_platform_info(void);
 asmlinkage void romstage_after_car(void *chipset_context);
 void romstage_common(struct romstage_params *params);
-asmlinkage void *romstage_main(unsigned int bist, uint32_t tsc_lo,
+asmlinkage void *romstage_main(struct cache_as_ram_params *car_params);
-			       uint32_t tsc_high, void *chipset_context);
 void *setup_stack_and_mtrrs(void);
 void set_max_freq(void);
 void soc_after_ram_init(struct romstage_params *params);