soc/intel/xeon_sp: Compress FSP-S

Compress FSP-S to save some space in CBFS.
Reduces the size of debug FSP-S by about 25%.

Test: Still boots on ibm/sbp1.
TEST= Build and boot on intel/archercity CRB.

Change-Id: I6248e7cabbce45f6c2fedfab34f328309f87e868
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81634
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/soc/intel/xeon_sp/Kconfig

@@ -15,6 +15,7 @@ config XEON_SP_COMMON_BASE
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select FSP_CAR
 	select FSP_M_XIP
+	select FSP_COMPRESS_FSP_S_LZ4
 	select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
 	select FSP_T_XIP
 	select HAVE_SMI_HANDLER