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mb/google/zork: keep the c-state IO base address alignment

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Align the C-state MSR value of BSP with AGESA.

BUG=b:162705221
BRANCH=none
TEST=Check the MSR value is correct and BSP can enter CC6 with AVT tool

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ib98d34af518439d338326446c20601867ad31690
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Chris Wang
2020-08-03 22:36:13 +08:00
committed by Aaron Durbin
parent b7184e28ba
commit e2497d0181
3 changed files with 11 additions and 7 deletions
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10
src/soc/amd/picasso/cpu.c
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@@ -46,6 +46,15 @@ int get_cpu_count(void)
return 1 + (cpuid_ecx(0x80000008) & 0xff);
}
static void set_cstate_io_addr(void)
{
msr_t cst_addr;
cst_addr.hi = 0;
cst_addr.lo = ACPI_CPU_CONTROL;
wrmsr(MSR_CSTATE_ADDRESS, cst_addr);
}
static void fill_in_relocation_params(struct smm_relocation_params *params)
{
uintptr_t tseg_base;
@@ -109,6 +118,7 @@ static void model_17_init(struct device *dev)
{
check_mca();
setup_lapic();
set_cstate_io_addr();
amd_update_microcode_from_cbfs();
}