nb/intel/ironlake: Move out HECI remainders into southbridge

Move the remaining HECI-related stuff to southbridge scope, as the HECI
hardware is in the southbridge. Note that HECI BAR is now enabled a bit
earlier than before, but this shouldn't matter.

Change-Id: I4a29d0b5d5c5e22508bcdfe34a1c5459ae967c75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/ironlake/early_init.c

@@ -106,10 +106,6 @@ void ironlake_early_initialization(int chipset_type)
 
 	early_cpu_init();
 
-	pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR);
-	pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
-			   PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-
 	/* Magic for S3 resume. Must be done early.  */
 	if (s3_resume) {
 		mchbar_clrsetbits32(0x1e8, 1, 6);

src/northbridge/intel/ironlake/ironlake.h

@@ -3,8 +3,6 @@
 #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__
 #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__
 
-#define DEFAULT_HECIBAR		((u8 *)0xfed17000)
-
 /*
  * D1:F0 PEG
  */