From e258df2cb7f0522c15b4ba451fda0ce66fb38597 Mon Sep 17 00:00:00 2001
From: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Date: Sun, 16 Jan 2022 21:26:56 +0530
Subject: [PATCH] soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake N

Alder Lake N has eMMC storage device. Add PCR Port ID for it.
Reference: Alder Lake N platform EDS Doc# 645548.

Change-Id: I6dc494d1748e66b8b4058954f127ec226863e8af
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
---
 src/soc/intel/alderlake/include/soc/pcr_ids.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/alderlake/include/soc/pcr_ids.h b/src/soc/intel/alderlake/include/soc/pcr_ids.h
index f125ee20cd..623a8140ba 100644
--- a/src/soc/intel/alderlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/alderlake/include/soc/pcr_ids.h
@@ -33,6 +33,9 @@
 #define PID_ITSS	0xc4
 #define PID_SERIALIO	0xcb
 
+/* eMMC Port ID for Alder Lake N */
+#define PID_EMMC	0xa1
+
 /* CPU Port IDs */
 #define PID_CPU_GPIOCOM0	0xb7
 #define PID_CPU_GPIOCOM1	0xb8