soc/intel/cannonlake: Add new cannon lake PCH-H support

Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake
RVP8 platforms.

- Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB,
  SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device.

- Add new device IDs to intel common code respectively.

- Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8.

- CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c
  is modified accordingly.

- Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8.

BUG=None
TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices
     are enumerated and cross checked devices ids in serial logs and UEFI shell.

Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28718
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/common/block/cse/cse.c

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2017 Intel Inc.
+ * Copyright 2017-2018 Intel Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -518,6 +518,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_GLK_CSE0,
 	PCI_DEVICE_ID_INTEL_CNL_CSE0,
 	PCI_DEVICE_ID_INTEL_SKL_CSE0,
+	PCI_DEVICE_ID_INTEL_CNP_H_CSE0,
 	0,
 };
 

src/soc/intel/common/block/dsp/dsp.c

@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  *  * Copyright (C) 2016 Google Inc.
- *  * Copyright (C) 2017 Intel Corporation.
+ *  * Copyright (C) 2017-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -31,6 +31,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_AUDIO,
 	PCI_DEVICE_ID_INTEL_GLK_AUDIO,
 	PCI_DEVICE_ID_INTEL_SKL_AUDIO,
+	PCI_DEVICE_ID_INTEL_CNP_H_AUDIO,
 	0,
 };
 

src/soc/intel/common/block/graphics/graphics.c

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017 Intel Corp.
+ * Copyright (C) 2017-2018 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -132,6 +132,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM,
 	PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM,
 	PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM,
+	PCI_DEVICE_ID_INTEL_CFL_H_GT2,
+	PCI_DEVICE_ID_INTEL_CFL_S_GT2,
 	0,
 };
 

src/soc/intel/common/block/i2c/i2c.c

@@ -213,6 +213,10 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_GLK_I2C5,
 	PCI_DEVICE_ID_INTEL_GLK_I2C6,
 	PCI_DEVICE_ID_INTEL_GLK_I2C7,
+	PCI_DEVICE_ID_INTEL_CNP_H_I2C0,
+	PCI_DEVICE_ID_INTEL_CNP_H_I2C1,
+	PCI_DEVICE_ID_INTEL_CNP_H_I2C2,
+	PCI_DEVICE_ID_INTEL_CNP_H_I2C3,
 	0,
 };
 

src/soc/intel/common/block/lpc/lpc.c

@@ -144,6 +144,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC,
 	PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC,
 	PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC,
+	PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370,
+	PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370,
 	0
 };
 

src/soc/intel/common/block/p2sb/p2sb.c

@@ -166,6 +166,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_APL_P2SB,
 	PCI_DEVICE_ID_INTEL_GLK_P2SB,
 	PCI_DEVICE_ID_INTEL_CNL_P2SB,
+	PCI_DEVICE_ID_INTEL_CNP_H_P2SB,
 	0,
 };
 

src/soc/intel/common/block/pcie/pcie.c

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -166,6 +166,30 @@ static const unsigned short pcie_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14,
 	PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15,
 	PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP3,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP4,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP5,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP6,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP7,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP8,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP9,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP10,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP11,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP12,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP13,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP14,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP15,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP16,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP17,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP18,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP19,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP20,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP21,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP22,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP23,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP24,
 	0
 };
 

src/soc/intel/common/block/pmc/pmc.c

@@ -126,6 +126,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_KBP_H_PMC,
 	PCI_DEVICE_ID_INTEL_APL_PMC,
 	PCI_DEVICE_ID_INTEL_GLK_PMC,
+	PCI_DEVICE_ID_INTEL_CNP_H_PMC,
 	0
 };
 

src/soc/intel/common/block/scs/sd.c

@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright 2017 Google Inc.
+ * Copyright (C) 2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -69,6 +70,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_SD,
 	PCI_DEVICE_ID_INTEL_GLK_SD,
 	PCI_DEVICE_ID_INTEL_SKL_SD,
+	PCI_DEVICE_ID_INTEL_CNP_H_SD,
 	0
 };
 

src/soc/intel/common/block/systemagent/systemagent.c

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -304,6 +304,8 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DEVICE_ID_INTEL_KBL_U_R,
 	PCI_DEVICE_ID_INTEL_KBL_ID_DT,
 	PCI_DEVICE_ID_INTEL_CFL_ID_U,
+	PCI_DEVICE_ID_INTEL_CFL_ID_H,
+	PCI_DEVICE_ID_INTEL_CFL_ID_S,
 	0
 };
 

src/soc/intel/common/block/uart/uart.c

@@ -262,6 +262,9 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_GLK_UART1,
 	PCI_DEVICE_ID_INTEL_GLK_UART2,
 	PCI_DEVICE_ID_INTEL_GLK_UART3,
+	PCI_DEVICE_ID_INTEL_CNP_H_UART0,
+	PCI_DEVICE_ID_INTEL_CNP_H_UART1,
+	PCI_DEVICE_ID_INTEL_CNP_H_UART2,
 	0,
 };
 

src/soc/intel/common/block/xdci/xdci.c

@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2017 Intel Corporation.
+ * Copyright (C) 2015-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -41,6 +41,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_LP_XDCI,
 	PCI_DEVICE_ID_INTEL_GLK_XDCI,
 	PCI_DEVICE_ID_INTEL_SPT_LP_XDCI,
+	PCI_DEVICE_ID_INTEL_CNP_H_XDCI,
 	0
 };
 

src/soc/intel/common/block/xhci/xhci.c

@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -42,6 +42,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_SPT_LP_XHCI,
 	PCI_DEVICE_ID_INTEL_SPT_H_XHCI,
 	PCI_DEVICE_ID_INTEL_KBP_H_XHCI,
+	PCI_DEVICE_ID_INTEL_CNP_H_XHCI,
 	0
 };