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nb/intel/i945: Move to C_ENVIRONMENT_BOOTBLOCK

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Console init in bootblock will be done in a separate CL.

Change-Id: Ia2405013f262d904aa82be323e928223dbb4296c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36795
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
2019-11-12 23:34:13 +01:00
committed by Patrick Georgi
parent dc584c3f22
commit e27c013f39
13 changed files with 38 additions and 77 deletions
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4
src/cpu/intel/car/core2/cache_as_ram.S
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@@ -18,14 +18,10 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
#else
#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
#endif
.global bootblock_pre_c_entry

8
src/cpu/intel/car/p4-netburst/cache_as_ram.S
View File

@@ -18,22 +18,14 @@
/* Macro to access Local APIC registers at default base. */
#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
/* Fixed location, ASSERTED in failover.ld if it changes. */
.set ap_sipi_vector_in_rom, 0xff
#endif
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
#else
#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
#endif
.global bootblock_pre_c_entry

9
src/cpu/intel/socket_441/Kconfig
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@@ -8,6 +8,11 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select CPU_INTEL_MODEL_106CX
select MMX
select SSE
select SETUP_XIP_CACHE
config C_ENV_BOOTBLOCK_SIZE
hex
default 0x4000
config DCACHE_RAM_BASE
hex
@@ -17,4 +22,8 @@ config DCACHE_RAM_SIZE
hex
default 0x8000
config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
endif # CPU_INTEL_SOCKET_441

3
src/cpu/intel/socket_441/Makefile.inc
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@@ -8,7 +8,8 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
bootblock-y += ../car/p4-netburst/cache_as_ram.S
bootblock-y += ../car/bootblock.c
postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c

8
src/cpu/intel/socket_m/Kconfig
View File

@@ -18,4 +18,12 @@ config DCACHE_RAM_SIZE
hex
default 0x8000
config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
config C_ENV_BOOTBLOCK_SIZE
hex
default 0x8000
endif

3
src/cpu/intel/socket_m/Makefile.inc
View File

@@ -9,7 +9,8 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
bootblock-y += ../car/core2/cache_as_ram.S
bootblock-y += ../car/bootblock.c
postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c