From 3dea2b63eeb8f97b31571f6f0eb37f38f9967b6b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 1 Oct 2020 22:50:12 +0200 Subject: [PATCH 001/262] soc/intel/common/block/systemagent/memmap.c: Align cached region When asked to place cbmem_top(), FSP does not seem to care about alignment. It can return an address that is MTRR poison, which will exhaust all variable MTRRs when trying to set up caching for CBMEM. This will make memory-mapped flash and TSEG caching fail as well. Safeguard against this by aligning the region to cache to half of its size, and move it upwards to compensate. It is assumed that caching memory above the provided bootloader TOLUM address is inconsequential. TEST=Boot Purism Librem Mini WHL, observe no MTRR exhaustion error messages in console. The boot process also feels more fluid. Change-Id: Ic64fd6d3d9e8ab4c78d68b910a476f9c4eb2d353 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45930 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Arthur Heymans Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/block/systemagent/memmap.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index 985f2c4814..27870b0cf7 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -6,6 +6,7 @@ #include #include #include +#include /* * Expected Host Memory Map (we don't know 100% and not all regions are present on all SoCs): @@ -55,18 +56,18 @@ void smm_region(uintptr_t *start, size_t *size) void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; + /* FSP does not seem to bother w.r.t. alignment when asked to place cbmem_top() */ + uintptr_t top_of_ram = ALIGN_UP((uintptr_t)cbmem_top(), 8 * MiB); /* * We need to make sure ramstage will be run cached. At this * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is + * Instruct postcar to cache 16 megs below cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); /* Cache the TSEG region */ postcar_enable_tseg_cache(pcf); From 995a7e25a1b84f01a07dacca043ec8cd17a5efd3 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Wed, 28 Oct 2020 17:08:54 -0600 Subject: [PATCH 002/262] soc/intel/xeon_sp; Use soc specific stack-port function Separate the get_stack_for_port into soc specific functions. This removes a #if in common code. Change-Id: Ib38a7d66947ded9b56193a9163e5128b2523e99c Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/46971 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- .../intel/xeon_sp/cpx/include/soc/soc_util.h | 1 + src/soc/intel/xeon_sp/cpx/soc_util.c | 22 ++++++++++ src/soc/intel/xeon_sp/nb_acpi.c | 44 +------------------ .../intel/xeon_sp/skx/include/soc/soc_util.h | 1 + src/soc/intel/xeon_sp/skx/soc_util.c | 28 ++++++++++++ 5 files changed, 53 insertions(+), 43 deletions(-) diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index f0c257508a..5f4a6f9e2f 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -26,5 +26,6 @@ int get_threads_per_package(void); const struct SystemMemoryMapHob *get_system_memory_map(void); void set_bios_init_completion(void); +int soc_get_stack_for_port(int port); #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index bc4a1e15b1..de6d8525c2 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -319,3 +319,25 @@ void set_bios_init_completion(void) /* And finally, take care of the SBSP */ set_bios_init_completion_for_package(sbsp_socket_id); } +/* + * EX: CPX-SP + * Ports Stack Stack(HOB) IioConfigIou + * ========================================== + * 0 CSTACK stack 0 IOU0 + * 1A..1D PSTACKZ stack 1 IOU1 + * 2A..2D PSTACK1 stack 2 IOU2 + * 3A..3D PSTACK2 stack 4 IOU3 + */ +int soc_get_stack_for_port(int port) +{ + if (port == PORT_0) + return CSTACK; + else if (port >= PORT_1A && port <= PORT_1D) + return PSTACK0; + else if (port >= PORT_2A && port <= PORT_2D) + return PSTACK1; + else if (port >= PORT_3A && port <= PORT_3D) + return PSTACK2; + else + return -1; +} diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 5955fa0e31..f6bf6edf90 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -142,48 +142,6 @@ static unsigned long acpi_fill_slit(unsigned long current) return current; } -/* - * EX: CPX-SP - * Ports Stack Stack(HOB) IioConfigIou - * ========================================== - * 0 CSTACK stack 0 IOU0 - * 1A..1D PSTACKZ stack 1 IOU1 - * 2A..2D PSTACK1 stack 2 IOU2 - * 3A..3D PSTACK2 stack 4 IOU3 - */ -static int get_stack_for_port(int port) -{ -#if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) - if (port == PORT_0) - return CSTACK; - else if (port >= PORT_1A && port <= PORT_1D) - return PSTACK0; - else if (port >= PORT_2A && port <= PORT_2D) - return PSTACK1; - else if (port >= PORT_3A && port <= PORT_3D) - return PSTACK2; - else - return -1; -#endif /* SOC_INTEL_COOPERLAKE_SP */ - -#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) - if (port == PORT_0) - return CSTACK; - else if (port >= PORT_1A && port <= PORT_1D) - return PSTACK0; - else if (port >= PORT_2A && port <= PORT_2D) - return PSTACK1; - else if (port >= PORT_3A && port <= PORT_3D) - return PSTACK2; - else if (port >= PORT_4A && port <= PORT_4D) - return PSTACK3; // MCP0 - else if (port >= PORT_5A && port <= PORT_5D) - return PSTACK4; // MCP1 - else - return -1; -#endif /* SOC_INTEL_SKYLAKE_SP */ -} - /* * This function adds PCIe bridge device entry in DMAR table. If it is called * in the context of ATSR subtable, it adds ATSR subtable when it is first called. @@ -193,7 +151,7 @@ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, bool is_atsr, bool *first) { - if (get_stack_for_port(port) != stack) + if (soc_get_stack_for_port(port) != stack) return 0; const uint32_t bus = iio_resource.StackRes[stack].BusBase; diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 25668301a4..cce542a1d5 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -27,5 +27,6 @@ const struct SystemMemoryMapHob *get_system_memory_map(void); void set_bios_init_completion(void); unsigned int soc_get_num_cpus(void); +int soc_get_stack_for_port(int port); #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 7dd954fd66..3af6483dfe 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -394,4 +394,32 @@ void xeonsp_init_cpu_config(void) } } +/* + * EX: SKX-SP + * Ports Stack Stack(HOB) IioConfigIou + * ========================================== + * 0 CSTACK stack 0 IOU0 + * 1A..1D PSTACKZ stack 1 IOU1 + * 2A..2D PSTACK1 stack 2 IOU2 + * 3A..3D PSTACK2 stack 3 IOU3 + * 5A..4D PSTACK3 stack 4 IOU4 + * 5A..5D PSTACK4 stack 5 IOU5 + */ +int soc_get_stack_for_port(int port) +{ + if (port == PORT_0) + return CSTACK; + else if (port >= PORT_1A && port <= PORT_1D) + return PSTACK0; + else if (port >= PORT_2A && port <= PORT_2D) + return PSTACK1; + else if (port >= PORT_3A && port <= PORT_3D) + return PSTACK2; + else if (port >= PORT_4A && port <= PORT_4D) + return PSTACK3; // MCP0 + else if (port >= PORT_5A && port <= PORT_5D) + return PSTACK4; // MCP1 + else + return -1; +} #endif From 2c707160a92ebb36577b886db6dc9a5ac8770163 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Sat, 31 Oct 2020 15:29:14 -0600 Subject: [PATCH 003/262] soc/intel/xeon_sp/acpi: Fix uncore dsdt for multiple cpus Fix the asl to use CONFIG_MAX_CPUS to create entries for multiple cpu uncores. Don't add the RTxx resource entries multiple times. The function is called for each CPUs. Change-Id: Ia4eb9716ae4bd72fb4eb98649105be629623cbef Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/47060 Reviewed-by: Jay Talbott Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/acpi/iiostack.asl | 2 +- src/soc/intel/xeon_sp/cpx/soc_acpi.c | 4 ++++ src/soc/intel/xeon_sp/skx/soc_acpi.c | 4 ++++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl index dca5569559..4b2b65bbc5 100644 --- a/src/soc/intel/xeon_sp/acpi/iiostack.asl +++ b/src/soc/intel/xeon_sp/acpi/iiostack.asl @@ -69,7 +69,7 @@ MAKE_IIO_DEV(01, 10) MAKE_IIO_DEV(02, 20) MAKE_IIO_DEV(03, 28) -#if MAX_SOCKET > 1 +#if (CONFIG_MAX_SOCKET > 1) MAKE_IIO_DEV(06, 40) MAKE_IIO_DEV(07, 50) MAKE_IIO_DEV(08, 60) diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index d60684bccb..c35c2482f4 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -60,6 +60,10 @@ void uncore_inject_dsdt(const struct device *device) { struct iiostack_resource stack_info = {0}; + /* Only add RTxx entries once. */ + if (device->bus->secondary != 0) + return; + get_iiostack_info(&stack_info); acpigen_write_scope("\\_SB"); diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index df2550c54a..b3926193da 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -104,6 +104,10 @@ void uncore_inject_dsdt(const struct device *device) const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); assert(hob != NULL && hob_size != 0); + /* Only add RTxx entries once. */ + if (device->bus->secondary != 0) + return; + acpigen_write_scope("\\_SB"); for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { IIO_RESOURCE_INSTANCE iio_resource = From 54e0fd21b1f916a3f152114027db1029a921fc55 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 29 Oct 2020 20:30:08 -0500 Subject: [PATCH 004/262] mb/purism/librem_whl: rename to librem_cnl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since Whiskeylake SoC code is actually a subset of soc/intel/cannonlake, rename the baseboard so that boards using other 'cannonlake family' SoCs (e.g., Cometlake) can be added with minimal confusion. Rename the mainboard dir and baseboard name, and adjust any references to them. Change-Id: I2af7977f1622070eb8bf8449bc8306f9d75b9851 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47050 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- .../purism/{librem_whl => librem_cnl}/Kconfig | 6 +++--- .../purism/{librem_whl => librem_cnl}/Kconfig.name | 2 +- .../purism/{librem_whl => librem_cnl}/Makefile.inc | 0 .../{librem_whl => librem_cnl}/acpi/mainboard.asl | 0 .../{librem_whl => librem_cnl}/board_info.txt | 2 +- .../purism/{librem_whl => librem_cnl}/devicetree.cb | 0 .../purism/{librem_whl => librem_cnl}/dsdt.asl | 0 .../purism/{librem_whl => librem_cnl}/ramstage.c | 0 .../purism/{librem_whl => librem_cnl}/romstage.c | 0 .../variants/librem_mini/data.vbt | Bin .../variants/librem_mini/gpio.c | 0 .../variants/librem_mini/hda_verb.c | 0 .../variants/librem_mini/include/variant/gpio.h | 0 13 files changed, 5 insertions(+), 5 deletions(-) rename src/mainboard/purism/{librem_whl => librem_cnl}/Kconfig (90%) rename src/mainboard/purism/{librem_whl => librem_cnl}/Kconfig.name (55%) rename src/mainboard/purism/{librem_whl => librem_cnl}/Makefile.inc (100%) rename src/mainboard/purism/{librem_whl => librem_cnl}/acpi/mainboard.asl (100%) rename src/mainboard/purism/{librem_whl => librem_cnl}/board_info.txt (85%) rename src/mainboard/purism/{librem_whl => librem_cnl}/devicetree.cb (100%) rename src/mainboard/purism/{librem_whl => librem_cnl}/dsdt.asl (100%) rename src/mainboard/purism/{librem_whl => librem_cnl}/ramstage.c (100%) rename src/mainboard/purism/{librem_whl => librem_cnl}/romstage.c (100%) rename src/mainboard/purism/{librem_whl => librem_cnl}/variants/librem_mini/data.vbt (100%) rename src/mainboard/purism/{librem_whl => librem_cnl}/variants/librem_mini/gpio.c (100%) rename src/mainboard/purism/{librem_whl => librem_cnl}/variants/librem_mini/hda_verb.c (100%) rename src/mainboard/purism/{librem_whl => librem_cnl}/variants/librem_mini/include/variant/gpio.h (100%) diff --git a/src/mainboard/purism/librem_whl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig similarity index 90% rename from src/mainboard/purism/librem_whl/Kconfig rename to src/mainboard/purism/librem_cnl/Kconfig index bc25fb5b3b..38be3806d5 100644 --- a/src/mainboard/purism/librem_whl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -1,4 +1,4 @@ -config BOARD_PURISM_BASEBOARD_LIBREM_WHL +config BOARD_PURISM_BASEBOARD_LIBREM_CNL def_bool n select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL @@ -13,11 +13,11 @@ config BOARD_PURISM_BASEBOARD_LIBREM_WHL select SPD_READ_BY_WORD select USE_LEGACY_8254_TIMER -if BOARD_PURISM_BASEBOARD_LIBREM_WHL +if BOARD_PURISM_BASEBOARD_LIBREM_CNL config MAINBOARD_DIR string - default "purism/librem_whl" + default "purism/librem_cnl" config MAINBOARD_FAMILY string diff --git a/src/mainboard/purism/librem_whl/Kconfig.name b/src/mainboard/purism/librem_cnl/Kconfig.name similarity index 55% rename from src/mainboard/purism/librem_whl/Kconfig.name rename to src/mainboard/purism/librem_cnl/Kconfig.name index 41a4003102..326165ba07 100644 --- a/src/mainboard/purism/librem_whl/Kconfig.name +++ b/src/mainboard/purism/librem_cnl/Kconfig.name @@ -1,3 +1,3 @@ config BOARD_PURISM_LIBREM_MINI bool "Librem Mini" - select BOARD_PURISM_BASEBOARD_LIBREM_WHL + select BOARD_PURISM_BASEBOARD_LIBREM_CNL diff --git a/src/mainboard/purism/librem_whl/Makefile.inc b/src/mainboard/purism/librem_cnl/Makefile.inc similarity index 100% rename from src/mainboard/purism/librem_whl/Makefile.inc rename to src/mainboard/purism/librem_cnl/Makefile.inc diff --git a/src/mainboard/purism/librem_whl/acpi/mainboard.asl b/src/mainboard/purism/librem_cnl/acpi/mainboard.asl similarity index 100% rename from src/mainboard/purism/librem_whl/acpi/mainboard.asl rename to src/mainboard/purism/librem_cnl/acpi/mainboard.asl diff --git a/src/mainboard/purism/librem_whl/board_info.txt b/src/mainboard/purism/librem_cnl/board_info.txt similarity index 85% rename from src/mainboard/purism/librem_whl/board_info.txt rename to src/mainboard/purism/librem_cnl/board_info.txt index e72dcdf2b7..ca61edd88d 100644 --- a/src/mainboard/purism/librem_whl/board_info.txt +++ b/src/mainboard/purism/librem_cnl/board_info.txt @@ -1,5 +1,5 @@ Vendor name: Purism -Board name: librem_whl +Board name: librem_cnl Category: desktop Release year: 2020 ROM package: SOIC-8 diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb similarity index 100% rename from src/mainboard/purism/librem_whl/devicetree.cb rename to src/mainboard/purism/librem_cnl/devicetree.cb diff --git a/src/mainboard/purism/librem_whl/dsdt.asl b/src/mainboard/purism/librem_cnl/dsdt.asl similarity index 100% rename from src/mainboard/purism/librem_whl/dsdt.asl rename to src/mainboard/purism/librem_cnl/dsdt.asl diff --git a/src/mainboard/purism/librem_whl/ramstage.c b/src/mainboard/purism/librem_cnl/ramstage.c similarity index 100% rename from src/mainboard/purism/librem_whl/ramstage.c rename to src/mainboard/purism/librem_cnl/ramstage.c diff --git a/src/mainboard/purism/librem_whl/romstage.c b/src/mainboard/purism/librem_cnl/romstage.c similarity index 100% rename from src/mainboard/purism/librem_whl/romstage.c rename to src/mainboard/purism/librem_cnl/romstage.c diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt b/src/mainboard/purism/librem_cnl/variants/librem_mini/data.vbt similarity index 100% rename from src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt rename to src/mainboard/purism/librem_cnl/variants/librem_mini/data.vbt diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c similarity index 100% rename from src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c rename to src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c similarity index 100% rename from src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c rename to src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h b/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/gpio.h similarity index 100% rename from src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h rename to src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/gpio.h From bf355e7159b3c812f748e366fdffdf0eade77e9d Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 29 Oct 2020 20:37:56 -0500 Subject: [PATCH 005/262] mb/purism/librem_cnl: Adjust in preparation for new variants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Move the SoC select to board config (vs baseboard config) - Qualify the VGA PCI ID and CBFS size values based on board selection - Move devicetree to variant dir and add Kconfig entry - Use a separate board_info.txt for the baseboard and each variant Change-Id: I4764f2c1243ea49bd08e0735865cc3cb7a66441f Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47051 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- src/mainboard/purism/librem_cnl/Kconfig | 9 ++++++--- src/mainboard/purism/librem_cnl/Kconfig.name | 1 + src/mainboard/purism/librem_cnl/board_info.txt | 4 ++-- .../librem_cnl/variants/librem_mini/board_info.txt | 8 ++++++++ .../librem_cnl/{ => variants/librem_mini}/devicetree.cb | 0 5 files changed, 17 insertions(+), 5 deletions(-) create mode 100644 src/mainboard/purism/librem_cnl/variants/librem_mini/board_info.txt rename src/mainboard/purism/librem_cnl/{ => variants/librem_mini}/devicetree.cb (100%) diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig index 38be3806d5..464350ce8c 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -9,7 +9,6 @@ config BOARD_PURISM_BASEBOARD_LIBREM_CNL select NO_UART_ON_SUPERIO select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select SOC_INTEL_WHISKEYLAKE select SPD_READ_BY_WORD select USE_LEGACY_8254_TIMER @@ -31,9 +30,13 @@ config VARIANT_DIR string default "librem_mini" if BOARD_PURISM_LIBREM_MINI +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + config CBFS_SIZE hex - default 0x800000 + default 0x800000 if BOARD_PURISM_LIBREM_MINI config MAX_CPUS int @@ -49,7 +52,7 @@ config DIMM_SPD_SIZE config VGA_BIOS_ID string - default "8086,3ea0" + default "8086,3ea0" if BOARD_PURISM_LIBREM_MINI config PXE_ROM_ID string diff --git a/src/mainboard/purism/librem_cnl/Kconfig.name b/src/mainboard/purism/librem_cnl/Kconfig.name index 326165ba07..83f1495ab1 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig.name +++ b/src/mainboard/purism/librem_cnl/Kconfig.name @@ -1,3 +1,4 @@ config BOARD_PURISM_LIBREM_MINI bool "Librem Mini" select BOARD_PURISM_BASEBOARD_LIBREM_CNL + select SOC_INTEL_WHISKEYLAKE diff --git a/src/mainboard/purism/librem_cnl/board_info.txt b/src/mainboard/purism/librem_cnl/board_info.txt index ca61edd88d..6c7620ce1e 100644 --- a/src/mainboard/purism/librem_cnl/board_info.txt +++ b/src/mainboard/purism/librem_cnl/board_info.txt @@ -1,6 +1,6 @@ Vendor name: Purism -Board name: librem_cnl -Category: desktop +Board name: Librem Cannonlake baseboard +Category: misc Release year: 2020 ROM package: SOIC-8 ROM protocol: SPI diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/board_info.txt b/src/mainboard/purism/librem_cnl/variants/librem_mini/board_info.txt new file mode 100644 index 0000000000..843ff9ff7c --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Purism +Board name: Librem Mini +Category: desktop +Release year: 2020 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/purism/librem_cnl/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb similarity index 100% rename from src/mainboard/purism/librem_cnl/devicetree.cb rename to src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb From 3d8b6e25bbb688fee09f540ef331f4846b688669 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 2 Nov 2020 13:40:11 +0100 Subject: [PATCH 006/262] sb/intel/bd82x6x/sata.c: Replace bad uses of `find_resource` The `find_resource` function will never return null (will die instead). Given that the existing code gracefully handles null pointers already, it is reasonable to replace these function calls with `probe_resource`. Change-Id: Ibd8f5ebd561cbde22ce5cd83de8270177bad1344 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47101 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/bd82x6x/sata.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 484f0f11a2..de1be62031 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -40,28 +40,28 @@ static void sata_read_resources(struct device *dev) if (sata_mode != 2) return; - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (res) { res->base = 0x1f0; res->size = 8; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } - res = find_resource(dev, PCI_BASE_ADDRESS_1); + res = probe_resource(dev, PCI_BASE_ADDRESS_1); if (res) { res->base = 0x3f4; res->size = 4; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } - res = find_resource(dev, PCI_BASE_ADDRESS_2); + res = probe_resource(dev, PCI_BASE_ADDRESS_2); if (res) { res->base = 0x170; res->size = 8; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } - res = find_resource(dev, PCI_BASE_ADDRESS_3); + res = probe_resource(dev, PCI_BASE_ADDRESS_3); if (res) { res->base = 0x374; res->size = 4; @@ -77,7 +77,7 @@ static void sata_set_resources(struct device *dev) if (sata_mode == 2) { unsigned int i; for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_3; i += 4) { - struct resource *const res = find_resource(dev, i); + struct resource *const res = probe_resource(dev, i); if (res) res->flags &= ~IORESOURCE_FIXED; } From 55a890fe3a4edede1580ab5c1d57dfe8e194e3f7 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 00:38:50 +0000 Subject: [PATCH 007/262] Revert "broadwell: Switch to using common ACPI _SWS code" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 81a4c85acf664156bb68807f681cd40928bf8267. Reason for revert: Blocks merging Haswell and Broadwell together. Tested on out-of-tree Acer Aspire E5-573, still boots. Change-Id: I29c4ad9174ab84c7e9111daa0491ede9e1d639b4 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46734 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/broadwell/acpi/platform.asl | 20 +++++++- src/soc/intel/broadwell/ramstage.c | 59 ++++++++++++++++++----- 3 files changed, 64 insertions(+), 16 deletions(-) diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 2430be61f5..6e57f0aa8e 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -34,7 +34,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_MONOTONIC_TIMER select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE - select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT select INTEL_GMA_ACPI select HAVE_POWER_STATE_AFTER_FAILURE diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/soc/intel/broadwell/acpi/platform.asl index f404352504..880b2061ec 100644 --- a/src/soc/intel/broadwell/acpi/platform.asl +++ b/src/soc/intel/broadwell/acpi/platform.asl @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Enable ACPI _SWS methods */ -#include #include /* @@ -19,3 +17,21 @@ Method (_WAK, 1) { Return (Package (){ 0, 0 }) } + +Scope (\_SB) +{ + Method (_SWS) + { + /* Index into PM1 for device that caused wake */ + Return (\PM1I) + } +} + +Scope (\_GPE) +{ + Method (_SWS) + { + /* Index into GPE for device that caused wake */ + Return (\GPEI) + } +} diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index c414d62192..57abf95207 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -2,32 +2,63 @@ #include #include +#include #include #include #include #include #include #include -#include -#include -/* Save wake source information for calculating ACPI _SWS values */ -int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) +/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */ +static void save_acpi_wake_source(struct global_nvs *gnvs) { struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - static uint32_t gpe0_sts[GPE0_REG_MAX]; - int i; + uint16_t pm1; + int gpe_reg; - assert(ps != NULL); + if (!ps) + return; - *pm1 = ps->pm1_sts & ps->pm1_en; + pm1 = ps->pm1_sts & ps->pm1_en; - /* Mask off GPE0 status bits that are not enabled */ - *gpe0 = &gpe0_sts[0]; - for (i = 0; i < GPE0_REG_MAX; i++) - gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i]; + /* Scan for first set bit in PM1 */ + for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) { + if (pm1 & 1) + break; + pm1 >>= 1; + } - return GPE0_REG_MAX; + /* If unable to determine then return -1 */ + if (gnvs->pm1i >= 16) + gnvs->pm1i = -1; + + /* Scan for first set bit in GPE registers */ + gnvs->gpei = -1; + for (gpe_reg = 0; gpe_reg < GPE0_REG_MAX; gpe_reg++) { + u32 gpe = ps->gpe0_sts[gpe_reg] & ps->gpe0_en[gpe_reg]; + int start = gpe_reg * GPE0_REG_SIZE; + int end = start + GPE0_REG_SIZE; + + if (gpe == 0) { + if (!gnvs->gpei) + gnvs->gpei = end; + continue; + } + + for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) { + if (gpe & 1) + break; + gpe >>= 1; + } + } + + /* If unable to determine then return -1 */ + if (gnvs->gpei >= (GPE0_REG_MAX * GPE0_REG_SIZE)) + gnvs->gpei = -1; + + printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n", + gnvs->pm1i, gnvs->gpei); } static void s3_resume_prepare(void) @@ -40,6 +71,8 @@ static void s3_resume_prepare(void) if (!acpi_is_wakeup_s3()) memset(gnvs, 0, sizeof(struct global_nvs)); + else + save_acpi_wake_source(gnvs); } void broadwell_init_pre_device(void *chip_info) From 96a480d507a97c27aa13a93ef9bc9176f498a895 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 12:23:45 +0100 Subject: [PATCH 008/262] cpu/intel/haswell: Move smmrelocate.c MSR definitions to header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: Ia271718477ea227b9ba7e836b0abe02264778129 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46733 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/cpu/intel/haswell/haswell.h | 20 ++++++++++++++++++++ src/cpu/intel/haswell/smmrelocate.c | 16 ---------------- 2 files changed, 20 insertions(+), 16 deletions(-) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index e0e1e1cdd3..9349a3d654 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -76,6 +76,26 @@ #define MSR_CONFIG_TDP_CONTROL 0x64b #define MSR_TURBO_ACTIVATION_RATIO 0x64c +#define SMM_MCA_CAP_MSR 0x17d +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) + +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 + +#define SMM_FEATURE_CONTROL_MSR 0x4e0 +#define SMM_CPU_SAVE_EN (1 << 1) + +/* SMM save state MSRs */ +#define SMBASE_MSR 0xc20 +#define IEDBASE_MSR 0xc22 + +/* MTRR_CAP_MSR bit definitions */ +#define SMRR_SUPPORTED (1 << 11) +#define PRMRR_SUPPORTED (1 << 12) + /* P-state configuration */ #define PSS_MAX_ENTRIES 8 #define PSS_RATIO_STEP 2 diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 2fc20aab3d..9e3554f9e3 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -17,22 +17,6 @@ #include #include "haswell.h" -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 -#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 -#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) -/* SMM save state MSRs */ -#define SMBASE_MSR 0xc20 -#define IEDBASE_MSR 0xc22 - -#define SMRR_SUPPORTED (1 << 11) -#define PRMRR_SUPPORTED (1 << 12) - static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, struct smm_relocation_params *relo_params) From 4c2389e28c4fe0c153d3153732d353d5960150f5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 12:31:23 +0100 Subject: [PATCH 009/262] soc/intel/broadwell: Relocate PCH ACPI files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I7f87085c70149d02c544e2d43e1bdb58c7502d6d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46754 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/google/auron/dsdt.asl | 4 ++-- src/mainboard/google/jecht/dsdt.asl | 4 ++-- src/mainboard/intel/wtm2/dsdt.asl | 4 ++-- src/mainboard/purism/librem_bdw/dsdt.asl | 4 ++-- src/soc/intel/broadwell/{ => pch}/acpi/adsp.asl | 0 src/soc/intel/broadwell/{ => pch}/acpi/device_nvs.asl | 0 src/soc/intel/broadwell/{ => pch}/acpi/ehci.asl | 0 src/soc/intel/broadwell/{ => pch}/acpi/globalnvs.asl | 0 src/soc/intel/broadwell/{ => pch}/acpi/gpio.asl | 0 src/soc/intel/broadwell/{ => pch}/acpi/hda.asl | 0 src/soc/intel/broadwell/{ => pch}/acpi/irqlinks.asl | 0 src/soc/intel/broadwell/{ => pch}/acpi/lpc.asl | 0 src/soc/intel/broadwell/{ => pch}/acpi/pch.asl | 0 src/soc/intel/broadwell/{ => pch}/acpi/pcie.asl | 0 src/soc/intel/broadwell/{ => pch}/acpi/pcie_port.asl | 0 src/soc/intel/broadwell/{ => pch}/acpi/sata.asl | 0 src/soc/intel/broadwell/{ => pch}/acpi/serialio.asl | 0 src/soc/intel/broadwell/{ => pch}/acpi/smbus.asl | 0 src/soc/intel/broadwell/{ => pch}/acpi/xhci.asl | 0 19 files changed, 8 insertions(+), 8 deletions(-) rename src/soc/intel/broadwell/{ => pch}/acpi/adsp.asl (100%) rename src/soc/intel/broadwell/{ => pch}/acpi/device_nvs.asl (100%) rename src/soc/intel/broadwell/{ => pch}/acpi/ehci.asl (100%) rename src/soc/intel/broadwell/{ => pch}/acpi/globalnvs.asl (100%) rename src/soc/intel/broadwell/{ => pch}/acpi/gpio.asl (100%) rename src/soc/intel/broadwell/{ => pch}/acpi/hda.asl (100%) rename src/soc/intel/broadwell/{ => pch}/acpi/irqlinks.asl (100%) rename src/soc/intel/broadwell/{ => pch}/acpi/lpc.asl (100%) rename src/soc/intel/broadwell/{ => pch}/acpi/pch.asl (100%) rename src/soc/intel/broadwell/{ => pch}/acpi/pcie.asl (100%) rename src/soc/intel/broadwell/{ => pch}/acpi/pcie_port.asl (100%) rename src/soc/intel/broadwell/{ => pch}/acpi/sata.asl (100%) rename src/soc/intel/broadwell/{ => pch}/acpi/serialio.asl (100%) rename src/soc/intel/broadwell/{ => pch}/acpi/smbus.asl (100%) rename src/soc/intel/broadwell/{ => pch}/acpi/xhci.asl (100%) diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index 32c71dee97..a61a669411 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -16,7 +16,7 @@ DefinitionBlock( #include "acpi/thermal.asl" // global NVS and variables - #include + #include // CPU #include @@ -25,7 +25,7 @@ DefinitionBlock( Device (PCI0) { #include - #include + #include #include } } diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index 3746d4bb35..6af99b4a77 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -17,7 +17,7 @@ DefinitionBlock( #include // global NVS and variables - #include + #include // CPU #include @@ -26,7 +26,7 @@ DefinitionBlock( Device (PCI0) { #include - #include + #include } } diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index b3b2ca6766..c842e8b7f8 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -17,7 +17,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include + #include // CPU #include @@ -26,7 +26,7 @@ DefinitionBlock( Device (PCI0) { #include - #include + #include } } diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index 4d81e1530f..a4b5bd8ca8 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( #include /* Global NVS and variables */ - #include + #include /* CPU */ #include @@ -22,7 +22,7 @@ DefinitionBlock( Device (PCI0) { #include - #include + #include } } diff --git a/src/soc/intel/broadwell/acpi/adsp.asl b/src/soc/intel/broadwell/pch/acpi/adsp.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/adsp.asl rename to src/soc/intel/broadwell/pch/acpi/adsp.asl diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/soc/intel/broadwell/pch/acpi/device_nvs.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/device_nvs.asl rename to src/soc/intel/broadwell/pch/acpi/device_nvs.asl diff --git a/src/soc/intel/broadwell/acpi/ehci.asl b/src/soc/intel/broadwell/pch/acpi/ehci.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/ehci.asl rename to src/soc/intel/broadwell/pch/acpi/ehci.asl diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/globalnvs.asl rename to src/soc/intel/broadwell/pch/acpi/globalnvs.asl diff --git a/src/soc/intel/broadwell/acpi/gpio.asl b/src/soc/intel/broadwell/pch/acpi/gpio.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/gpio.asl rename to src/soc/intel/broadwell/pch/acpi/gpio.asl diff --git a/src/soc/intel/broadwell/acpi/hda.asl b/src/soc/intel/broadwell/pch/acpi/hda.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/hda.asl rename to src/soc/intel/broadwell/pch/acpi/hda.asl diff --git a/src/soc/intel/broadwell/acpi/irqlinks.asl b/src/soc/intel/broadwell/pch/acpi/irqlinks.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/irqlinks.asl rename to src/soc/intel/broadwell/pch/acpi/irqlinks.asl diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/lpc.asl rename to src/soc/intel/broadwell/pch/acpi/lpc.asl diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pch.asl rename to src/soc/intel/broadwell/pch/acpi/pch.asl diff --git a/src/soc/intel/broadwell/acpi/pcie.asl b/src/soc/intel/broadwell/pch/acpi/pcie.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pcie.asl rename to src/soc/intel/broadwell/pch/acpi/pcie.asl diff --git a/src/soc/intel/broadwell/acpi/pcie_port.asl b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pcie_port.asl rename to src/soc/intel/broadwell/pch/acpi/pcie_port.asl diff --git a/src/soc/intel/broadwell/acpi/sata.asl b/src/soc/intel/broadwell/pch/acpi/sata.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/sata.asl rename to src/soc/intel/broadwell/pch/acpi/sata.asl diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/serialio.asl rename to src/soc/intel/broadwell/pch/acpi/serialio.asl diff --git a/src/soc/intel/broadwell/acpi/smbus.asl b/src/soc/intel/broadwell/pch/acpi/smbus.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/smbus.asl rename to src/soc/intel/broadwell/pch/acpi/smbus.asl diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/pch/acpi/xhci.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/xhci.asl rename to src/soc/intel/broadwell/pch/acpi/xhci.asl From 1b85692fc4247659a188cba577ba8c35aa373fbd Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 30 Oct 2020 15:30:48 +0100 Subject: [PATCH 010/262] sb/intel/lynxpoint/sata.c: Don't enable Bus Master MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bus Master is not required and reference code does not set it. Tested on Asrock B85M Pro4, still boots from SATA SSD with TianoCore. Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47031 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Michael Niewöhner --- src/southbridge/intel/lynxpoint/sata.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 510440b76a..e1a2fa5a57 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -41,9 +41,8 @@ static void sata_init(struct device *dev) /* SATA configuration */ - /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + /* Enable memory space decoding for ABAR */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); if (config->ide_legacy_combined) { printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); From 7c36dc12df01ed168169b9abcb374d570cf458af Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 2 Nov 2020 14:00:35 -0800 Subject: [PATCH 011/262] soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix This change adds elog.c to smm-y for Tiger lake and Jasper Lake platforms to enable the logging of wake sources in eventlog for S0ix. BUG=b:172272078,b:169731044 BRANCH=volteer TEST=Verified on volteer that wake sources are correctly logged for S0ix: 8 | 2020-11-02 13:54:27 | S0ix Enter 9 | 2020-11-02 13:54:33 | S0ix Exit 10 | 2020-11-02 13:54:33 | Wake Source | RTC Alarm | 0 11 | 2020-11-02 13:54:49 | S0ix Enter 12 | 2020-11-02 13:54:54 | S0ix Exit 13 | 2020-11-02 13:54:54 | Wake Source | Power Button | 0 14 | 2020-11-02 13:55:04 | S0ix Enter 15 | 2020-11-02 13:55:10 | S0ix Exit 16 | 2020-11-02 13:55:10 | Wake Source | GPE # | 112 Signed-off-by: Furquan Shaikh Change-Id: Ie1c40dfba6c82ca45a21d35c5a2725e4d30855d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47141 Reviewed-by: Tim Wawrzynczak Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/Makefile.inc | 1 + src/soc/intel/tigerlake/Makefile.inc | 1 + 2 files changed, 2 insertions(+) diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 1cba218700..209d8a2661 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -51,6 +51,7 @@ smm-y += pmc.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += elog.c verstage-y += gpio.c diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index c4f71c78b3..a25d0a4ee0 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -50,6 +50,7 @@ smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += elog.c verstage-y += gpio.c From 3cea0594df500c2f08448ea4e5383fab63a7ab77 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 2 Nov 2020 14:19:14 -0800 Subject: [PATCH 012/262] mb/google/volteer: Log EC events in case of S0ix resume This change adds the callback `elog_gsmi_cb_mainboard_log_wake_source()` to volteer to enable logging of EC events in case of S0ix resume. BUG=b:172272078 BRANCH=volteer TEST=Verified that EC events are logged correctly for S0ix resume: 11 | 2020-11-02 14:11:05 | S0ix Enter 12 | 2020-11-02 14:11:08 | S0ix Exit 13 | 2020-11-02 14:11:08 | Wake Source | Power Button | 0 14 | 2020-11-02 14:11:08 | EC Event | Power Button 15 | 2020-11-02 14:11:17 | S0ix Enter 16 | 2020-11-02 14:11:21 | S0ix Exit 17 | 2020-11-02 14:11:21 | Wake Source | GPE # | 112 18 | 2020-11-02 14:11:21 | EC Event | Lid Open Signed-off-by: Furquan Shaikh Change-Id: I7aa9dc2470da3226925927f2a0cc39fdd426e3b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47142 Reviewed-by: Tim Wawrzynczak Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/smihandler.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/volteer/smihandler.c b/src/mainboard/google/volteer/smihandler.c index 5b3e38ca70..adb60fedbe 100644 --- a/src/mainboard/google/volteer/smihandler.c +++ b/src/mainboard/google/volteer/smihandler.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include +#include #include #include @@ -22,3 +24,8 @@ int mainboard_smi_apmc(u8 apmc) MAINBOARD_EC_SMI_EVENTS); return 0; } + +void elog_gsmi_cb_mainboard_log_wake_source(void) +{ + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS); +} From b38d6bbe1c74309f078915c2d467475bb4144943 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 28 Oct 2020 18:24:56 +0100 Subject: [PATCH 013/262] soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T The CAR set up by FSP-T is at base 0xfe800000 and has a 0x200000 size. FSP-M seems to have a very large stack usage so it would overflow other car symbols located below the coreboot stack such as timestamps and the pre-ram console, which are now fixed. TEST: boot with ocp/deltalake. Change-Id: I886f9391ad79fcfa0724109393e3781a08d954b4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/46895 Reviewed-by: Angel Pons Reviewed-by: Christian Walter Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/Kconfig | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 975afc9e26..28e7b83386 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -27,22 +27,25 @@ config PCR_BASE_ADDRESS config DCACHE_RAM_BASE hex - default 0xfe8b0000 + default 0xfe800000 config DCACHE_RAM_SIZE hex - default 0x170000 + default 0x1fff00 help The size of the cache-as-ram region required during bootblock - and/or romstage. + and/or romstage. FSP-T reserves the upper 0x100 for + FspReservedBuffer. config DCACHE_BSP_STACK_SIZE hex - default 0xA0000 + default 0x140000 help The amount of anticipated stack usage in CAR by bootblock and other stages. It needs to include FSP-M stack requirement and - CB romstage stack requirement. + CB romstage stack requirement. The integration documentation + says this needs to be 256KiB, but practice show this needs to + be a lot more. config CPU_MICROCODE_CBFS_LOC hex @@ -67,11 +70,13 @@ config STACK_SIZE config FSP_TEMP_RAM_SIZE hex depends on FSP_USES_CB_STACK - default 0xA0000 + default 0x40000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know - the exact FSP requirement for Heap setup. + the exact FSP requirement for Heap setup. The FSP integration + documentation says this needs to be at least 128KiB, but practice + show this needs to be 256KiB or more. config SOC_INTEL_COMMON_BLOCK_P2SB def_bool y From b5f580e03c8797278bebec66f30eeae6bf41fab8 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 29 Oct 2020 12:25:44 +0100 Subject: [PATCH 014/262] mb/prodrive/hermes: Set tcc offset to 1 Prevent early throttling when the ambient temperature is high. Change-Id: Ie6881c9c0942aae3e43509170352271a74244d42 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/47094 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese Reviewed-by: Angel Pons --- .../prodrive/hermes/variants/baseboard/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 2c0c26a92f..1bf65ff5a1 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -124,7 +124,7 @@ chip soc/intel/cannonlake register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Thermal - register "tcc_offset" = "6" # TCC of 94C + register "tcc_offset" = "1" # TCC of 99C # Disable S0ix From 5c7311a5248ee2e021a163d49234d5412fba6ad4 Mon Sep 17 00:00:00 2001 From: Jes Klinke Date: Fri, 30 Oct 2020 13:23:14 -0700 Subject: [PATCH 015/262] mb/google/volteer: clang-format mainboard.c This CL is entirely generated by running the automatic formatter on this one file. BUG=None TEST=abuild -t GOOGLE_VOLTEER2 -c max -x Change-Id: Ibdd8cc2222e7af11c11df963b088ca2db07a3214 Signed-off-by: Jes Bodi Klinke Reviewed-on: https://review.coreboot.org/c/coreboot/+/47048 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/volteer/mainboard.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 016572a39f..acba9722dc 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -102,8 +102,7 @@ void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg) return; } - if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && - cr50_is_long_interrupt_pulse_enabled()) { + if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && cr50_is_long_interrupt_pulse_enabled()) { printk(BIOS_INFO, "Enabling S0i3.4\n"); } else { /* @@ -126,8 +125,7 @@ static void mainboard_chip_init(void *chip_info) base_pads = variant_base_gpio_table(&base_num); override_pads = variant_override_gpio_table(&override_num); - gpio_configure_pads_with_override(base_pads, base_num, - override_pads, override_num); + gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); } void mainboard_silicon_init_params(FSP_S_CONFIG *params) @@ -135,14 +133,13 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) bool has_usb4; /* If device doesn't have USB4 hardware, disable tbt */ - has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || - fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3))); + has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) + || fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3))); if (!has_usb4) - memset(params->ITbtPcieRootPortEn, - 0, - ARRAY_SIZE(params->ITbtPcieRootPortEn) * - sizeof(*params->ITbtPcieRootPortEn)); + memset(params->ITbtPcieRootPortEn, 0, + ARRAY_SIZE(params->ITbtPcieRootPortEn) + * sizeof(*params->ITbtPcieRootPortEn)); } struct chip_operations mainboard_ops = { From 50526d5a307bf614d8ca3107836c93dad3ee1dd0 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 2 Nov 2020 21:32:41 +0100 Subject: [PATCH 016/262] mb/emulation/qemu-aarch64: Add a timestamp region The romstage region is moved up a bit more to satisfy the MMU. Change-Id: I00c2b4972495fa669d4dc2a52f298a0e4d0cf5ff Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47105 Reviewed-by: Angel Pons Reviewed-by: Christian Walter Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/mainboard/emulation/qemu-aarch64/memlayout.ld | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld index f739ddf4f7..cee77cd45f 100644 --- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -21,7 +21,8 @@ SECTIONS BOOTBLOCK(0x60010000, 64K) STACK(0x60020000, 62K) FMAP_CACHE(0x6002F800, 2K) - ROMSTAGE(0x60030000, 128K) + TIMESTAMP(0x60030000, 1K) + ROMSTAGE(0x60031000, 128K) TTB(0x60070000, 128K) RAMSTAGE(0x600b0000, 16M) From 5193312e1e26d3e9e865cb4584b823cfe2e52f0d Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 2 Nov 2020 18:08:14 +0100 Subject: [PATCH 017/262] util/sconfig: Report which key is duplicate It slightly helps debugging issues when you know what to look out for. Change-Id: I21eafaf8291701316aa920e458ba74535121b0a1 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/47103 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Stefan Reinauer Reviewed-by: Angel Pons --- util/sconfig/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index a7b2ce676e..1fd4404942 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -872,7 +872,7 @@ static void add_reg(struct reg **const head, char *const name, char *const val) for (cur = *head; cur != NULL; prev = cur, cur = cur->next) { const int sort = strcmp(r->key, cur->key); if (sort == 0) { - printf("ERROR: duplicate 'register' key.\n"); + printf("ERROR: duplicate 'register' key '%s'.\n", r->key); exit(1); } if (sort < 0) From 6df38700123820fa95ad3de5bfaef6def1a112f2 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Sat, 24 Oct 2020 16:23:45 -0600 Subject: [PATCH 018/262] soc/intel/xeon_sp: Pass IIO_RESOURCE_INSTANCE as pointer IIO_RESOURCE_INSTANCE is a large struct, so it should be passed as a constant pointer rather than making a copy. Found-by: Coverity CID 1432759 Change-Id: Iebbb4d292f4d956e767bda28cbf20b0318586510 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/46729 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/nb_acpi.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index f6bf6edf90..cf397f7897 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -147,16 +147,16 @@ static unsigned long acpi_fill_slit(unsigned long current) * in the context of ATSR subtable, it adds ATSR subtable when it is first called. */ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, - int port, int stack, IIO_RESOURCE_INSTANCE iio_resource, uint32_t pcie_seg, + int port, int stack, const IIO_RESOURCE_INSTANCE *iio_resource, uint32_t pcie_seg, bool is_atsr, bool *first) { if (soc_get_stack_for_port(port) != stack) return 0; - const uint32_t bus = iio_resource.StackRes[stack].BusBase; - const uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device; - const uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function; + const uint32_t bus = iio_resource->StackRes[stack].BusBase; + const uint32_t dev = iio_resource->PcieInfo.PortInfo[port].Device; + const uint32_t func = iio_resource->PcieInfo.PortInfo[port].Function; const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID); @@ -253,7 +253,7 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket, hob->PlatformData.IIO_resource[socket]; for (int p = PORT_0; p < MAX_PORTS; ++p) current += acpi_create_dmar_ds_pci_br_for_port(current, p, stack, - iio_resource, pcie_seg, false, NULL); + &iio_resource, pcie_seg, false, NULL); // Add VMD if (hob->PlatformData.VMDStackEnable[socket][stack] && @@ -317,7 +317,7 @@ static unsigned long acpi_create_atsr(unsigned long current, const IIO_UDS *hob) if (socket == 0 && p == PORT_0) continue; current += acpi_create_dmar_ds_pci_br_for_port(current, p, - stack, iio_resource, pcie_seg, true, &first); + stack, &iio_resource, pcie_seg, true, &first); } } if (tmp != current) From a08328ecffdf3eeb9aeec400361a48266bcf0bf2 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 25 Oct 2020 12:37:21 +0100 Subject: [PATCH 019/262] util/qemu: Add `qemu` make target Add some mechanics to automatically have a `qemu` make target for supported configurations. So with a QEMU target selected in Kconfig, one would ideally only have to run `make qemu` to test things. There are some notable variables that can be set or adapted in `Makefile.inc` files, the make command line or the environment. Primarily for `Makefile.inc` use: QEMU-y the QEMU executable QEMU_CFG-y a QEMU config that sets the available default devices, used to run more comprehensive tests by default, e.g. many more PCI devices For general use: QEMU_ARGS additional command line arguments (default: -serial stdio) QEMU_EXTRA_CFGS additional config files that can add devices QEMU_CFG_ARGS gathers config file related arguments, can be used to override a default config (QEMU_CFG-y) Examples: $ # Run coreboot's default config with additional command line args $ make qemu QEMU_ARGS="-cdrom site-local/grml64-small_2018.12.iso" $ # Force QEMU's built-in config $ make qemu QEMU_CFG_ARGS= Change-Id: I658f86e05df416ae09be6d432f9a80f7f71f9f75 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/46767 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Stefan Reinauer --- Makefile.inc | 2 +- util/qemu/Makefile.inc | 46 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 util/qemu/Makefile.inc diff --git a/Makefile.inc b/Makefile.inc index a6418b1327..b3868a5fbb 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -83,7 +83,7 @@ subdirs-y += src/superio subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*) subdirs-y += src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool -subdirs-y += util/futility util/marvell util/bincfg util/supermicro +subdirs-y += util/futility util/marvell util/bincfg util/supermicro util/qemu subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += src/security diff --git a/util/qemu/Makefile.inc b/util/qemu/Makefile.inc new file mode 100644 index 0000000000..3346349844 --- /dev/null +++ b/util/qemu/Makefile.inc @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: BSD-3-Clause + +# This automatically adds a `qemu` make target if a compatible +# configuration is selected. There are some notable variables +# that can be set or adapted in `Makefile.inc` files, the make +# command line or the environment: +# +# Primarily for `Makefile.inc` use: +# QEMU-y the QEMU executable +# QEMU_CFG-y a QEMU config that sets the available default devices, +# used to run more comprehensive tests by default, +# e.g. many more PCI devices +# +# For general use: +# QEMU_ARGS additional command line arguments (default: -serial stdio) +# QEMU_EXTRA_CFGS additional config files that can add devices +# +# QEMU_CFG_ARGS gathers config file related arguments, +# can be used to override a default config (QEMU_CFG-y) +# +# Examples: +# +# $ # Run coreboot's default config with additional command line args +# $ make qemu QEMU_ARGS="-cdrom site-local/grml64-small_2018.12.iso" +# +# $ # Force QEMU's built-in config +# $ make qemu QEMU_CFG_ARGS= + +QEMU-$(CONFIG_BOARD_EMULATION_QEMU_X86_I440FX) ?= qemu-system-x86_64 -M pc +QEMU-$(CONFIG_BOARD_EMULATION_QEMU_X86_Q35) ?= qemu-system-x86_64 -M q35 + +ifneq ($(QEMU-y),) + +QEMU_ARGS ?= -serial stdio +QEMU_EXTRA_CFGS ?= + +QEMU_CFG_ARGS ?= \ + $(if $(QEMU_CFG-y),-nodefaults) \ + $(addprefix -readconfig ,$(QEMU_CFG-y) $(QEMU_EXTRA_CFGS)) + +qemu: $(obj)/coreboot.rom + $(QEMU-y) $(QEMU_CFG_ARGS) $(QEMU_ARGS) -bios $< + +.PHONY: qemu + +endif From 9e20e2f1587b4bba2db41a8279e070eac6ddd92b Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 25 Oct 2020 14:41:40 +0100 Subject: [PATCH 020/262] util/qemu: Add comprehensive default config for QEMU Q35 This config tries to mimic the actual devices of a mainboard with Intel's Q35 chipset. It provides a much better base to test coreboot (e.g. its allocator) and payloads. Change-Id: Id465016e37ee75628a55b9da68facb4ae0efe822 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/46768 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Stefan Reinauer --- util/qemu/Makefile.inc | 2 + util/qemu/q35-base.cfg | 180 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 182 insertions(+) create mode 100644 util/qemu/q35-base.cfg diff --git a/util/qemu/Makefile.inc b/util/qemu/Makefile.inc index 3346349844..651ef21635 100644 --- a/util/qemu/Makefile.inc +++ b/util/qemu/Makefile.inc @@ -27,7 +27,9 @@ # $ make qemu QEMU_CFG_ARGS= QEMU-$(CONFIG_BOARD_EMULATION_QEMU_X86_I440FX) ?= qemu-system-x86_64 -M pc + QEMU-$(CONFIG_BOARD_EMULATION_QEMU_X86_Q35) ?= qemu-system-x86_64 -M q35 +QEMU_CFG-$(CONFIG_BOARD_EMULATION_QEMU_X86_Q35) ?= util/qemu/q35-base.cfg ifneq ($(QEMU-y),) diff --git a/util/qemu/q35-base.cfg b/util/qemu/q35-base.cfg new file mode 100644 index 0000000000..87dcfcd6b0 --- /dev/null +++ b/util/qemu/q35-base.cfg @@ -0,0 +1,180 @@ +# $ qemu-system-x86_64 -nodefaults -readconfig q35-base.cfg -readconfig ... +# +# Devices that show up even with `-nodefaults`: +# 00.0 Host bridge +# 1f.0 LPC bridge +# 1f.2 SATA controller (AHCI mode) +# 1f.3 SMBus controller + +[machine] + type = "q35" + accel = "kvm:tcg" + +[memory] + size = "1024" + + +[device "q35-peg"] + driver = "pcie-root-port" + bus = "pcie.0" + addr = "01.0" + + +[device "q35-igpu"] + driver = "VGA" + bus = "pcie.0" + addr = "02.0" + + +[netdev "hostnet"] + type = "user" + +[device "net"] + driver = "e1000" + netdev = "hostnet" + bus = "pcie.0" + addr = "19.0" + + +[device "ich9-ehci-2"] + driver = "ich9-usb-ehci2" + multifunction = "on" + bus = "pcie.0" + addr = "1a.7" + +[device "ich9-uhci-4"] + driver = "ich9-usb-uhci4" + multifunction = "on" + bus = "pcie.0" + addr = "1a.0" + masterbus = "ich9-ehci-2.0" + firstport = "0" + +[device "ich9-uhci-5"] + driver = "ich9-usb-uhci5" + multifunction = "on" + bus = "pcie.0" + addr = "1a.1" + masterbus = "ich9-ehci-2.0" + firstport = "2" + +[device "ich9-uhci-6"] + driver = "ich9-usb-uhci6" + multifunction = "on" + bus = "pcie.0" + addr = "1a.2" + masterbus = "ich9-ehci-2.0" + firstport = "4" + + +[device "ich9-hda-audio"] + driver = "ich9-intel-hda" + bus = "pcie.0" + addr = "1b.0" + +[device "ich9-hda-duplex"] + driver = "hda-duplex" + bus = "ich9-hda-audio.0" + cad = "0" + + +[device "ich9-pcie-port-1"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.0" + port = "1" + chassis = "1" + +[device "ich9-pcie-port-2"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.1" + port = "2" + chassis = "2" + +[device "ich9-pcie-port-3"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.2" + port = "3" + chassis = "3" + +[device "ich9-pcie-port-4"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.3" + port = "4" + chassis = "4" + +[device "ich9-pcie-port-5"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.4" + port = "5" + chassis = "5" + +[device "ich9-pcie-port-6"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.5" + port = "6" + chassis = "6" + +[device "ich9-pcie-port-7"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.6" + port = "7" + chassis = "7" + +[device "ich9-pcie-port-8"] + driver = "ioh3420" + multifunction = "on" + bus = "pcie.0" + addr = "1c.7" + port = "8" + chassis = "8" + + +[device "ich9-ehci-1"] + driver = "ich9-usb-ehci1" + multifunction = "on" + bus = "pcie.0" + addr = "1d.7" + +[device "ich9-uhci-1"] + driver = "ich9-usb-uhci1" + multifunction = "on" + bus = "pcie.0" + addr = "1d.0" + masterbus = "ich9-ehci-1.0" + firstport = "0" + +[device "ich9-uhci-2"] + driver = "ich9-usb-uhci2" + multifunction = "on" + bus = "pcie.0" + addr = "1d.1" + masterbus = "ich9-ehci-1.0" + firstport = "2" + +[device "ich9-uhci-3"] + driver = "ich9-usb-uhci3" + multifunction = "on" + bus = "pcie.0" + addr = "1d.2" + masterbus = "ich9-ehci-1.0" + firstport = "4" + + +[device "ich9-pci-bridge"] + driver = "i82801b11-bridge" + bus = "pcie.0" + addr = "1e.0" From b20aac072144e650dd5ba93bb4bfce1e061732e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 14 Oct 2020 19:30:46 +0200 Subject: [PATCH 021/262] soc/intel/skl,acpi/acpigen: convert global CPPC package to local one MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the global CPPC package \GCPC to the first logical core CP00 and adapt the reference in the other cores. This is cleaner and avoids confusion. Test: dumped SSDT on Supermicro X11SSM-F and verified decompiled version Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46465 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/acpi/acpigen.c | 9 ++++++--- src/soc/intel/skylake/acpi.c | 24 ++++++++++++++++-------- 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 7b7258469f..4a7dfc9325 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -10,6 +10,8 @@ #define ACPIGEN_MAXLEN 0xfffff +#define CPPC_PACKAGE_NAME "GCPC" + #include #include #include @@ -1578,8 +1580,6 @@ void acpigen_write_dsm_uuid_arr(struct dsm_uuid *ids, size_t count) acpigen_pop_len(); /* Method _DSM */ } -#define CPPC_PACKAGE_NAME "\\GCPC" - void acpigen_write_CPPC_package(const struct cppc_config *config) { u32 i; @@ -1621,9 +1621,12 @@ void acpigen_write_CPPC_package(const struct cppc_config *config) void acpigen_write_CPPC_method(void) { + char pscope[16]; + snprintf(pscope, sizeof(pscope), CONFIG_ACPI_CPU_STRING "." CPPC_PACKAGE_NAME, 0); + acpigen_write_method("_CPC", 0); acpigen_emit_byte(RETURN_OP); - acpigen_emit_namestring(CPPC_PACKAGE_NAME); + acpigen_emit_namestring(pscope); acpigen_pop_len(); } diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 637092be97..743b33f9ae 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -369,6 +369,19 @@ static void generate_p_state_entries(int core, int cores_per_package) acpigen_pop_len(); } +static void generate_cppc_entries(int core_id) +{ + /* Generate GCPC table in first logical core */ + if (core_id == 0) { + struct cppc_config cppc_config; + cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2); + acpigen_write_CPPC_package(&cppc_config); + } + + /* Write _CST entry for each logical core */ + acpigen_write_CPPC_method(); +} + void generate_cpu_entries(const struct device *device) { int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; @@ -377,16 +390,11 @@ void generate_cpu_entries(const struct device *device) int numcpus = totalcores/cores_per_package; config_t *config = config_of_soc(); int is_s0ix_enable = config->s0ix_enable; + const bool isst_supported = cpuid_eax(6) & CPUID_6_EAX_ISST; printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); - if (cpuid_eax(6) & CPUID_6_EAX_ISST) { - struct cppc_config cppc_config; - cpu_init_cppc_config(&cppc_config, 2 /* version 2 */); - acpigen_write_CPPC_package(&cppc_config); - } - for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { for (core_id = 0; core_id < cores_per_package; core_id++) { if (core_id > 0) { @@ -407,8 +415,8 @@ void generate_cpu_entries(const struct device *device) cores_per_package); } - if (cpuid_eax(6) & CPUID_6_EAX_ISST) - acpigen_write_CPPC_method(); + if (isst_supported) + generate_cppc_entries(core_id); acpigen_pop_len(); } From 5f5fd853ed3eac04990d50571f7c5daf2a028ed8 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 15 Oct 2020 12:24:00 +0200 Subject: [PATCH 022/262] acpi/acpi.h: Update region spaces Update operation region spaces according to ACPI Release 6.3 Errata A. Change-Id: I05305c96a2170eaf651d71ac79b67653745108a2 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46445 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/include/acpi/acpi.h | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index a9ec07754d..78740fb796 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -99,19 +99,24 @@ typedef struct acpi_gen_regaddr { u32 addrh; /* Register address, high 32 bits */ } __packed acpi_addr_t; -#define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */ -#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */ -#define ACPI_ADDRESS_SPACE_PCI 2 /* PCI config space */ -#define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */ -#define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */ -#define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */ -#define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */ -#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */ -#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */ -#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */ -#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */ -#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ -#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */ +#define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */ +#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */ +#define ACPI_ADDRESS_SPACE_PCI 2 /* PCI config space */ +#define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */ +#define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */ +#define ACPI_ADDRESS_SPACE_CMOS 5 /* SystemCMOS */ +#define ACPI_ADDRESS_SPACE_PCI_BAR_TARGET 6 /* PciBarTarget */ +#define ACPI_ADDRESS_SPACE_IPMI 7 /* IPMI */ +#define ACPI_ADDRESS_SPACE_GENERAL_PURPOSE_IO 8 /* GeneralPurposeIO */ +#define ACPI_ADDRESS_SPACE_GENERIC_SERIAL_BUS 9 /* GenericSerialBus */ +#define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */ +#define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */ +#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */ +#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */ +#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */ +#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */ +#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ +#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */ /* 0x80-0xbf: Reserved */ /* 0xc0-0xff: OEM defined */ From 50a44350ee5e0f3b34869a0b6804425efb2a906d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 30 Sep 2020 13:30:46 +0200 Subject: [PATCH 023/262] mb/getac/p470/acpi/ec.asl: Remove duplicated code "If(And(RFDV, 0x02)) {Or(Local0, 0x02, Local0)}" is duplicated. Change-Id: I91698fb308cd37c65aa65e563bcd88743097f56c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/45865 Reviewed-by: Stefan Reinauer Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/getac/p470/acpi/ec.asl | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 90ae64452e..5c0f4d85bd 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -469,9 +469,6 @@ Scope(\_SB) If(And(RFDV, 0x02)) { Or(Local0, 0x02, Local0) } - If(And(RFDV, 0x02)) { - Or(Local0, 0x02, Local0) - } If(And(RFDV, 0x04)) { Or(Local0, 0x04, Local0) } From e28133a9948df5f98007219d54d1afa478318d56 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 20 Sep 2020 11:57:14 +0200 Subject: [PATCH 024/262] mb/getac/p470/acpi: Convert to ASL 2.0 syntax Generated 'build/dsdt.dsl' are identical. Change-Id: Ifed93f4b0c360ec74f28926fb7cc9774ae03b8a6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/45555 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/getac/p470/acpi/ec.asl | 178 +++++------ src/mainboard/getac/p470/acpi/platform.asl | 42 +-- src/mainboard/getac/p470/acpi/superio.asl | 350 ++++++++++----------- src/mainboard/getac/p470/acpi/thermal.asl | 18 +- 4 files changed, 294 insertions(+), 294 deletions(-) diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 5c0f4d85bd..da6046ce4c 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -87,16 +87,16 @@ Device(EC0) Method (_Q01, 0) { Notify (\_SB.CP00, 0x80) - If(ADP) { - Store(1, \_SB.AC.ACST) - TRAP(0xe3) - Store(1, PWRS) - TRAP(0x2b) + If (ADP) { + \_SB.AC.ACST = 1 + TRAP (0xe3) + PWRS = 1 + TRAP (0x2b) } Else { - Store(0, \_SB.AC.ACST) - Notify(\_SB.AC, 0x80) - Notify(\_SB.BAT0, 0x80) - Store(0, PWRS) + \_SB.AC.ACST = 0 + Notify (\_SB.AC, 0x80) + Notify (\_SB.BAT0, 0x80) + PWRS = 0 TRAP(0x2b) } @@ -107,7 +107,7 @@ Device(EC0) Method (_Q02, 0) { - If(BAT) { + If (BAT) { Notify(\_SB.BAT0, 0x00) Notify(\_SB.AC, 0x80) } Else { @@ -132,7 +132,7 @@ Device(EC0) { TRAP(0xe0) - If (LEqual(RTCF, 0x00)) { + If (RTCF == 0x00) { Notify(LID0, 0x80) } else { TRAP(0xc1) @@ -172,25 +172,25 @@ Device(EC0) Method (_Q24, 0) { - Store(0x3f, HOTK) - If(IGDS) { + HOTK = 0x3f + If (IGDS) { Notify (\_SB.PCI0.GFX0, 0x82) } Else { - TRAP(0xE1) + TRAP (0xE1) } Notify (\_SB.ECO, 0x85) } Method (_Q25, 0) { - Store(0x40, HOTK) + HOTK = 0x40 TRAP(0xe1) Notify(\_SB.ECO, 0x86) } Method (_Q26, 0) { - Store(0x41, HOTK) + HOTK = 0x41 TRAP(0xe1) Notify(\_SB.ECO, 0x87) } @@ -212,7 +212,7 @@ Device(EC0) Method (_Q2A, 0) { - Store(0x57, HOTK) + HOTK = 0x57 TRAP(0xe1) Notify(\_SB.ECO, 0x8b) } @@ -225,7 +225,7 @@ Device(EC0) Method (_Q2C, 0) { - Store(0x59, HOTK) + HOTK = 0x59 TRAP(0xe1) } @@ -241,25 +241,25 @@ Device(EC0) Method (_Q3A, 0) { - Store(1, BRTL) + BRTL = 1 Notify(\_SB.ECO, 0x93) } Method (_Q3B, 0) { - Store(0, BRTL) + BRTL = 0 Notify(\_SB.ECO, 0x93) } Method (_Q3C, 0) { - Store(1, SUN) + SUN = 1 Notify(\_SB.ECO, 0x92) } Method (_Q3D, 0) { - Store(0, SUN) + SUN = 0 Notify(\_SB.ECO, 0x92) } @@ -302,14 +302,14 @@ Device(EC0) Method (_Q48, 0) { TRAP(0xd2) // Check AC Status - Store (1, ODDS) + ODDS = 1 Notify(\_SB.ECO, 0x90) } Method (_Q49, 0) { TRAP(0xd2) // Check AC Status - Store (0, ODDS) + ODDS = 0 Notify(\_SB.ECO, 0x90) } @@ -337,7 +337,7 @@ Device(EC0) Method (_Q5C, 0) { - // Store(2, IGPS) + // IGPS = 2 Notify(\_SB.ECO, 0x94) } @@ -364,26 +364,26 @@ Scope(\_SB) Method (GDPD, 0, Serialized) { // Set flag byte to zero - Store (0, Local0) + Local0 = 0 - If (And(BRTL, 0x01)) { - Or(Local0, 0x01, Local0) + If (BRTL & 0x01) { + Local0 |= 0x01 } - If (And(BRTL, 0x02)) { - Or(Local0, 0x04, Local0) + If (BRTL & 0x02) { + Local0 |= 0x04 } - If (And(BRTL, 0x04)) { - Or(Local0, 0x02, Local0) + If (BRTL & 0x04) { + Local0 |= 0x02 } - If (And(BRTL, 0x30)) { - Or(Local0, 0x10, Local0) + If (BRTL & 0x30) { + Local0 |= 0x10 } - If (And(BRTL, 0x40)) { - Or(Local0, 0x40, Local0) + If (BRTL & 0x40) { + Local0 |= 0x40 } Return (Local0) @@ -391,18 +391,18 @@ Scope(\_SB) Method (GDPC, 0, Serialized) { - Store (0, Local0) + Local0 = 0 - If (And(BRTL, 0x10)) { - Or(Local0, 0x04, Local0) + If (BRTL & 0x10) { + Local0 |= 0x04 } - If (And( BRTL, 0x20)) { - Or(Local0, 0x01, Local0) + If (BRTL & 0x20) { + Local0 |= 0x01 } - If (And(BRTL, 0x40)) { - Or(Local0, 0x02, Local0) + If (BRTL & 0x40) { + Local0 |= 0x02 } Return (Local0) @@ -411,7 +411,7 @@ Scope(\_SB) /* Set Brightness Level */ Method(SBLL, 1, Serialized) { - Store (Arg0, BRTL) + BRTL = Arg0 TRAP(0xd5) // See mainboard's smihandler.c Return (0) } @@ -426,7 +426,7 @@ Scope(\_SB) /* Get Brightness Level Medium? */ Method(GBLM, 0, Serialized) { - Store(0x3f, BRTL) + BRTL = 0x3f // XXX don't we have to set the brightness? Return(BRTL) } @@ -434,7 +434,7 @@ Scope(\_SB) /* ??? */ Method(SUTE, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xf5) } Else { TRAP(0xf6) @@ -462,30 +462,30 @@ Scope(\_SB) /* Let coreboot update the flags */ TRAP(0xe5) - Store (0, Local0) - If(And(RFDV, 0x01)) { - Or(Local0, 0x01, Local0) + Local0 = 0 + If (RFDV & 0x01) { + Local0 |= 0x01 } - If(And(RFDV, 0x02)) { - Or(Local0, 0x02, Local0) + If (RFDV & 0x02) { + Local0 |= 0x02 } - If(And(RFDV, 0x04)) { - Or(Local0, 0x04, Local0) + If (RFDV & 0x04) { + Local0 |= 0x04 } - If(And(RFDV, 0x08)) { - Or(Local0, 0x08, Local0) + If (RFDV & 0x08) { + Local0 |= 0x08 } - If(And(GP15, 0x01)) { // GDIS - Or(Local0, 0x10, Local0) + If (GP15 & 0x01) { // GDIS + Local0 |= 0x10 } - If(And(GP12, 0x01)) { // WIFI Led (WLED) - Or(Local0, 0x20, Local0) + If (GP12 & 0x01) { // WIFI Led (WLED) + Local0 |= 0x20 } - If(And(BTEN, 0x01)) { // BlueTooth Enable - Or(Local0, 0x40, Local0) + If (BTEN & 0x01) { // BlueTooth Enable + Local0 |= 0x40 } - If(And(GP10, 0x01)) { // GPS Enable - Or(Local0, 0x80, Local0) + If (GP10 & 0x01) { // GPS Enable + Local0 |= 0x80 } Return (Local0) @@ -494,30 +494,30 @@ Scope(\_SB) /* Set RFD */ Method(SRFD, 1, Serialized) { - If (And(Arg0, 0x01)) { - Store (1, GP14) // GLED - Store (1, GP15) // GDIS + If (Arg0 & 0x01) { + GP14 = 1 // GLED + GP15 = 1 // GDIS } Else { - Store (0, GP14) - Store (0, GP15) + GP14 = 0 + GP15 = 0 } /* WIFI */ - If (And(Arg0, 0x02)) { - Store (1, GP12) // WLED - Store (1, GP25) // WLAN + If (Arg0 & 0x02) { + GP12 = 1 // WLED + GP25 = 1 // WLAN } Else { - Store (0, GP12) - Store (0, GP25) + GP12 = 0 + GP25 = 0 } /* Bluetooth */ - If (And(Arg0, 0x04)) { - Store (1, GP13) // BLED - Store (1, BTEN) + If (Arg0 & 0x04) { + GP13 = 1 // BLED + BTEN = 1 } Else { - Store (0, GP13) // BLED - Store (0, BTEN) + GP13 = 0 // BLED + BTEN = 0 } Return (0) } @@ -539,7 +539,7 @@ Scope(\_SB) /* Set IGD (Graphics) */ Method(SIGD, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xf7) } Else { TRAP(0xf8) @@ -550,7 +550,7 @@ Scope(\_SB) /* SMI-C? Set Mic? */ Method (SMIC, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xeb) } Else { TRAP(0xec) @@ -567,7 +567,7 @@ Scope(\_SB) /* Not even decent function names anymore? */ Method(S024, 1, Serialized) { - If (And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xf1) } Else { TRAP(0xf2) @@ -585,13 +585,13 @@ Scope(\_SB) /* ??? Something with PATA */ Method(S025, 1, Serialized) { - If(And(Arg0, 0x01)) { + If (Arg0 & 0x01) { TRAP(0xfc) - Store (1, GP33) // CREN + GP33 = 1 // CREN Sleep(1500) - Store (1, GP34) // CRRS + GP34 = 1 // CRRS Sleep(500) Notify(^^PCI0.PATA, 0) @@ -599,7 +599,7 @@ Scope(\_SB) } Else { TRAP(0xfb) Sleep(1500) - Store(0, GP33) // CREN + GP33 = 0 // CREN Sleep(1500) Notify(^^PCI0.PATA, 0) Notify(^^PCI0.PATA.PRID, 0) @@ -613,16 +613,16 @@ Scope(\_SB) Method(G021, 0, Serialized) { TRAP(0xfe) - If (LEqual(ACIN, 0)) { + If (ACIN == 0) { TRAP(0xfa) TRAP(0xfd) - If (LEqual(ODDS, 1)) { + If (ODDS == 1) { TRAP(0xfb) Notify(^^PCI0.PATA, 0) Notify(^^PCI0.PATA.PRID.DSK1, 1) Notify(^^PCI0.PATA.PRID.DSK0, 1) Sleep (1500) - Store (0, GP33) // CREN + GP33 = 0 // CREN Sleep (1500) Notify(^^PCI0.PATA, 0) Notify(^^PCI0.PATA.PRID.DSK1, 1) @@ -645,7 +645,7 @@ Scope(\_SB) /* ??? */ Method(S00B, 1, Serialized) { - If (And(Arg0, 1)) { + If (Arg0 & 1) { TRAP(0xdc) } Else { TRAP(0xdd) diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl index 98cecbc587..b9835d1f87 100644 --- a/src/mainboard/getac/p470/acpi/platform.asl +++ b/src/mainboard/getac/p470/acpi/platform.asl @@ -9,23 +9,23 @@ Method(_PTS,1) TRAP(0xed) Sleep(1000) - Store(0, \_SB.ACFG) + \_SB.ACFG = 0 // Are we going to S4? - If (Lequal(Arg0, 4)) { + If (Arg0 == 4) { TRAP(0xe7) TRAP(0xea) } // Are we going to S5? - If (Lequal(Arg0, 5)) { + If (Arg0 == 5) { TRAP(0xde) } // The 2.6.12.5 ACPI engine seems to optimize the - // If(LEqual(Arg0, 5)) path away. This keeps it from doing so: + // If(Arg0 == 5) path away. This keeps it from doing so: TRAP(Arg0) - Store(Arg0, DBG0) + DBG0 = Arg0 // End of ugly OS bug workaround } @@ -34,12 +34,12 @@ Method(_PTS,1) Method(_WAK,1) { // Enable GPS - Store (1, GP11) // GPSE + GP11 = 1 // GPSE // Wake from S3 or S4? - If (LOr(LEqual(Arg0, 3), LEqual(Arg0, 4))) { - If (And(CFGD, 0x01000000)) { - If (LAnd(And(CFGD, 0xf0), LEqual(OSYS, 2001))) { + If ((Arg0 == 0x03) || (Arg0 == 0x04)) { + If (CFGD & 0x01000000) { + If ((CFGD & 0xF0) && (OSYS == 2001)) { TRAP(0x3d) } } @@ -48,26 +48,26 @@ Method(_WAK,1) // Notify PCI Express slots in case a card // was inserted while a sleep state was active. - If (LEqual(RP1D, 0)) { + If (RP1D == 0) { Notify(\_SB.PCI0.RP01, 0) } - If (LEqual(RP3D, 0)) { + If (RP3D == 0) { Notify(\_SB.PCI0.RP03, 0) } - If (LEqual(RP4D, 0)) { + If (RP4D == 0) { Notify(\_SB.PCI0.RP04, 0) } // Are we coming from S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { TRAP(0xeb) TRAP(0x46) } // Are we coming from S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { Notify(SLPB, 0x02) If (DTSE) { TRAP(0x47) @@ -75,16 +75,16 @@ Method(_WAK,1) } // Windows XP SP2 P-State restore - If (LAnd(LEqual(OSYS, 2002), And(CFGD, 1))) { - If (LGreater(\_SB.CP00._PPC, 0)) { - Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + If ((OSYS == 2002) && (CFGD & 0x01)) { + If (\_SB.CP00._PPC > 0) { + \_SB.CP00._PPC -= 1 PNOT() - Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + \_SB.CP00._PPC += 1 PNOT() } Else { - Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + \_SB.CP00._PPC += 1 PNOT() - Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC) + \_SB.CP00._PPC -= 1 PNOT() } } @@ -118,7 +118,7 @@ Scope(\_SB) * running: Windows XP SP1 needs to have C-State coordination * enabled in SMM. */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { + If ((OSYS == 2001) && MPEN) { TRAP(0x3d) } diff --git a/src/mainboard/getac/p470/acpi/superio.asl b/src/mainboard/getac/p470/acpi/superio.asl index 705b2b9c61..ab3839c6aa 100644 --- a/src/mainboard/getac/p470/acpi/superio.asl +++ b/src/mainboard/getac/p470/acpi/superio.asl @@ -19,13 +19,13 @@ Device (SIO1) Method (READ, 3) { Acquire (SIOM, 0xffff) - If (LEqual(Arg0, 0)) { - Store (0x55, INDX) - Store (Arg1, INDX) - Store (DATA, Local1) - Store (0xaa, INDX) + If (Arg0 == 0) { + INDX = 0x55 + INDX = Arg1 + Local1 = DATA + INDX = 0xaa } - And (Local1, Arg2, Local1) + Local1 &= Arg2 Release(SIOM) Return(Local1) } @@ -33,11 +33,11 @@ Device (SIO1) Method (WRIT, 3) { Acquire (SIOM, 0xffff) - If (LEqual(Arg0, 0)) { - Store (0x55, INDX) - Store (Arg1, INDX) - Store (Arg2, DATA) - Store (0xaa, INDX) + If (Arg0 == 0) { + INDX = 0x55 + INDX = Arg1 + DATA = Arg2 + INDX = 0xaa } Release(SIOM) } @@ -55,13 +55,13 @@ Device (SIO1) Acquire (SIOM, 0xffff) // Is the hardware enabled? - Store (READ(0, 0x24, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x24, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x08), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x08) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -74,12 +74,12 @@ Device (SIO1) { WRIT(0, 0x24, 0x00) - Store(READ(0, 0x28, 0x0f), Local0) + Local0 = READ (0, 0x28, 0x0f) WRIT(0, 0x28, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -104,8 +104,8 @@ Device (SIO1) IRQNoFlags(_IRA) { 4 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = (_STA () & 0x02) + If (Local0 == 0) { Return(NONE) } @@ -117,15 +117,15 @@ Device (SIO1) \_SB.PCI0.LPCB.SIO1.UAR1._CRS._IRA._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x24, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x24, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x28, 0xf0), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x28, 0xf0) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -138,29 +138,29 @@ Device (SIO1) WRIT(0, 0x24, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) - ShiftLeft(Local0, 4, Local0) + Local0-- + Local0 <<= 4 - Store(READ(0, 0x28, 0x0f), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0, 0x28, 0x0f) + Local0 |= Local1 WRIT(0, 0x28, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x24, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x08, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x08 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x40, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x40 + Local0 &= Local1 WRIT(0, 0x07, Local0) } @@ -168,22 +168,22 @@ Device (SIO1) /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x08, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x08 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x40, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x40 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } @@ -199,19 +199,19 @@ Device (SIO1) Method (_STA, 0) { /* IRDA? */ - Store(READ(0, 0x0c, 0x38), Local0) - If (LNotEqual(Local0, Zero)) { + Local0 = READ(0, 0x0c, 0x38) + If (Local0 != 0) { Return (0) } // Is the hardware enabled? - Store (READ(0, 0x25, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x25, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x80), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x80) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -224,12 +224,12 @@ Device (SIO1) { WRIT(0, 0x25, 0x00) - Store(READ(0, 0x28, 0xf0), Local0) + Local0 = READ (0, 0x28, 0xf0) WRIT(0, 0x28, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x80, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x80 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -254,8 +254,8 @@ Device (SIO1) IRQNoFlags(_IRB) { 3 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA () & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -267,15 +267,15 @@ Device (SIO1) \_SB.PCI0.LPCB.SIO1.UAR2._CRS._IRB._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x25, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x25, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x28, 0x0f), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x28, 0x0f) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -288,55 +288,55 @@ Device (SIO1) WRIT(0, 0x25, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) + Local0-- - Store(READ(0, 0x28, 0xf0), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0x00, 0x28, 0xf0) + Local0 |= Local1 WRIT(0, 0x28, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x25, Local0) - Store(READ(0, 0x0c, 0xff), Local0) - Not(0x38, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x0c, 0xff) + Local1 = ~0x38 + Local0 &= Local1 WRIT(0, 0x0c, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x80, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x80 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x20, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x20 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x80, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x80 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x20, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x20 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x80, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x80 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } @@ -354,13 +354,13 @@ Device (SIO1) Acquire (SIOM, 0xffff) // Is the hardware enabled? - Store (READ(0, 0x1b, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x1b, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x02), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x02) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -373,12 +373,12 @@ Device (SIO1) { WRIT(0, 0x1b, 0x00) - Store(READ(0, 0x1d, 0x0f), Local0) + Local0 = READ (0, 0x1d, 0x0f) WRIT(0, 0x1d, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x02, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x02 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -403,8 +403,8 @@ Device (SIO1) IRQNoFlags(_IRA) { 5 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA () & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -416,15 +416,15 @@ Device (SIO1) \_SB.PCI0.LPCB.SIO1.UAR3._CRS._IRA._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x1b, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0x00, 0x1b, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x1d, 0xf0), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x1d, 0xf0) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -437,29 +437,29 @@ Device (SIO1) WRIT(0, 0x1b, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) - ShiftLeft(Local0, 4, Local0) + Local0-- + Local0 <<= 4 - Store(READ(0, 0x1d, 0x0f), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0, 0x1d, 0x0f) + Local0 |= Local1 WRIT(0, 0x1d, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x1b, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x02, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x02 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x04, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x07, Local0) } @@ -467,22 +467,22 @@ Device (SIO1) /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x02, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x02 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x04, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x02, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x02 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } @@ -501,13 +501,13 @@ Device (SIO1) Acquire (SIOM, 0xffff) // Is the hardware enabled? - Store (READ(0, 0x1c, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x1c, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x04), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x04) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -520,12 +520,12 @@ Device (SIO1) { WRIT(0, 0x1c, 0x00) - Store(READ(0, 0x1d, 0x0f), Local0) + Local0 = READ (0, 0x1d, 0x0f) WRIT(0, 0x1d, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x04, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -550,8 +550,8 @@ Device (SIO1) IRQNoFlags(_IRA) { 11 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA () & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -563,15 +563,15 @@ Device (SIO1) \_SB.PCI0.LPCB.SIO1.UAR4._CRS._IRA._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x1c, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x1c, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x1d, 0xf0), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x1d, 0xf0) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -584,29 +584,29 @@ Device (SIO1) WRIT(0, 0x1c, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) - ShiftLeft(Local0, 4, Local0) + Local0-- + Local0 <<= 4 - Store(READ(0, 0x1d, 0x0f), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0x00, 0x1d, 0x0f) + Local0 |= Local1 WRIT(0, 0x1d, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x1c, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x04, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x04 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x08, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x07, Local0) } @@ -614,22 +614,22 @@ Device (SIO1) /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x04, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x04 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x04, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x04 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } diff --git a/src/mainboard/getac/p470/acpi/thermal.asl b/src/mainboard/getac/p470/acpi/thermal.asl index 6e3dc22cf9..4e31ef3a93 100644 --- a/src/mainboard/getac/p470/acpi/thermal.asl +++ b/src/mainboard/getac/p470/acpi/thermal.asl @@ -17,11 +17,11 @@ Scope (\_TZ) // Convert from °C to 1/10 Kelvin Method(DEGR, 1, NotSerialized) { - Store(Arg0, Local0) + Local0 = Arg0 // 10ths of degrees - Multiply(Local0, 10, Local0) + Local0 *= 10 // 0°C is 273.15 K, we need to round it. - Add(Local0, 2732, Local0) + Local0 += 2732 Return(Local0) } @@ -35,24 +35,24 @@ Scope (\_TZ) // Critical shutdown temperature Method (_CRT, 0, Serialized) { - Store(\_SB.PCI0.LPCB.EC0.CRTT, Local0) - Store(DEGR(Local0), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.CRTT + Local0 = DEGR (Local0) Return(Local0) } // CPU throttling start temperature Method (_PSV, 0, Serialized) { - Store(\_SB.PCI0.LPCB.EC0.CTRO, Local0) - Store(DEGR(Local0), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.CTRO + Local0 = DEGR (Local0) Return(Local0) } // Get DTS Temperature Method (_TMP, 0, Serialized) { - Store(\_SB.PCI0.LPCB.EC0.CTMP, Local0) - Store(DEGR(Local0), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.CTMP + Local0 = DEGR (Local0) Return(Local0) } From 2f1b51ac2b4b11866ae998cc09bfc6273edb2f14 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 8 Oct 2020 09:38:36 +0200 Subject: [PATCH 025/262] mb/intel/emeraldlake2: Convert to ASL 2.0 syntax Generated 'build/dsdt.dsl' files are identical. Change-Id: Idd2bf447975b4c9b2cd3b440505c0bd960374165 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46184 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- .../intel/emeraldlake2/acpi/platform.asl | 8 +- .../intel/emeraldlake2/acpi/thermal.asl | 74 +++++++++---------- 2 files changed, 41 insertions(+), 41 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/acpi/platform.asl b/src/mainboard/intel/emeraldlake2/acpi/platform.asl index 9568641fcf..9858fda223 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/platform.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/platform.asl @@ -8,16 +8,16 @@ Method(_PTS,1) { // NVS has a flag to determine USB policy in S3 if (S3U0) { - Store (One, GP47) // Enable USB0 + GP47 = 1 // Enable USB0 } Else { - Store (Zero, GP47) // Disable USB0 + GP47 = 0 // Disable USB0 } // NVS has a flag to determine USB policy in S3 if (S3U1) { - Store (One, GP56) // Enable USB1 + GP56 = 1 // Enable USB1 } Else { - Store (Zero, GP56) // Disable USB1 + GP56 = 0 // Disable USB1 } } diff --git a/src/mainboard/intel/emeraldlake2/acpi/thermal.asl b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl index 39d61b2a13..0a3bb49732 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/thermal.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl @@ -21,10 +21,10 @@ Scope (\_TZ) // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -50,28 +50,28 @@ Scope (\_TZ) Method (_TMP, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN3 // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If ((Local0 == 255) || (Local0 == 0)) { Return (CTOK (\F2ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { + If (Local1 >= \TMAX) { Return (CTOK (\TMAX)) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (\F0OF)) } Else { Return (CTOK (\F0ON)) @@ -79,7 +79,7 @@ Scope (\_TZ) } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (\F1OF)) } Else { Return (CTOK (\F1ON)) @@ -87,7 +87,7 @@ Scope (\_TZ) } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (\F2OF)) } Else { Return (CTOK (\F2ON)) @@ -95,7 +95,7 @@ Scope (\_TZ) } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (\F3OF)) } Else { Return (CTOK (\F3ON)) @@ -103,7 +103,7 @@ Scope (\_TZ) } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (\F4OF)) } Else { Return (CTOK (\F4ON)) @@ -119,20 +119,20 @@ Scope (\_TZ) PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) - Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F0PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } } @@ -140,20 +140,20 @@ Scope (\_TZ) PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } } @@ -161,20 +161,20 @@ Scope (\_TZ) PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } } @@ -182,20 +182,20 @@ Scope (\_TZ) PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } @@ -203,20 +203,20 @@ Scope (\_TZ) PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } From 9e90807b40529e1e8b236fe73505c3c43f5ca5b5 Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Wed, 28 Oct 2020 11:39:13 +0800 Subject: [PATCH 026/262] amdfwtool: Add an option to show debug message Change-Id: I3e3bcc2c9e1b3edfed1ce845c1603b2a9a2bb044 Signed-off-by: Zheng Bao Reviewed-on: https://review.coreboot.org/c/coreboot/+/46867 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- util/amdfwtool/amdfwtool.c | 39 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 561b511e3d..0c4153e10d 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -216,6 +216,7 @@ static void usage(void) printf(" 0x2 Micron parts optional, this option is only\n"); printf(" supported with RN/LCN SOC\n"); printf("-c | --config Config file\n"); + printf("-d | --debug Print debug message\n"); printf("-D | --depend List out the firmware files\n"); } @@ -596,6 +597,29 @@ static void integrate_firmwares(context *ctx, } } +/* For debugging */ +static void dump_psp_firmwares(amd_fw_entry *fw_table) +{ + amd_fw_entry *index; + + printf("PSP firmware components:"); + for (index = fw_table; index->type != AMD_FW_INVALID; index++) { + if (index->filename) + printf(" filename=%s\n", index->filename); + } +} + +static void dump_bdt_firmwares(amd_bios_entry *fw_table) +{ + amd_bios_entry *index; + + printf("BIOS Directory Table (BDT) components:"); + for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { + if (index->filename) + printf(" filename=%s\n", index->filename); + } +} + static void free_psp_firmware_filenames(amd_fw_entry *fw_table) { amd_fw_entry *index; @@ -1007,9 +1031,9 @@ enum { LONGOPT_SPI_MICRON_FLAG = 258, }; -/* Unused values: BGJKNXYbdkmprstuwyz*/ +/* Unused values: BGJKNXYbkmprstuwyz*/ static const char *optstring = "x:i:g:AMn:T:SPLUW:I:a:Q:V:e:v:j:O:F:" - "H:o:f:l:hZ:qR:C:c:E:D"; + "H:o:f:l:hZ:qR:C:c:E:dD"; static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1052,6 +1076,7 @@ static struct option long_options[] = { {"soc-name", required_argument, 0, 'C' }, {"config", required_argument, 0, 'c' }, + {"debug", no_argument, 0, 'd' }, {"help", no_argument, 0, 'h' }, {"depend", no_argument, 0, 'D' }, {NULL, 0, 0, 0 } @@ -1250,6 +1275,7 @@ int main(int argc, char **argv) int multi = 0; amd_cb_config cb_config; + int debug = 0; int list_deps = 0; cb_config.have_whitelist = 0; @@ -1425,6 +1451,9 @@ int main(int argc, char **argv) case 'c': config = optarg; break; + case 'd': + debug = 1; + break; case 'h': usage(); return 0; @@ -1450,6 +1479,12 @@ int main(int argc, char **argv) } fclose(config_handle); } + /* For debug. */ + if (debug) { + dump_psp_firmwares(amd_psp_fw_table); + dump_bdt_firmwares(amd_bios_table); + } + if (!fuse_defined) register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); From 77a2c67dfe94e1dac09c5878d9963d30fae2a90f Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Thu, 1 Oct 2020 17:05:43 +0800 Subject: [PATCH 027/262] amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- util/amdfwtool/amdfwtool.c | 54 ++++++++++++++++++------------------- util/amdfwtool/data_parse.c | 4 +-- 2 files changed, 29 insertions(+), 29 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 0c4153e10d..9cf6a4f8c0 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -529,19 +529,19 @@ static ssize_t copy_blob(void *dest, const char *src_file, size_t room) fd = open(src_file, O_RDONLY); if (fd < 0) { - printf("Error opening file: %s: %s\n", + fprintf(stderr, "Error opening file: %s: %s\n", src_file, strerror(errno)); return -1; } if (fstat(fd, &fd_stat)) { - printf("fstat error: %s\n", strerror(errno)); + fprintf(stderr, "fstat error: %s\n", strerror(errno)); close(fd); return -2; } if ((size_t)fd_stat.st_size > room) { - printf("Error: %s will not fit. Exiting.\n", src_file); + fprintf(stderr, "Error: %s will not fit. Exiting.\n", src_file); close(fd); return -3; } @@ -549,7 +549,7 @@ static ssize_t copy_blob(void *dest, const char *src_file, size_t room) bytes = read(fd, dest, (size_t)fd_stat.st_size); close(fd); if (bytes != (ssize_t)fd_stat.st_size) { - printf("Error while reading %s\n", src_file); + fprintf(stderr, "Error while reading %s\n", src_file); return -4; } @@ -755,7 +755,7 @@ static void integrate_psp_firmwares(context *ctx, } if (count > MAX_PSP_ENTRIES) { - printf("Error: PSP entries exceed max allowed items\n"); + fprintf(stderr, "Error: PSP entries exceed max allowed items\n"); free(ctx->rom); exit(1); } @@ -871,7 +871,7 @@ static void integrate_bios_firmwares(context *ctx, if (!fw_table[i].size && !fw_table[i].src) continue; /* APOB_NV not used */ if (fw_table[i].src && !fw_table[i].size) { - printf("Error: APOB NV address provided, but no size\n"); + fprintf(stderr, "Error: APOB NV address provided, but no size\n"); free(ctx->rom); exit(1); } @@ -883,7 +883,7 @@ static void integrate_bios_firmwares(context *ctx, /* APOB_DATA needs destination */ if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) { - printf("Error: APOB destination not provided\n"); + fprintf(stderr, "Error: APOB destination not provided\n"); free(ctx->rom); exit(1); } @@ -893,12 +893,12 @@ static void integrate_bios_firmwares(context *ctx, */ if (fw_table[i].type == AMD_BIOS_BIN) { if (!fw_table[i].dest || !fw_table[i].size) { - printf("Error: BIOS binary destination and uncompressed size are required\n"); + fprintf(stderr, "Error: BIOS binary destination and uncompressed size are required\n"); free(ctx->rom); exit(1); } if (!fw_table[i].filename && !fw_table[i].src) { - printf("Error: BIOS binary assumed outside amdfw.rom but no source address given\n"); + fprintf(stderr, "Error: BIOS binary assumed outside amdfw.rom but no source address given\n"); free(ctx->rom); exit(1); } @@ -1015,7 +1015,7 @@ static void integrate_bios_firmwares(context *ctx, } if (count > MAX_BIOS_ENTRIES) { - printf("Error: BIOS entries (%d) exceeds max allowed items " + fprintf(stderr, "Error: BIOS entries (%d) exceeds max allowed items " "(%d)\n", count, MAX_BIOS_ENTRIES); free(ctx->rom); exit(1); @@ -1177,7 +1177,7 @@ static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig, uint8_t efs_spi_micron_flag) { if ((efs_spi_readmode == 0xFF) || (efs_spi_speed == 0xFF)) { - printf("Error: EFS read mode and SPI speed must be set\n"); + fprintf(stderr, "Error: EFS read mode and SPI speed must be set\n"); return 1; } switch (soc_id) { @@ -1199,7 +1199,7 @@ static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig, amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xa; break; default: - printf("Error: EFS Micron flag must be correctly set.\n\n"); + fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n"); return 1; } break; @@ -1219,13 +1219,13 @@ static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig, amd_romsig->micron_detect_f17_mod_30_3f = 0x55; break; default: - printf("Error: EFS Micron flag must be correctly set.\n\n"); + fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n"); return 1; } break; case PLATFORM_UNKNOWN: default: - printf("Error: Invalid SOC name.\n\n"); + fprintf(stderr, "Error: Invalid SOC name.\n\n"); return 1; } return 0; @@ -1398,7 +1398,7 @@ int main(int argc, char **argv) case 'C': soc_id = identify_platform(optarg); if (soc_id == PLATFORM_UNKNOWN) { - printf("Error: Invalid SOC name specified\n\n"); + fprintf(stderr, "Error: Invalid SOC name specified\n\n"); retval = 1; } sub = instance = 0; @@ -1421,7 +1421,7 @@ int main(int argc, char **argv) case 'f': ctx.rom_size = (uint32_t)strtoul(optarg, &tmp, 16); if (*tmp != '\0') { - printf("Error: ROM size specified" + fprintf(stderr, "Error: ROM size specified" " incorrectly (%s)\n\n", optarg); retval = 1; } @@ -1429,7 +1429,7 @@ int main(int argc, char **argv) case 'l': dir_location = (uint32_t)strtoul(optarg, &tmp, 16); if (*tmp != '\0') { - printf("Error: Directory Location specified" + fprintf(stderr, "Error: Directory Location specified" " incorrectly (%s)\n\n", optarg); retval = 1; } @@ -1518,14 +1518,14 @@ int main(int argc, char **argv) rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1; if (dir_location && (dir_location < rom_base_address)) { - printf("Error: Directory location outside of ROM.\n\n"); + fprintf(stderr, "Error: Directory location outside of ROM.\n\n"); return 1; } if (any_location) { if (dir_location & 0x3f) { - printf("Error: Invalid Directory location.\n"); - printf(" Valid locations are 64-byte aligned\n"); + fprintf(stderr, "Error: Invalid Directory location.\n"); + fprintf(stderr, " Valid locations are 64-byte aligned\n"); return 1; } } else { @@ -1539,16 +1539,16 @@ int main(int argc, char **argv) case 0xFF020000: /* Fall through */ break; default: - printf("Error: Invalid Directory location.\n"); - printf(" Valid locations are 0xFFFA0000, 0xFFF20000,\n"); - printf(" 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); + fprintf(stderr, "Error: Invalid Directory location.\n"); + fprintf(stderr, " Valid locations are 0xFFFA0000, 0xFFF20000,\n"); + fprintf(stderr, " 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); return 1; } } ctx.rom = malloc(ctx.rom_size); if (!ctx.rom) { - printf("Error: Failed to allocate memory\n"); + fprintf(stderr, "Error: Failed to allocate memory\n"); return 1; } memset(ctx.rom, 0xFF, ctx.rom_size); @@ -1570,11 +1570,11 @@ int main(int argc, char **argv) retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, efs_spi_speed, efs_spi_micron_flag); if (retval) { - printf("ERROR: Failed to initialize EFS table!\n"); + fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); return retval; } } else { - printf("WARNING: No SOC name specified.\n"); + fprintf(stderr, "WARNING: No SOC name specified.\n"); } integrate_firmwares(&ctx, amd_romsig, amd_fw_table); @@ -1650,7 +1650,7 @@ int main(int argc, char **argv) } close(targetfd); } else { - printf("Error: could not open file: %s\n", output); + fprintf(stderr, "Error: could not open file: %s\n", output); retval = 1; } diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index bb616d3405..2af6c31991 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -38,7 +38,7 @@ void compile_reg_expr(int cflags, const char *expr, regex_t *reg) result = regcomp(reg, expr, cflags); if (result != 0) { regerror(result, reg, error_msg, ERROR_BUF_SIZE); - printf("%s\n", error_msg); + fprintf(stderr, "%s\n", error_msg); } } @@ -304,7 +304,7 @@ int get_input_file_line(FILE *f, char line[], int line_buf_size) line[strlen(line) - 1] = '\0'; if (strlen(line) == ((size_t) (line_buf_size - 1))) { - printf("The line size in config file should be lower than %d bytes.\n", + fprintf(stderr, "The line size in config file should be lower than %d bytes.\n", MAX_LINE_SIZE); exit(1); } From 3384e4a709b97071a67b724bc9f4a4208f0f5fe8 Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Tue, 6 Oct 2020 12:03:11 +0800 Subject: [PATCH 028/262] soc/amd: Change FIRMWARE_LOCATE to FIRMWARE_LOCATION Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2 Signed-off-by: Zheng Bao Reviewed-on: https://review.coreboot.org/c/coreboot/+/46062 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/google/zork/spd/Makefile.inc | 2 +- src/soc/amd/picasso/Makefile.inc | 8 ++++---- src/soc/amd/picasso/fw.cfg | 2 +- src/soc/amd/stoneyridge/Makefile.inc | 16 ++++++++-------- src/soc/amd/stoneyridge/fw_cz.cfg | 2 +- src/soc/amd/stoneyridge/fw_st.cfg | 2 +- src/southbridge/amd/pi/hudson/Makefile.inc | 22 +++++++++++----------- src/southbridge/amd/pi/hudson/fw_avl.cfg | 2 +- util/amdfwtool/data_parse.c | 6 +++--- 9 files changed, 31 insertions(+), 31 deletions(-) diff --git a/src/mainboard/google/zork/spd/Makefile.inc b/src/mainboard/google/zork/spd/Makefile.inc index 1042d9101d..d6ae475b12 100644 --- a/src/mainboard/google/zork/spd/Makefile.inc +++ b/src/mainboard/google/zork/spd/Makefile.inc @@ -6,7 +6,7 @@ SPD_SOURCES_DIR := src/mainboard/$(MAINBOARDDIR)/spd APCB_SOURCES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/APCB_$(f).gen) # APCB binary with magic numbers to be replaced by apcb_edit tool -APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin +APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATION)/APCB_magic.bin $(obj)/APCB_%.gen: $(SPD_SOURCES_DIR)/%.hex \ $(APCB_EDIT_TOOL) \ diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index f0c6ae52f2..5a88d0b684 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -130,7 +130,7 @@ PICASSO_FWM_POSITION=$(call int-add, \ # Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). # -FIRMWARE_LOCATE=$(shell grep -e FIRMWARE_LOCATE $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) # Enable secure debug unlock @@ -180,9 +180,9 @@ APOB_NV_SIZE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_SIZE" $(obj)/fmap_config.h APOB_NV_BASE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_START" $(obj)/fmap_config.h | awk '{print $$(NF)}') # type = 0x66 -PSP_UCODE_FILE1=$(FIRMWARE_LOCATE)/UcodePatch_PCO_B1.bin -PSP_UCODE_FILE2=$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin -PSP_UCODE_FILE3=$(FIRMWARE_LOCATE)/UcodePatch_RV2_A0.bin +PSP_UCODE_FILE1=$(FIRMWARE_LOCATION)/UcodePatch_PCO_B1.bin +PSP_UCODE_FILE2=$(FIRMWARE_LOCATION)/UcodePatch_PCO_B0.bin +PSP_UCODE_FILE3=$(FIRMWARE_LOCATION)/UcodePatch_RV2_A0.bin ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) # type = 0x6B - PSP Shared memory location diff --git a/src/soc/amd/picasso/fw.cfg b/src/soc/amd/picasso/fw.cfg index e746d1e299..516af7bf3a 100644 --- a/src/soc/amd/picasso/fw.cfg +++ b/src/soc/amd/picasso/fw.cfg @@ -1,6 +1,6 @@ # PSP fw config file -FIRMWARE_LOCATE 3rdparty/amd_blobs/picasso/PSP +FIRMWARE_LOCATION 3rdparty/amd_blobs/picasso/PSP # type file AMD_PUBKEY_FILE AmdPubKeyRV.bin diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 9211e81476..c608286382 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -102,9 +102,9 @@ STONEYRIDGE_FWM_POSITION=$(call int-add, \ ### 0 -FIRMWARE_LOCATE=$(shell grep -e FIRMWARE_LOCATE $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') -ifneq ($(FIRMWARE_LOCATE),) +ifneq ($(FIRMWARE_LOCATION),) ifeq ($(CONFIG_AMD_APU_STONEYRIDGE),y) FIRMWARE_TYPE=ST @@ -126,11 +126,11 @@ add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) OPT_STONEYRIDGE_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE), --gec) -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/$(shell awk '($$1=="PSP_SMUFW1_SUB0_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/$(shell awk '($$1=="PSP_SMUFW1_SUB1_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) +SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATION)/$(shell awk '($$1=="PSP_SMUFW1_SUB0_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) +SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATION)/$(shell awk '($$1=="PSP_SMUFW1_SUB1_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/$(shell awk '($$1=="PSP_SMUFW2_SUB0_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) -SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/$(shell awk '($$1=="PSP_SMUFW2_SUB1_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) +SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATION)/$(shell awk '($$1=="PSP_SMUFW2_SUB0_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) +SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATION)/$(shell awk '($$1=="PSP_SMUFW2_SUB1_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) ifeq ("$(wildcard $(SMUFWM_FN_FILE))","") SMUFWM_FN_FILE= @@ -211,7 +211,7 @@ endif endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) -else # ifneq ($(FIRMWARE_LOCATE),) +else # ifneq ($(FIRMWARE_LOCATION),) warn_no_amdfw: printf "\n\t** WARNING **\n" @@ -222,6 +222,6 @@ PHONY+=warn_no_amdfw files_added:: warn_no_amdfw -endif # ifneq ($(FIRMWARE_LOCATE),) +endif # ifneq ($(FIRMWARE_LOCATION),) endif # ($(CONFIG_SOC_AMD_STONEYRIDGE),y) diff --git a/src/soc/amd/stoneyridge/fw_cz.cfg b/src/soc/amd/stoneyridge/fw_cz.cfg index acbf13616b..a6a22f7191 100644 --- a/src/soc/amd/stoneyridge/fw_cz.cfg +++ b/src/soc/amd/stoneyridge/fw_cz.cfg @@ -1,6 +1,6 @@ # PSP fw config file -FIRMWARE_LOCATE 3rdparty/amd_blobs/stoneyridge/PSP/CZ +FIRMWARE_LOCATION 3rdparty/amd_blobs/stoneyridge/PSP/CZ #PSP AMD_PUBKEY_FILE AmdPubKeyCZ.bin PSPBTLDR_FILE PspBootLoader_prod_CZ.sbin diff --git a/src/soc/amd/stoneyridge/fw_st.cfg b/src/soc/amd/stoneyridge/fw_st.cfg index aa026683c0..01db8b9748 100644 --- a/src/soc/amd/stoneyridge/fw_st.cfg +++ b/src/soc/amd/stoneyridge/fw_st.cfg @@ -1,6 +1,6 @@ # PSP fw config file -FIRMWARE_LOCATE 3rdparty/amd_blobs/stoneyridge/PSP/ST +FIRMWARE_LOCATION 3rdparty/amd_blobs/stoneyridge/PSP/ST #XHCI_FWM_FILE xhci.bin #PSP diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index c845f846c7..d5528aacef 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -78,26 +78,26 @@ endif ifeq ($(CONFIG_HUDSON_PSP), y) ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -FIRMWARE_LOCATE=$(shell grep -e FIRMWARE_LOCATE $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') FIRMWARE_TYPE= endif ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) +FIRMWARE_LOCATION=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE=CZ -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_CZ.sbin -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_CZ.sbin -PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_CZ.csbin -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_CZ.cbin -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_CZ.sbin -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_CZ.sbin +PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATION)/PspBootLoader_prod_CZ.sbin +PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATION)/PspRecoveryBootLoader_prod_CZ.sbin +PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATION)/PspSecureOs_prod_CZ.csbin +PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATION)/PspTrustlets_prod_CZ.cbin +TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATION)/TrustletKey_prod_CZ.sbin +SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware2_prod_CZ.sbin endif -#PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key -#PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin -#PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key +#PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATION)/RtmPubSigned$(FIRMWARE_TYPE).key +#PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATION)/PspNvram$(FIRMWARE_TYPE).bin +#PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATION)/PspSecureDebug$(FIRMWARE_TYPE).Key endif diff --git a/src/southbridge/amd/pi/hudson/fw_avl.cfg b/src/southbridge/amd/pi/hudson/fw_avl.cfg index f65d6b822f..71593aead7 100644 --- a/src/southbridge/amd/pi/hudson/fw_avl.cfg +++ b/src/southbridge/amd/pi/hudson/fw_avl.cfg @@ -1,6 +1,6 @@ # PSP fw config file -FIRMWARE_LOCATE 3rdparty/blobs/southbridge/amd/avalon/PSP +FIRMWARE_LOCATION 3rdparty/blobs/southbridge/amd/avalon/PSP #PSP AMD_PUBKEY_FILE AmdPubKey.bin PSPBTLDR_FILE PspBootLoader.Bypass.sbin diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 2af6c31991..b3470d54cc 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -359,13 +359,13 @@ uint8_t process_config(FILE *config, amd_cb_config *cb_config, uint8_t print_dep entries_line_regex, &entries_line_expr); /* Get a line */ - /* Get FIRMWARE_LOCATE in the first loop */ + /* Get FIRMWARE_LOCATION in the first loop */ while (get_input_file_line(config, oneline, MAX_LINE_SIZE) == OK) { /* get a line */ if (skip_comment_blank_line(oneline)) continue; if (is_valid_entry(oneline, match)) { - if (strcmp(&(oneline[match[1].rm_so]), "FIRMWARE_LOCATE") == 0) { + if (strcmp(&(oneline[match[1].rm_so]), "FIRMWARE_LOCATION") == 0) { strcpy(dir, &(oneline[match[2].rm_so])); break; } @@ -384,7 +384,7 @@ uint8_t process_config(FILE *config, amd_cb_config *cb_config, uint8_t print_dep if (skip_comment_blank_line(oneline)) continue; if (is_valid_entry(oneline, match)) { - if (strcmp(&(oneline[match[1].rm_so]), "FIRMWARE_LOCATE") == 0) { + if (strcmp(&(oneline[match[1].rm_so]), "FIRMWARE_LOCATION") == 0) { continue; } else { path_filename = malloc(MAX_LINE_SIZE); From c98ba034932bc2c3874a60d4ae36d799777e53be Mon Sep 17 00:00:00 2001 From: David Wu Date: Mon, 2 Nov 2020 14:20:40 +0800 Subject: [PATCH 029/262] mb/google/volteer/var/voema: Update dq/dqs mappings Update dq/dqs mappings based on voema schematics. BUG=b:169356808 BRANCH=volteer TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu Change-Id: I1aae4286278e712bf29ebb15738477828d3f74d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47093 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../volteer/variants/voema/Makefile.inc | 3 + .../google/volteer/variants/voema/memory.c | 65 +++++++++++++++++++ 2 files changed, 68 insertions(+) create mode 100644 src/mainboard/google/volteer/variants/voema/Makefile.inc create mode 100644 src/mainboard/google/volteer/variants/voema/memory.c diff --git a/src/mainboard/google/volteer/variants/voema/Makefile.inc b/src/mainboard/google/volteer/variants/voema/Makefile.inc new file mode 100644 index 0000000000..9064208bff --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c diff --git a/src/mainboard/google/volteer/variants/voema/memory.c b/src/mainboard/google/volteer/variants/voema/memory.c new file mode 100644 index 0000000000..b611af5161 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct lpddr4x_cfg voema_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ + [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &voema_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} From 29ef574b3f7bd5431373efa4f86bdd65d6b347c5 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 8 Oct 2020 09:37:31 +0200 Subject: [PATCH 030/262] mb/intel/baskingridge: Convert to ASL 2.0 syntax Generated 'dsdt.dsl' files are identical. Change-Id: I5897397bdadf86214ceaf90d8cd706e10969d8c1 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46182 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- .../intel/baskingridge/acpi/thermal.asl | 64 +++++++++---------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/src/mainboard/intel/baskingridge/acpi/thermal.asl b/src/mainboard/intel/baskingridge/acpi/thermal.asl index 487b7417f5..c1bb1163ed 100644 --- a/src/mainboard/intel/baskingridge/acpi/thermal.asl +++ b/src/mainboard/intel/baskingridge/acpi/thermal.asl @@ -20,10 +20,10 @@ Scope (\_TZ) // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -52,7 +52,7 @@ Scope (\_TZ) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (\F0OF)) } Else { Return (CTOK (\F0ON)) @@ -60,7 +60,7 @@ Scope (\_TZ) } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (\F1OF)) } Else { Return (CTOK (\F1ON)) @@ -68,7 +68,7 @@ Scope (\_TZ) } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (\F2OF)) } Else { Return (CTOK (\F2ON)) @@ -76,7 +76,7 @@ Scope (\_TZ) } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (\F3OF)) } Else { Return (CTOK (\F3ON)) @@ -84,7 +84,7 @@ Scope (\_TZ) } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (\F4OF)) } Else { Return (CTOK (\F4ON)) @@ -100,20 +100,20 @@ Scope (\_TZ) PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) - Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F0PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } } @@ -121,20 +121,20 @@ Scope (\_TZ) PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } } @@ -142,20 +142,20 @@ Scope (\_TZ) PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } } @@ -163,20 +163,20 @@ Scope (\_TZ) PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } @@ -184,20 +184,20 @@ Scope (\_TZ) PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } From 3ed5c9e3cdf7eb38c92c4c75c2eee6fb22d61eea Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 8 Oct 2020 09:30:35 +0200 Subject: [PATCH 031/262] mb/google/beltino: Convert to ASL 2.0 syntax Built google/beltino (Monroe) provides identical 'dsdt.dsl'. Change-Id: I12b6a8264e53ece30ae79da2d79c6f1d302fb357 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46170 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- .../google/beltino/acpi/mainboard.asl | 8 +- src/mainboard/google/beltino/acpi/thermal.asl | 116 ++++++++---------- 2 files changed, 57 insertions(+), 67 deletions(-) diff --git a/src/mainboard/google/beltino/acpi/mainboard.asl b/src/mainboard/google/beltino/acpi/mainboard.asl index 3049dbee96..10696ff9fc 100644 --- a/src/mainboard/google/beltino/acpi/mainboard.asl +++ b/src/mainboard/google/beltino/acpi/mainboard.asl @@ -14,9 +14,9 @@ Scope (\_SB.PCI0.RP01) Method (_DSW, 3, NotSerialized) { - Store (NIC_WAKE_GPIO, Local0) + Local0 = NIC_WAKE_GPIO - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GWAK (Local0) } @@ -36,9 +36,9 @@ Scope (\_SB.PCI0.RP02) Method (_DSW, 3, NotSerialized) { - Store (WLAN_WAKE_GPIO, Local0) + Local0 = WLAN_WAKE_GPIO - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GWAK (Local0) } diff --git a/src/mainboard/google/beltino/acpi/thermal.asl b/src/mainboard/google/beltino/acpi/thermal.asl index 1292af4a20..96acaeb975 100644 --- a/src/mainboard/google/beltino/acpi/thermal.asl +++ b/src/mainboard/google/beltino/acpi/thermal.asl @@ -23,10 +23,10 @@ Scope (\_TZ) // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -52,66 +52,66 @@ Scope (\_TZ) // Start fan at state 4 = lowest temp state Method (_INI) { - Store (4, \FLVL) - Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } Method (TCHK, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN3 // Check for "no reading available" - If (LEqual (Local0, 0x80)) { + If (Local0 == 0x80) { Return (CTOK (FAN0_THRESHOLD_ON)) } // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If ((Local0 == 255) || (Local0 == 0)) { Return (CTOK (FAN0_THRESHOLD_ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { + If (Local1 >= \TMAX) { Return (CTOK (\TMAX)) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } Method (_TMP, 0, Serialized) { // Get temperature from SuperIO in deci-kelvin - Store (TCHK (), Local0) + Local0 = TCHK () // Critical temperature in deci-kelvin - Store (CTOK (\TMAX), Local1) + Local1 = CTOK (\TMAX) - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 // Wait 1 second for SuperIO to re-poll Sleep (1000) // Re-read temperature from SuperIO - Store (TCHK (), Local0) + Local0 = TCHK () - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Debug = "RE-READ TEMPERATURE" + Debug = Local0 } Return (Local0) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (FAN0_THRESHOLD_OFF)) } Else { Return (CTOK (FAN0_THRESHOLD_ON)) @@ -119,7 +119,7 @@ Scope (\_TZ) } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (FAN1_THRESHOLD_OFF)) } Else { Return (CTOK (FAN1_THRESHOLD_ON)) @@ -127,7 +127,7 @@ Scope (\_TZ) } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (FAN2_THRESHOLD_OFF)) } Else { Return (CTOK (FAN2_THRESHOLD_ON)) @@ -135,7 +135,7 @@ Scope (\_TZ) } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (FAN3_THRESHOLD_OFF)) } Else { Return (CTOK (FAN3_THRESHOLD_ON)) @@ -143,7 +143,7 @@ Scope (\_TZ) } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (FAN4_THRESHOLD_OFF)) } Else { Return (CTOK (FAN4_THRESHOLD_ON)) @@ -159,25 +159,23 @@ Scope (\_TZ) PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (0, \FLVL) - Store (FAN0_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN0_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM Notify (\_TZ.THRM, 0x81) } } @@ -186,25 +184,23 @@ Scope (\_TZ) PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM Notify (\_TZ.THRM, 0x81) } } @@ -213,25 +209,23 @@ Scope (\_TZ) PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM Notify (\_TZ.THRM, 0x81) } } @@ -240,25 +234,23 @@ Scope (\_TZ) PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } @@ -267,25 +259,23 @@ Scope (\_TZ) PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } From 527690c7bf6f96b52496d26223e8ac885dedf907 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 8 Oct 2020 09:33:16 +0200 Subject: [PATCH 032/262] mb/google/link: Convert to ASL 2.0 syntax Generated 'dsdt.dsl' files are identical. Change-Id: I7d4fc3acd82023b007d80638bcb71476330ef320 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46176 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/link/acpi/platform.asl | 14 +++--- src/mainboard/google/link/acpi/thermal.asl | 50 ++++++++++----------- 2 files changed, 32 insertions(+), 32 deletions(-) diff --git a/src/mainboard/google/link/acpi/platform.asl b/src/mainboard/google/link/acpi/platform.asl index 35893ee1a7..12b14530f2 100644 --- a/src/mainboard/google/link/acpi/platform.asl +++ b/src/mainboard/google/link/acpi/platform.asl @@ -7,7 +7,7 @@ Method(_PTS,1) { /* Disable WWAN */ - Store (Zero, GP36) + GP36 = 0 } /* The _WAK method is called on system wakeup */ @@ -15,16 +15,16 @@ Method(_PTS,1) Method(_WAK,1) { /* Update AC status */ - Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0) - if (LNotEqual (Local0, \PWRS)) { - Store (Local0, \PWRS) + Local0 = \_SB.PCI0.LPCB.EC0.ACEX + if (Local0 != \PWRS) { + \PWRS = Local0 Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) } /* Update LID status */ - Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0) - if (LNotEqual (Local0, \LIDS)) { - Store (Local0, \LIDS) + Local0 = \_SB.PCI0.LPCB.EC0.LIDS + if (Local0 != \LIDS) { + \LIDS = Local0 Notify (\_SB.PCI0.LPCB.EC0.LID0, 0x80) } diff --git a/src/mainboard/google/link/acpi/thermal.asl b/src/mainboard/google/link/acpi/thermal.asl index 28fa4907cc..7ea38ae6cd 100644 --- a/src/mainboard/google/link/acpi/thermal.asl +++ b/src/mainboard/google/link/acpi/thermal.asl @@ -15,10 +15,10 @@ Scope (\_TZ) // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -32,33 +32,33 @@ Scope (\_TZ) Method (_TMP, 0, Serialized) { // Get CPU Temperature from TIN9/PECI via EC - Store (\_SB.PCI0.LPCB.EC0.TIN9, Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TIN9 // Check for sensor not calibrated - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNCA) { Return (CTOK(0)) } // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNPR) { Return (CTOK(0)) } // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNOP) { Return (CTOK(0)) } // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TBAD) { Return (CTOK(0)) } // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + Local0 += \_SB.PCI0.LPCB.EC0.TOFS // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) + Local0 *= 10 Return (Local0) } } @@ -77,10 +77,10 @@ Scope (\_TZ) // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -106,34 +106,34 @@ Scope (\_TZ) Method (_TMP, 0, Serialized) { // Get Temperature from TIN# set in NVS - Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TINS (TMPS) // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNPR) { Return (CTOK(0)) } // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNOP) { Return (CTOK(0)) } // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TBAD) { Return (CTOK(0)) } // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + Local0 += \_SB.PCI0.LPCB.EC0.TOFS // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) + Local0 *= 10 Return (Local0) } /* CTDP Down */ Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (\F0OF)) } Else { Return (CTOK (\F0ON)) @@ -142,7 +142,7 @@ Scope (\_TZ) /* CTDP Nominal */ Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (\F1OF)) } Else { Return (CTOK (\F1ON)) @@ -155,19 +155,19 @@ Scope (\_TZ) PowerResource (TNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) + \FLVL = 0 \_SB.PCI0.MCHC.STND () Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) + \FLVL = 1 \_SB.PCI0.MCHC.STDN () Notify (\_TZ.THRM, 0x81) } @@ -176,18 +176,18 @@ Scope (\_TZ) PowerResource (TNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } } From 62a437dd88742af332c4950a09f935bbf3d9812b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 4 Oct 2020 14:57:37 +0200 Subject: [PATCH 033/262] mb/roda/rk886ex: Convert *.asl to ASL 2.0 syntax Generated 'build/dsdt.dsl' files are identical. Change-Id: I2eea24db6cfd260e0f36243e90a5e01b360f23fb Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46012 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/roda/rk886ex/acpi/battery.asl | 174 ++++++++--------- src/mainboard/roda/rk886ex/acpi/ec.asl | 38 ++-- src/mainboard/roda/rk886ex/acpi/platform.asl | 6 +- src/mainboard/roda/rk886ex/acpi/superio.asl | 192 +++++++++---------- src/mainboard/roda/rk886ex/acpi/thermal.asl | 2 +- 5 files changed, 206 insertions(+), 206 deletions(-) diff --git a/src/mainboard/roda/rk886ex/acpi/battery.asl b/src/mainboard/roda/rk886ex/acpi/battery.asl index de13049eb4..8f4f00c751 100644 --- a/src/mainboard/roda/rk886ex/acpi/battery.asl +++ b/src/mainboard/roda/rk886ex/acpi/battery.asl @@ -69,76 +69,76 @@ Device (BAT1) /* Update Battery Info */ Method(UPBI, 0) { - Store (0x78, Index(PBIF, 1)) - Store (0x64, Index(PBIF, 2)) - Store (0x2b5c, Index(PBIF, 4)) - Store ("Bat1", Index(PBIF, 9)) - Store ("001", Index(PBIF, 10)) - Store ("LION", Index(PBIF, 11)) - Store ("Panasonic", Index(PBIF, 12)) + PBIF [1] = 0x78 + PBIF [2] = 0x64 + PBIF [4] = 0x2b5c + PBIF [9] = "Bat1" + PBIF [10] = "001" + PBIF [11] = "LION" + PBIF [12] = "Panasonic" } Method(UPBS, 0) { - Store(\_SB.PCI0.LPCB.EC0.QEVT, Local0) - If (Not(Local0)) { - Store(0, GP38) + Local0 = \_SB.PCI0.LPCB.EC0.QEVT + If (~Local0) { + GP38 = 0 Sleep(0x64) - Store(GP38, Local0) - If (Not(Local0)) { - Store (RDW(0x0d), Local0) - If (LNotEqual(Local0, 0xeeee)) { - If (LLessEqual(Local0, 0x64)) { - Store(Local0, CBA1) + Local0 = GP38 + If (~Local0) { + Local0 = RDW (0x0d) + If (Local0 != 0xeeee) { + If (Local0 <= 0x64) { + CBA1 = Local0 } } } } - Store (CBA1, Local0) - Store (Local0, Index(PBST, 2)) - Store (DerefOf(Index(PBIF, 4)), Index(PBST, 3)) - Store (0, Local1) + Local0 = CBA1 + PBST [2] = Local0 + PBST [3] = DerefOf (PBIF [4]) + Local1 = 0 If (PWRS) { - If (LLess(Local0, 0x64)) { - Store (2, Local1) + If (Local0 < 0x64) { + Local1 = 2 } } Else { - If (LLessEqual(Local0, 0x5)) { - Store (4, Local1) + If (Local0 <= 0x5) { + Local1 = 4 } Else { - Store (1, Local1) + Local1 = 1 } } - Store (Local1, Index(PBST, 0)) + PBST [0] = Local1 If (\_SB.PCI0.LPCB.EC0.P63S) { - Store (0x16, Index(PBST, 1)) + PBST [1] = 0x16 } Else { - Store (0x0b, Index(PBST, 1)) + PBST [1] = 0x0b } } // Invalidate Battery Info Method(IVBI, 0) { - Store (0xffffffff, Index(PBIF, 1)) - Store (0xffffffff, Index(PBIF, 2)) - Store (0xffffffff, Index(PBIF, 4)) - Store ("Bad", Index(PBIF, 9)) - Store ("Bad", Index(PBIF, 10)) - Store ("Bad", Index(PBIF, 11)) - Store ("Bad", Index(PBIF, 12)) - Store (1, Index(PBIF, 0)) + PBIF [1] = 0xffffffff + PBIF [2] = 0xffffffff + PBIF [4] = 0xffffffff + PBIF [9] = "Bad" + PBIF [10] = "Bad" + PBIF [11] = "Bad" + PBIF [12] = "Bad" + PBIF [0] = 1 } Method(IVBS, 0) { - Store (0x0, Index(PBST, 0)) - Store (0xffffffff, Index(PBST, 1)) - Store (0xffffffff, Index(PBST, 2)) - Store (0xffffffff, Index(PBST, 3)) + PBST [0] = 0 + PBST [1] = 0xffffffff + PBST [2] = 0xffffffff + PBST [3] = 0xffffffff } } @@ -209,85 +209,85 @@ Device (BAT2) /* Update Battery Info */ Method(UPBI, 0) { - Store (0x78, Index(PBIF, 1)) - Store (0x64, Index(PBIF, 2)) - Store (0x2b5c, Index(PBIF, 4)) - Store ("Bat2", Index(PBIF, 9)) - Store ("002", Index(PBIF, 10)) - Store ("LION", Index(PBIF, 11)) - Store ("Panasonic", Index(PBIF, 12)) + PBIF [1] = 0x78 + PBIF [2] = 0x64 + PBIF [4] = 0x2b5c + PBIF [9] = "Bat2" + PBIF [10] = "002" + PBIF [11] = "LION" + PBIF [12] = "Panasonic" } Method(UPBS, 0) { - Store(\_SB.PCI0.LPCB.EC0.QEVT, Local0) - If (Not(Local0)) { - Store(0, GP38) + Local0 = \_SB.PCI0.LPCB.EC0.QEVT + If (~Local0) { + GP38 = 0 Sleep(0x64) - Store(GP38, Local0) - If (Not(Local0)) { - Store (RDW(0x0d), Local0) - If (LNotEqual(Local0, 0xeeee)) { - If (LLessEqual(Local0, 0x64)) { - Store(Local0, CBA2) + Local0 = GP38 + If (~Local0) { + Local0 = RDW (0x0d) + If (Local0 != 0xeeee) { + If (Local0 <= 0x64) { + CBA2 = Local0 } } } } - Store (CBA2, Local0) - Store (Local0, Index(PBST, 2)) - Store (DerefOf(Index(PBIF, 4)), Index(PBST, 3)) - Store (0, Local1) + Local0 = CBA2 + PBST [2] = Local0 + PBST [3] = DerefOf (PBIF [4]) + Local1 = 0 If (PWRS) { - If (LLess(Local0, 0x64)) { - Store (2, Local1) + If (Local0 < 0x64) { + Local1 = 2 } } Else { - If (LLessEqual(Local0, 0x5)) { - Store (4, Local1) + If (Local0 <= 0x5) { + Local1 = 4 } Else { - Store (1, Local1) + Local1 = 1 } } - Store (Local1, Index(PBST, 0)) + PBST [0] = Local1 If (\_SB.PCI0.LPCB.EC0.P62S) { - Store (0x16, Index(PBST, 1)) + PBST [1] = 0x16 } Else { - Store (0x0b, Index(PBST, 1)) + PBST [1] = 0x0b } } // Invalidate Battery Info Method(IVBI, 0) { - Store (0xffffffff, Index(PBIF, 1)) - Store (0xffffffff, Index(PBIF, 2)) - Store (0xffffffff, Index(PBIF, 4)) - Store ("Bad", Index(PBIF, 9)) - Store ("Bad", Index(PBIF, 10)) - Store ("Bad", Index(PBIF, 11)) - Store ("Bad", Index(PBIF, 12)) - Store (1, Index(PBIF, 0)) + PBIF [1] = 0xffffffff + PBIF [2] = 0xffffffff + PBIF [4] = 0xffffffff + PBIF [9] = "Bad" + PBIF [10] = "Bad" + PBIF [11] = "Bad" + PBIF [12] = "Bad" + PBIF [0] = 1 } Method(IVBS, 0) { - Store (0x0, Index(PBST, 0)) - Store (0xffffffff, Index(PBST, 1)) - Store (0xffffffff, Index(PBST, 2)) - Store (0xffffffff, Index(PBST, 3)) + PBST [0] = 0 + PBST [1] = 0xffffffff + PBST [2] = 0xffffffff + PBST [3] = 0xffffffff } } Method (RDW, 1) { - Store (0x16, \_SB.PCI0.LPCB.EC0.SMAD) - Store (Arg0, \_SB.PCI0.LPCB.EC0.SMCM) - Store (0x09, \_SB.PCI0.LPCB.EC0.SMPR) - While (LNotEqual(\_SB.PCI0.LPCB.EC0.SMPR, 0x00)) { + \_SB.PCI0.LPCB.EC0.SMAD = 0x16 + \_SB.PCI0.LPCB.EC0.SMCM = Arg0 + \_SB.PCI0.LPCB.EC0.SMPR = 0x09 + While (\_SB.PCI0.LPCB.EC0.SMPR != 0x00) { Stall (1) } @@ -300,11 +300,11 @@ Device (ADP1) Method (_PSR, 0) { If (\_SB.PCI0.LPCB.EC0.ECON) { - Store (\_SB.PCI0.LPCB.EC0.P60S, Local0) + Local0 = \_SB.PCI0.LPCB.EC0.P60S If (Local0) { - Store (0, PWRS) + PWRS = 0 } Else { - Store (1, PWRS) + PWRS = 1 } } diff --git a/src/mainboard/roda/rk886ex/acpi/ec.asl b/src/mainboard/roda/rk886ex/acpi/ec.asl index 9ec0c36234..9ebe4b5eac 100644 --- a/src/mainboard/roda/rk886ex/acpi/ec.asl +++ b/src/mainboard/roda/rk886ex/acpi/ec.asl @@ -63,8 +63,8 @@ Device(EC0) // This method is needed by Windows XP/2000 for // EC initialization before a driver is loaded - If (LEqual(Arg0, 0x03)) { - Store (Arg1, ECON) + If (Arg0 == 0x03) { + ECON = Arg1 } } @@ -72,20 +72,20 @@ Device(EC0) Method (_Q11, 0) { - Store("_Q11: Fn-F8 (Sleep Button) pressed", Debug) + Debug = "_Q11: Fn-F8 (Sleep Button) pressed" Notify(SLPB, 0x80) } Method (_Q12, 0) { - Store("_Q12: Fn-F9 (Display Switch) pressed", Debug) + Debug = "_Q12: Fn-F9 (Display Switch) pressed" Notify (\_SB.PCI0.GFX0, 0x82) - // Store(1, TLST) + // TLST = 1 } Method (_Q30, 0) { - Store("_Q30: AC In/Out", Debug) + Debug = "_Q30: AC In/Out" Notify(ADP1, 0x80) // Tell the Power Adapter PNOT() // and the CPU and Battery // Notify the Batteries @@ -95,16 +95,16 @@ Device(EC0) Method (_Q31, 0) { - Store("_Q31: LID Open/Close", Debug) + Debug = "_Q31: LID Open/Close" Notify(LID0, 0x80) } Method (_Q32, 0) { - Store("_Q32: Battery 1 In/Out", Debug) + Debug = "_Q32: Battery 1 In/Out" If (ECON) { - Store (P62S, Local0) - If (Not(Local0)) { + Local0 = P62S + If (~Local0) { Notify(BAT1, 0x80) } } @@ -112,10 +112,10 @@ Device(EC0) Method (_Q33, 0) { - Store("_Q33: Battery 2 In/Out", Debug) + Debug = "_Q33: Battery 2 In/Out" If (ECON) { - Store (P63S, Local0) - If (Not(Local0)) { + Local0 = P63S + If (~Local0) { Notify(BAT2, 0x80) } } @@ -123,33 +123,33 @@ Device(EC0) Method (_Q34, 0) { - Store("_Q34: LPT/FDD", Debug) + Debug = "_Q34: LPT/FDD" // PHSS(0x70) } Method (_Q35, 0) { - Store("_Q35: Processor is hot", Debug) + Debug = "_Q35: Processor is hot" } Method (_Q36, 0) { - Store("_Q36: Thermal Warning", Debug) + Debug = "_Q36: Thermal Warning" } Method (_Q37, 0) { - Store("_Q37: PME", Debug) + Debug = "_Q37: PME" } Method (_Q38, 0) { - Store("_Q38: Thermal", Debug) + Debug = "_Q38: Thermal" } Method (_Q39, 0) { - Store("_Q39: Thermal", Debug) + Debug = "_Q39: Thermal" } // TODO Scope _SB devices for AC power, LID, Power button diff --git a/src/mainboard/roda/rk886ex/acpi/platform.asl b/src/mainboard/roda/rk886ex/acpi/platform.asl index fb272ddc68..d62e051ad0 100644 --- a/src/mainboard/roda/rk886ex/acpi/platform.asl +++ b/src/mainboard/roda/rk886ex/acpi/platform.asl @@ -20,12 +20,12 @@ Method(_WAK,1) // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } @@ -56,7 +56,7 @@ Scope(\_SB) * running: Windows XP SP1 needs to have C-State coordination * enabled in SMM. */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { + If ((OSYS == 2001) && MPEN) { // TRAP(61) // TODO } diff --git a/src/mainboard/roda/rk886ex/acpi/superio.asl b/src/mainboard/roda/rk886ex/acpi/superio.asl index 6f356e9833..d1c670c8c2 100644 --- a/src/mainboard/roda/rk886ex/acpi/superio.asl +++ b/src/mainboard/roda/rk886ex/acpi/superio.asl @@ -19,13 +19,13 @@ Device (SIO1) Method (READ, 3) { Acquire (SIOM, 0xffff) - If (LEqual(Arg0, 0)) { - Store (0x55, INDX) - Store (Arg1, INDX) - Store (DATA, Local1) - Store (0xaa, INDX) + If (Arg0 == 0) { + INDX = 0x55 + INDX = Arg1 + Local1 = DATA + INDX = 0xaa } - And (Local1, Arg2, Local1) + Local1 &= Arg2 Release(SIOM) Return(Local1) } @@ -33,11 +33,11 @@ Device (SIO1) Method (WRIT, 3) { Acquire (SIOM, 0xffff) - If (LEqual(Arg0, 0)) { - Store (0x55, INDX) - Store (Arg1, INDX) - Store (Arg2, DATA) - Store (0xaa, INDX) + If (Arg0 == 0) { + INDX = 0x55 + INDX = Arg1 + DATA = Arg2 + INDX = 0xaa } Release(SIOM) } @@ -52,18 +52,18 @@ Device (SIO1) Method (_STA, 0) { // Device disabled by coreboot? - If (LEqual(CMAP, 0)) { + If (CMAP == 0) { Return (0) } // Is the hardware enabled? - Store (READ(0, 0x24, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x24, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x08), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x08) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -76,12 +76,12 @@ Device (SIO1) { WRIT(0, 0x24, 0x00) - Store(READ(0, 0x28, 0x0f), Local0) + Local0 = READ (0, 0x28, 0x0f) WRIT(0, 0x28, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -106,8 +106,8 @@ Device (SIO1) IRQNoFlags(_IRA) { 4 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA() & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -119,15 +119,15 @@ Device (SIO1) \_SB.PCI0.LPCB.SIO1.COMA._CRS._IRA._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x24, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x24, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x28, 0xf0), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x28, 0xf0) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -140,29 +140,29 @@ Device (SIO1) WRIT(0, 0x24, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) - ShiftLeft(Local0, 4, Local0) + Local0-- + Local0 <<= 4 - Store(READ(0, 0x28, 0x0f), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0, 0x28, 0x0f) + Local0 |= Local1 WRIT(0, 0x28, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x24, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x08, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x08 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x40, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x40 + Local0 &= Local1 WRIT(0, 0x07, Local0) } @@ -170,22 +170,22 @@ Device (SIO1) /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x08, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x08 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x40, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x40 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } @@ -200,24 +200,24 @@ Device (SIO1) Method (_STA, 0) { // Device disabled by coreboot? - If (LEqual(CMBP, 0)) { + If (CMBP == 0) { Return (0) } /* IRDA? */ - Store(READ(0, 0x0c, 0x38), Local0) - If (LNotEqual(Local0, Zero)) { + Local0 = READ (0, 0x0c, 0x38) + If (Local0 != 0) { Return (0) } // Is the hardware enabled? - Store (READ(0, 0x25, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x25, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x80), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x80) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -230,12 +230,12 @@ Device (SIO1) { WRIT(0, 0x25, 0x00) - Store(READ(0, 0x28, 0xf0), Local0) + Local0 = READ (0, 0x28, 0xf0) WRIT(0, 0x28, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x80, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x80 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -260,8 +260,8 @@ Device (SIO1) IRQNoFlags(_IRB) { 3 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA() & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -273,14 +273,14 @@ Device (SIO1) \_SB.PCI0.LPCB.SIO1.COMB._CRS._IRB._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x25, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x25, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x28, 0x0f), Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x28, 0x0f) + IRQ = 1 << Local0 Return(RSRC) } @@ -293,55 +293,55 @@ Device (SIO1) WRIT(0, 0x25, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) + Local0-- - Store(READ(0, 0x28, 0xf0), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0, 0x28, 0xf0) + Local0 |= Local1 WRIT(0, 0x28, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x25, Local0) - Store(READ(0, 0x0c, 0xff), Local0) - Not(0x38, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x0c, 0xff) + Local1 = ~0x38 + Local0 &= Local1 WRIT(0, 0x0c, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x80, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x80 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x20, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x20 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x80, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x80 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x20, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x20 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x80, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x80 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } diff --git a/src/mainboard/roda/rk886ex/acpi/thermal.asl b/src/mainboard/roda/rk886ex/acpi/thermal.asl index ff7639f877..29d501f6bc 100644 --- a/src/mainboard/roda/rk886ex/acpi/thermal.asl +++ b/src/mainboard/roda/rk886ex/acpi/thermal.asl @@ -29,7 +29,7 @@ Scope (\_TZ) // Critical shutdown temperature Method (_CRT, 0, Serialized) { - Return (Add (0x0aac, 0x50)) // FIXME + Return (0x0aac + 0x50) // FIXME } // CPU throttling start temperature From f0334b86dd569ac229c8a317d929ab7504c07fcf Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 9 Oct 2020 15:05:48 +0200 Subject: [PATCH 034/262] soc/intel/xeon_sp: Convert to ASL 2.0 syntax Change-Id: I43e36f2e736192603be61519d3e185605e81f0e8 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46243 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/xeon_sp/acpi/southcluster.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/xeon_sp/acpi/southcluster.asl b/src/soc/intel/xeon_sp/acpi/southcluster.asl index effed432ba..d1fd98fbab 100644 --- a/src/soc/intel/xeon_sp/acpi/southcluster.asl +++ b/src/soc/intel/xeon_sp/acpi/southcluster.asl @@ -138,7 +138,7 @@ Method (_CRS, 0, Serialized) { Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -147,7 +147,7 @@ Method (_OSC, 4) { { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } From 50fcce54e03d8104e1222a53159f6775437a78c1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 6 Oct 2020 18:06:34 +0200 Subject: [PATCH 035/262] ec/purism/librem: Convert to ASL 2.0 syntax Generated build/dsdt.dsl are same for purism Librem 15 v4. Change-Id: I36cb7a2ebde1161f87e78eeab739b15e3cf88860 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46102 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/ec/purism/librem/acpi/battery.asl | 81 +++++++++++++-------------- src/ec/purism/librem/acpi/ec.asl | 26 ++++----- 2 files changed, 53 insertions(+), 54 deletions(-) diff --git a/src/ec/purism/librem/acpi/battery.asl b/src/ec/purism/librem/acpi/battery.asl index ca682a8f03..742dd250e6 100644 --- a/src/ec/purism/librem/acpi/battery.asl +++ b/src/ec/purism/librem/acpi/battery.asl @@ -65,13 +65,13 @@ Device (BAT) /* Method to enable full battery workaround */ Method (BFWE) { - Store (One, BFWK) + BFWK = 1 } /* Method to disable full battery workaround */ Method (BFWD) { - Store (Zero, BFWK) + BFWK = 0 } Method (_STA, 0, Serialized) @@ -86,22 +86,22 @@ Device (BAT) Method (_BIF, 0, Serialized) { /* Last Full Charge Capacity */ - Store (BTDF, Index (PBIF, 2)) + PBIF [2] = BTDF /* Design Voltage */ - Store (BTDV, Index (PBIF, 4)) + PBIF [4] = BTDV /* Design Capacity */ - Store (BTDA, Local0) - Store (Local0, Index (PBIF, 1)) + Local0 = BTDA + PBIF [1] = Local0 /* Design Capacity of Warning */ - Divide (Multiply (Local0, DWRN), 100, , Local2) - Store (Local2, Index (PBIF, 5)) + Local2 = (Local0 * DWRN) / 100 + PBIF [5] = Local2 /* Design Capacity of Low */ - Divide (Multiply (Local0, DLOW), 100, , Local2) - Store (Local2, Index (PBIF, 6)) + Local2 = (Local0 * DLOW) / 100 + PBIF [6] = Local2 Return (PBIF) } @@ -109,22 +109,22 @@ Device (BAT) Method (_BIX, 0, Serialized) { /* Last Full Charge Capacity */ - Store (BTDF, Index (PBIX, 3)) + PBIX [3] = BTDF /* Design Voltage */ - Store (BTDV, Index (PBIX, 5)) + PBIX [5] = BTDV /* Design Capacity */ - Store (BTDA, Local0) - Store (Local0, Index (PBIX, 2)) + Local0 = BTDA + PBIX [2] = Local0 /* Design Capacity of Warning */ - Divide (Multiply (Local0, DWRN), 100, , Local2) - Store (Local2, Index (PBIX, 6)) + Local2 = (Local0 * DWRN) / 100 + PBIX [6] = Local2 /* Design Capacity of Low */ - Divide (Multiply (Local0, DLOW), 100, , Local2) - Store (Local2, Index (PBIX, 7)) + Local2 = (Local0 * DLOW) / 100 + PBIX [7] = Local2 Return (PBIX) } @@ -142,61 +142,60 @@ Device (BAT) /* Check if AC is present */ If (ACEX) { /* Read battery status from EC */ - Store (BSTS, Local0) + Local0 = BSTS } Else { /* Always discharging when on battery power */ - Store (0x01, Local0) + Local0 = 0x01 } /* Check for critical battery level */ If (BFCR) { - Or (Local0, 0x04, Local0) + Local0 |= 0x04 } - Store (Local0, Index (PBST, 0)) + PBST [0] = Local0 /* Notify if battery state has changed since last time */ - If (LNotEqual (Local0, BSTP)) { - Store (Local0, BSTP) + If (Local0 != BSTP) { + BSTP = Local0 Notify (BAT, 0x80) } /* * 1: BATTERY PRESENT RATE */ - Store (BTPR, Local1) - If (And (Local1, 0x8000)) { - And (Not (Local1), 0x7FFF, Local0) - Increment (Local0) + Local1 = BTPR + If (Local1 & 0x8000) { + Local0 = ~Local1 & 0x7FFF + Local0++ } Else { - And (Local1, 0x7FFF, Local0) + Local0 = Local1 & 0x7FFF } - If(LLess(Local0, 0x0352)) + If(Local0 < 0x0352) { - Store(0x0352, Local0) + Local0 = 0x0352 } - Store (Local0, Index (PBST, 1)) + PBST [1] = Local0 /* * 2: BATTERY REMAINING CAPACITY */ - Store (BTRA, Local0) - If (LAnd (BFWK, LAnd (ACEX, LNot (BSTS)))) { - Store (BTDF, Local1) + Local0 = BTRA + If (BFWK && ACEX && !BSTS) { + Local1 = BTDF /* See if within ~6% of full */ - ShiftRight (Local1, 4, Local2) - If (LAnd (LGreater (Local0, Subtract (Local1, Local2)), - LLess (Local0, Add (Local1, Local2)))) + Local2 = Local1 >> 4 + If ((Local0 > (Local1 - Local2)) && (Local0 < (Local1 + Local2))) { - Store (Local1, Local0) + Local0 = Local1 } } - Store (Local0, Index (PBST, 2)) + PBST [2] = Local0 /* * 3: BATTERY PRESENT VOLTAGE */ - Store (BTVO, Index (PBST, 3)) + PBST [3] = BTVO Return (PBST) } diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl index 668b7d11bf..bf855af35b 100644 --- a/src/ec/purism/librem/acpi/ec.asl +++ b/src/ec/purism/librem/acpi/ec.asl @@ -15,12 +15,12 @@ Device (TPSD) Method (FNCX, 1, NotSerialized) { - If (LEqual (Arg0, 0x86)) { + If (Arg0 == 0x86) { /* Enable topstar-laptop kernel driver handling */ - Store (One, ^^EC.TPSE) - } ElseIf (LEqual (Arg0, 0x87)) { + ^^EC.TPSE = 1 + } ElseIf (Arg0 == 0x87) { /* Disable topstar-laptop kernel driver handling */ - Store (Zero, ^^EC.TPSE) + ^^EC.TPSE = 0 } } } @@ -80,10 +80,10 @@ Device (EC) Method (_REG, 2, NotSerialized) { /* Initialize AC power state */ - Store (ACEX, \PWRS) + \PWRS = ACEX /* Initialize LID switch state */ - Store (LIDS, \LIDS) + \LIDS = LIDS } /* Notify topstar-laptop kernel driver */ @@ -115,7 +115,7 @@ Device (EC) /* AC Status Changed */ Method (_Q20) { - Store (ACEX, \PWRS) + \PWRS = ACEX Notify (AC, 0x80) Notify (BAT, 0x80) PNOT () @@ -124,7 +124,7 @@ Device (EC) /* Lid Event */ Method (_Q21) { - Store (LIDS, \LIDS) + \LIDS = LIDS Notify (LID0, 0x80) } @@ -193,7 +193,7 @@ Device (EC) /* KEY_BLUETOOTH */ Method (_Q37) { - XOr (^BTLE, One, ^BTLE) + ^BTLE ^= 1 } /* Turbo Enable/Disable */ @@ -208,13 +208,13 @@ Device (EC) * when the system is charging. */ If (TURB) { - Store (PPCM_TURBO, PPCM) + PPCM = PPCM_TURBO PPCN () - Store (One, EDTB) + EDTB = 1 } Else { - Store (PPCM_NOTURBO, PPCM) + PPCM = PPCM_NOTURBO PPCN () - Store (Zero, EDTB) + EDTB = 0 } } From 38eaf3e13f3d430f3f096e1b8881aa585a60f41a Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 8 Oct 2020 10:10:38 +0200 Subject: [PATCH 036/262] mb/samsung/stumpy: Convert to ASL 2.0 syntax Generated 'build/dsdt.dsl' files are same. Change-Id: I0eda144f1a4f07ca82b3a799afcd8fc908419e69 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46215 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- .../samsung/stumpy/acpi/platform.asl | 24 +++--- src/mainboard/samsung/stumpy/acpi/thermal.asl | 74 +++++++++---------- 2 files changed, 49 insertions(+), 49 deletions(-) diff --git a/src/mainboard/samsung/stumpy/acpi/platform.asl b/src/mainboard/samsung/stumpy/acpi/platform.asl index 39e414b30a..ed056db475 100644 --- a/src/mainboard/samsung/stumpy/acpi/platform.asl +++ b/src/mainboard/samsung/stumpy/acpi/platform.asl @@ -6,36 +6,36 @@ Method(_PTS,1) { - Store (Zero, GP08) // Disable Bluetooth + GP08 = 0 // Disable Bluetooth - If (LEqual (Arg0, 3)) { + If (Arg0 == 3) { // NVS has a flag to determine USB policy in S3 If (S3U0) { - Store (One, GP47) // Enable USB0 + GP47 = 1 // Enable USB0 } Else { - Store (Zero, GP47) // Disable USB0 + GP47 = 0 // Disable USB0 } // NVS has a flag to determine USB policy in S3 If (S3U1) { - Store (One, GP56) // Enable USB1 + GP56 = 1 // Enable USB1 } Else { - Store (Zero, GP56) // Disable USB1 + GP56 = 0 // Disable USB1 } } - If (LEqual (Arg0, 5)) { + If (Arg0 == 5) { // NVS has a flag to determine USB policy in S5 If (S5U0) { - Store (One, GP47) // Enable USB0 + GP47 = 1 // Enable USB0 } Else { - Store (Zero, GP47) // Disable USB0 + GP47 = 0 // Disable USB0 } // NVS has a flag to determine USB policy in S5 If (S5U1) { - Store (One, GP56) // Enable USB1 + GP56 = 1 // Enable USB1 } Else { - Store (Zero, GP56) // Disable USB1 + GP56 = 0 // Disable USB1 } } } @@ -66,5 +66,5 @@ IndexField (NVRI, NVRD, ByteAcc, NoLock, Preserve) /* Disable USB Controller Reset in S3 (defaults to enabled) */ Method (USBR, 0, Serialized) { - Store (USB_RESET_DISABLE_MAGIC, US3B) + US3B = USB_RESET_DISABLE_MAGIC } diff --git a/src/mainboard/samsung/stumpy/acpi/thermal.asl b/src/mainboard/samsung/stumpy/acpi/thermal.asl index 39df88ac5f..cf44aba767 100644 --- a/src/mainboard/samsung/stumpy/acpi/thermal.asl +++ b/src/mainboard/samsung/stumpy/acpi/thermal.asl @@ -20,10 +20,10 @@ Scope (\_TZ) // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -49,28 +49,28 @@ Scope (\_TZ) Method (_TMP, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN3 // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If ((Local0 == 255) || (Local0 == 0)) { Return (CTOK (\F2ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { + If (Local1 >= \TMAX) { Return (CTOK (\TMAX)) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (\F0OF)) } Else { Return (CTOK (\F0ON)) @@ -78,7 +78,7 @@ Scope (\_TZ) } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (\F1OF)) } Else { Return (CTOK (\F1ON)) @@ -86,7 +86,7 @@ Scope (\_TZ) } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (\F2OF)) } Else { Return (CTOK (\F2ON)) @@ -94,7 +94,7 @@ Scope (\_TZ) } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (\F3OF)) } Else { Return (CTOK (\F3ON)) @@ -102,7 +102,7 @@ Scope (\_TZ) } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (\F4OF)) } Else { Return (CTOK (\F4ON)) @@ -118,20 +118,20 @@ Scope (\_TZ) PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) - Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F0PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } } @@ -139,20 +139,20 @@ Scope (\_TZ) PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } } @@ -160,20 +160,20 @@ Scope (\_TZ) PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } } @@ -181,20 +181,20 @@ Scope (\_TZ) PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } @@ -202,20 +202,20 @@ Scope (\_TZ) PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } From 12f69c5ef1f22355867974318410a1671014dcfe Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 8 Oct 2020 10:05:44 +0200 Subject: [PATCH 037/262] mb/ocp/tiogapass: Convert to ASL 2.0 syntax Generated build/dsdt.dsl files are identical. Change-Id: Iffd6954dcb3f9fb8bcd89854d84f6944cb520dd1 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46208 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/mainboard/ocp/tiogapass/acpi/platform.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/ocp/tiogapass/acpi/platform.asl b/src/mainboard/ocp/tiogapass/acpi/platform.asl index 3398568f1c..02c32f93b7 100644 --- a/src/mainboard/ocp/tiogapass/acpi/platform.asl +++ b/src/mainboard/ocp/tiogapass/acpi/platform.asl @@ -329,9 +329,9 @@ Field (PSYS, ByteAcc, NoLock, Preserve) /* SMI I/O Trap */ Method (TRAP, 1, Serialized) { - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler + SMIF = Arg0 // SMI Function + TRP0 = 0 // Generate trap + Return (SMIF) // Return value of SMI handler } /* @@ -345,7 +345,7 @@ Method (TRAP, 1, Serialized) Method (_PIC, 1) { /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) + PICM = Arg0 } /* From b29769a39160d4a6efe0dc863ba889388536fda5 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 8 Oct 2020 10:04:52 +0200 Subject: [PATCH 038/262] mb/ocp/deltalake: Convert to ASL 2.0 syntax Generated build/dsdt.dsl files are same. Change-Id: I5bd8fe629fb969ec14dd400b6463ee1592d6903b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46207 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/mainboard/ocp/deltalake/acpi/platform.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/ocp/deltalake/acpi/platform.asl b/src/mainboard/ocp/deltalake/acpi/platform.asl index e04bde5d19..286cc6cb99 100644 --- a/src/mainboard/ocp/deltalake/acpi/platform.asl +++ b/src/mainboard/ocp/deltalake/acpi/platform.asl @@ -329,9 +329,9 @@ Field (PSYS, ByteAcc, NoLock, Preserve) /* SMI I/O Trap */ Method (TRAP, 1, Serialized) { - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler + SMIF = Arg0 // SMI Function + TRP0 = 0 // Generate trap + Return (SMIF) // Return value of SMI handler } /* @@ -345,7 +345,7 @@ Method (TRAP, 1, Serialized) Method (_PIC, 1) { /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) + PICM = Arg0 } /* From 0be783b30e76a9f9aa6bf65eb315a02cb91cbe23 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 8 Oct 2020 10:10:17 +0200 Subject: [PATCH 039/262] mb/samsung/lumpy: Convert to ASL 2.0 syntax Generated 'build/dsdt.dsl' files are identical. Change-Id: I7ad79a31142af8ae1b62497ade0b4ba7bac3a93c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46214 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- .../samsung/lumpy/acpi/mainboard.asl | 2 +- src/mainboard/samsung/lumpy/acpi/platform.asl | 32 +++++++++---------- src/mainboard/samsung/lumpy/acpi/thermal.asl | 32 +++++++++---------- 3 files changed, 33 insertions(+), 33 deletions(-) diff --git a/src/mainboard/samsung/lumpy/acpi/mainboard.asl b/src/mainboard/samsung/lumpy/acpi/mainboard.asl index 9b5ae77b4d..d9c9d614a7 100644 --- a/src/mainboard/samsung/lumpy/acpi/mainboard.asl +++ b/src/mainboard/samsung/lumpy/acpi/mainboard.asl @@ -8,7 +8,7 @@ Scope (\_SB) { Name(_HID, EisaId("PNP0C0D")) Method(_LID, 0) { - Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + \LIDS = \_SB.PCI0.LPCB.EC0.LIDS Return (\LIDS) } diff --git a/src/mainboard/samsung/lumpy/acpi/platform.asl b/src/mainboard/samsung/lumpy/acpi/platform.asl index 579308de5f..0b83f50d4f 100644 --- a/src/mainboard/samsung/lumpy/acpi/platform.asl +++ b/src/mainboard/samsung/lumpy/acpi/platform.asl @@ -6,43 +6,43 @@ Method(_PTS,1) { - Store (Zero, GP35) // Disable WLAN - Store (Zero, GP38) // Disable WWAN + GP35 = 0 // Disable WLAN + GP38 = 0 // Disable WWAN If (S33G) { - Store (Zero, GP43) // Enable HSPA + GP43 = 0 // Enable HSPA } Else { - Store (One, GP43) // Disable HSPA + GP43 = 1 // Disable HSPA } - If (LEqual (Arg0, 3)) { + If (Arg0 == 3) { // NVS has a flag to determine USB policy in S3 If (S3U0) { - Store (One, GP47) // Enable USB0 + GP47 = 1 // Enable USB0 } Else { - Store (Zero, GP47) // Disable USB0 + GP47 = 0 // Disable USB0 } // NVS has a flag to determine USB policy in S3 If (S3U1) { - Store (One, GP56) // Enable USB1 + GP56 = 1 // Enable USB1 } Else { - Store (Zero, GP56) // Disable USB1 + GP56 = 0 // Disable USB1 } } - If (LEqual (Arg0, 5)) { + If (Arg0 == 5) { // NVS has a flag to determine USB policy in S5 If (S5U0) { - Store (One, GP47) // Enable USB0 + GP47 = 1 // Enable USB0 } Else { - Store (Zero, GP47) // Disable USB0 + GP47 = 0 // Disable USB0 } // NVS has a flag to determine USB policy in S5 If (S5U1) { - Store (One, GP56) // Enable USB1 + GP56 = 1 // Enable USB1 } Else { - Store (Zero, GP56) // Disable USB1 + GP56 = 0 // Disable USB1 } } } @@ -52,10 +52,10 @@ Method(_PTS,1) Method(_WAK,1) { /* Update in case state changed while asleep */ - Store (\_SB.PCI0.LPCB.EC0.ACEX, \PWRS) + \PWRS = \_SB.PCI0.LPCB.EC0.ACEX /* Enable OS control of fan */ - Store (One, \_SB.PCI0.LPCB.EC0.FCOS) + \_SB.PCI0.LPCB.EC0.FCOS = 1 Return(Package(){0,0}) } diff --git a/src/mainboard/samsung/lumpy/acpi/thermal.asl b/src/mainboard/samsung/lumpy/acpi/thermal.asl index dd85181e6f..55923bd9ca 100644 --- a/src/mainboard/samsung/lumpy/acpi/thermal.asl +++ b/src/mainboard/samsung/lumpy/acpi/thermal.asl @@ -26,10 +26,10 @@ Scope (\_TZ) // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -55,27 +55,27 @@ Scope (\_TZ) Method (_TMP, 0, Serialized) { // Get CPU Temperature from the Embedded Controller - Store (\_SB.PCI0.LPCB.EC0.CPUT, Local0) + Local0 = \_SB.PCI0.LPCB.EC0.CPUT // Re-read from EC if the temperature is very high to // avoid OS shutdown if we got a bad reading. - If (LGreaterEqual (Local0, \TCRT)) { - Store (\_SB.PCI0.LPCB.EC0.CPUT, Local0) - If (LGreaterEqual (Local0, \TCRT)) { + If (Local0 >= \TCRT) { + Local0 = \_SB.PCI0.LPCB.EC0.CPUT + If (Local0 >= \TCRT) { // Check if this is an early read - If (LLess (CRDC, IRDC)) { - Store (0, Local0) + If (CRDC < IRDC) { + Local0 = 0 } } } // Keep track of first few reads by the OS - If (LLess (CRDC, IRDC)) { - Increment (CRDC) + If (CRDC < IRDC) { + CRDC++ } // Invalid reading, ensure fan is spinning - If (LGreaterEqual (Local0, 0x80)) { + If (Local0 >= 0x80) { Return (CTOK (\F4ON)) } @@ -83,7 +83,7 @@ Scope (\_TZ) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (\F0OF)) } Else { Return (CTOK (\F0ON)) @@ -91,7 +91,7 @@ Scope (\_TZ) } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (\F1OF)) } Else { Return (CTOK (\F1ON)) @@ -99,7 +99,7 @@ Scope (\_TZ) } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (\F2OF)) } Else { Return (CTOK (\F2ON)) @@ -107,7 +107,7 @@ Scope (\_TZ) } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (\F3OF)) } Else { Return (CTOK (\F3ON)) @@ -115,7 +115,7 @@ Scope (\_TZ) } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (\F4OF)) } Else { Return (CTOK (\F4ON)) From 7f44929ed91d3f3157f2d26673fadb74ae7d8ff4 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 22 Oct 2020 14:03:46 +0200 Subject: [PATCH 040/262] soc/intel/xeon_sp: Add a smm_region function This reports where TSEG is located and will be used when setting up SMM. Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/46657 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/Makefile.inc | 3 ++- .../intel/xeon_sp/cpx/include/soc/pci_devs.h | 10 +++++++-- src/soc/intel/xeon_sp/memmap.c | 22 +++++++++++++++++++ .../intel/xeon_sp/skx/include/soc/pci_devs.h | 10 +++++++-- 4 files changed, 40 insertions(+), 5 deletions(-) create mode 100644 src/soc/intel/xeon_sp/memmap.c diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 40a1020c5c..07fe3debb4 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -6,8 +6,9 @@ subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c -romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c +romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c chip_common.c +ramstage-y += memmap.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index bb0f877560..68dee28a07 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -77,8 +77,14 @@ #define VMD_FUNC_NUM 0x05 #define MMAP_VTD_CFG_REG_DEVID 0x2024 -#define VTD_DEV 0x5 -#define VTD_FUNC 0x0 +#define VTD_DEV_NUM 0x5 +#define VTD_FUNC_NUM 0x0 + +#if !defined(__SIMPLE_DEVICE__) +#define VTD_DEV(bus) pcidev_path_on_bus((bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM)) +#else +#define VTD_DEV(bus) PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM) +#endif #define APIC_DEV_NUM 0x05 #define APIC_FUNC_NUM 0x04 diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c new file mode 100644 index 0000000000..79ab47eaed --- /dev/null +++ b/src/soc/intel/xeon_sp/memmap.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void smm_region(uintptr_t *start, size_t *size) +{ + uintptr_t tseg_base = pci_read_config32(VTD_DEV(0), VTD_TSEG_BASE_CSR); + uintptr_t tseg_limit = pci_read_config32(VTD_DEV(0), VTD_TSEG_LIMIT_CSR); + + tseg_base = ALIGN_DOWN(tseg_base, 1 * MiB); + tseg_limit = ALIGN_DOWN(tseg_limit, 1 * MiB); + /* Only the upper [31:20] bits of an address are checked against + * VTD_TSEG_LIMIT_CSR[31:20] which must be below or equal, so this + * effectively means +1MiB for the limit. + */ + tseg_limit += 1 * MiB; + + *start = tseg_base; + *size = tseg_limit - tseg_base; +} diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 6b84f70d3b..b500c2896c 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -126,8 +126,14 @@ #define HPET0_FUNC_NUM 0x00 #define MMAP_VTD_CFG_REG_DEVID 0x2024 -#define VTD_DEV 5 -#define VTD_FUNC 0 +#define VTD_DEV_NUM 0x5 +#define VTD_FUNC_NUM 0x0 + +#if !defined(__SIMPLE_DEVICE__) +#define VTD_DEV(bus) pcidev_path_on_bus((bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM)) +#else +#define VTD_DEV(bus) PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM) +#endif #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) From d8b36d23fae042824d95d2b5e6685cc789070525 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 3 Nov 2020 19:58:29 +0100 Subject: [PATCH 041/262] soc/amd/common/psp: move v1-only mailbox commands to separate section Two of the PSP mailbox commands are only applicable to the first generation of PSP mailbox interface. Change-Id: Ice940ee780c3d96ae1d9ec7ba49ea4add00e8723 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47180 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/common/block/psp/psp_def.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 47741fa3ef..38d62066b2 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -18,9 +18,10 @@ #define MBOX_BIOS_CMD_CLEAR_S3_STS 0x07 #define MBOX_BIOS_CMD_S3_DATA_INFO 0x08 #define MBOX_BIOS_CMD_NOP 0x09 +#define MBOX_BIOS_CMD_ABORT 0xfe +/* x86 to PSP commands, v1 */ #define MBOX_BIOS_CMD_SMU_FW 0x19 #define MBOX_BIOS_CMD_SMU_FW2 0x1a -#define MBOX_BIOS_CMD_ABORT 0xfe /* generic PSP interface status, v1 */ #define PSPV1_STATUS_INITIALIZED BIT(0) From 40368a29a160a345210249f351a005c7233a7e6c Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 3 Nov 2020 12:53:00 -0600 Subject: [PATCH 042/262] mb/purism/librem_mini: drop SendVrMbxCmd from devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not needed for this board. Change-Id: I15a68b59bc512e571b9590007ea64561b3f3dae1 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47184 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- .../purism/librem_cnl/variants/librem_mini/devicetree.cb | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 205033230b..40779a2116 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -4,9 +4,6 @@ chip soc/intel/cannonlake .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, }" - # Send an extra VR mailbox command for the PS4 exit issue - register "SendVrMbxCmd" = "2" - # ACPI (soc/intel/cannonlake/acpi.c) # Disable s0ix register "s0ix_enable" = "0" From 0b327a4c3a74da879476ef919d7b45bf628ffd8e Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 3 Nov 2020 13:02:38 -0600 Subject: [PATCH 043/262] mb/purism/librem_mini: Drop devicetree settings which default to 0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All chip registers default to 0, no need to explicitly set them. Change-Id: I056121170d22393484b0ee79bd0815452161a900 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47185 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- .../variants/librem_mini/devicetree.cb | 47 ------------------- 1 file changed, 47 deletions(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 40779a2116..308fa69489 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -4,16 +4,6 @@ chip soc/intel/cannonlake .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, }" -# ACPI (soc/intel/cannonlake/acpi.c) - # Disable s0ix - register "s0ix_enable" = "0" - - # PM Timer Enabled - register "PmTimerDisabled" = "0" - - # Disable DPTF - register "dptf_enable" = "0" - # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ @@ -28,45 +18,13 @@ chip soc/intel/cannonlake register "SaGv" = "SaGv_Enabled" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # Serial I/O - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexSPI1] = PchSerialIoDisabled, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoDisabled, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - # SATA register "SataMode" = "Sata_AHCI" - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" # 2.5" register "SataPortsEnable[2]" = "1" # m.2 - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[2]" = "0" # Audio - register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - register "PchHdaAudioLinkDmic0" = "0" - register "PchHdaAudioLinkDmic1" = "0" - register "PchHdaAudioLinkSsp0" = "0" - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkSsp2" = "0" - register "PchHdaAudioLinkSndw1" = "0" - register "PchHdaAudioLinkSndw2" = "0" - register "PchHdaAudioLinkSndw3" = "0" - register "PchHdaAudioLinkSndw4" = "0" - - # USB - register "SsicPortEnable" = "0" # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper @@ -107,7 +65,6 @@ chip soc/intel/cannonlake # PCI Express Root Port #10 x1, Clock 3 (LAN) register "PcieRpEnable[9]" = "1" - register "PcieRpLtrEnable[9]" = "0" # PCI Express Root port #13 x4, Clock 1 (NVMe) register "PcieRpEnable[12]" = "1" @@ -129,10 +86,6 @@ chip soc/intel/cannonlake # Serial IRQ Mode register "serirq_mode" = "SERIRQ_CONTINUOUS" -# PMC (soc/intel/cannonlake/pmc.c) - # Disable deep Sx states - register "deep_sx_config" = "0" - # PM Util (soc/intel/cannonlake/pmutil.c) # GPE configuration # Note that GPE events called out in ASL code rely on this From a41991a3f91987c04c2c80f271d9e63d32ca4338 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 3 Nov 2020 13:05:04 -0600 Subject: [PATCH 044/262] mb/purism/librem_mini: Increase TDP/PL2 setting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PL2 was set artificially low during development when the active cooling fan was not functional, and never corrected once the fan was fixed. Raise PL2 to a value which works with both Librem Mini variants. Change-Id: Ie377392020f73359aed80ddae727adb6f8d06344 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47186 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- .../purism/librem_cnl/variants/librem_mini/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 308fa69489..9d2b34b16c 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -8,7 +8,7 @@ chip soc/intel/cannonlake # Power limit register "power_limits_config" = "{ .tdp_pl1_override = 25, - .tdp_pl2_override = 28, + .tdp_pl2_override = 51, }" # Enable Enhanced Intel SpeedStep From 6e651aaf4e0705722ce4bc499ee44d9a7cf9891e Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 3 Nov 2020 13:09:02 -0600 Subject: [PATCH 045/262] mb/purism/librem_mini: drop unused HeciEnabled register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit this should have been corrected as part of: commit 3de90d1 [soc/intel/cnl: Set Heci1Disable depending on devicetree config] Change-Id: I6a103a1de01fc258ef359258a8a64f4c5a181139 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47187 Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../purism/librem_cnl/variants/librem_mini/devicetree.cb | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 9d2b34b16c..ae19b041b5 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -204,10 +204,7 @@ chip soc/intel/cannonlake device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off # Management Engine Interface 1 - # HECI must be enabled w/HAP disable else S3 issues - register "HeciEnabled" = "1" - end + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection From b808e7678d79994dbc5ed4cfaff20959222e5c2e Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 3 Nov 2020 13:17:30 -0600 Subject: [PATCH 046/262] mb/purism/librem_mini: Reorganize devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move registers under devices to which they belong. Change-Id: I61ca7c1db02646252d7421f8b79dfc8a40b2bdb5 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47188 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../variants/librem_mini/devicetree.cb | 65 ++++++++----------- 1 file changed, 27 insertions(+), 38 deletions(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index ae19b041b5..c69f3f635e 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -18,30 +18,6 @@ chip soc/intel/cannonlake register "SaGv" = "SaGv_Enabled" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # SATA - register "SataMode" = "Sata_AHCI" - register "SataPortsEnable[0]" = "1" # 2.5" - register "SataPortsEnable[2]" = "1" # m.2 - - # Audio - register "PchHdaAudioLinkHda" = "1" - - # USB2 - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper - register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth - register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower - - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper # All SRCCLKREQ pins mapped directly register "PcieClkSrcClkReq[0]" = "0" @@ -59,20 +35,8 @@ chip soc/intel/cannonlake register "PcieClkSrcUsage[4]" = "0x80" register "PcieClkSrcUsage[5]" = "0x80" - # PCI Express Root Port #8 x1, Clock 2 (WLAN) - register "PcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - - # PCI Express Root Port #10 x1, Clock 3 (LAN) - register "PcieRpEnable[9]" = "1" - - # PCI Express Root port #13 x4, Clock 1 (NVMe) - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - # Misc register "AcousticNoiseMitigation" = "1" - register "satapwroptimize" = "1" # Power register "PchPmSlpS3MinAssert" = "3" # 50ms @@ -198,6 +162,19 @@ chip soc/intel/cannonlake end end end + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth + register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper end device pci 14.1 off end # USB xDCI (OTG) device pci 15.0 off end # I2C #0 @@ -210,7 +187,12 @@ chip soc/intel/cannonlake device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA + device pci 17.0 on # SATA + register "SataMode" = "Sata_AHCI" + register "SataPortsEnable[0]" = "1" # 2.5" + register "SataPortsEnable[2]" = "1" # m.2 + register "satapwroptimize" = "1" + end device pci 19.0 off end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 off end # UART #2 @@ -224,15 +206,20 @@ chip soc/intel/cannonlake device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on # PCI Express Port 8 (WLAN) register "PcieRpSlotImplemented[7]" = "1" + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" end device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 on # PCI Express Port 10 (LAN) register "PcieRpSlotImplemented[9]" = "1" + register "PcieRpEnable[9]" = "1" end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on # PCI Express Port 13 (NVMe) register "PcieRpSlotImplemented[12]" = "1" + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" end device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 @@ -244,7 +231,9 @@ chip soc/intel/cannonlake device pci 1f.0 on end # LPC Bridge device pci 1f.1 off end # P2SB device pci 1f.2 off end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkHda" = "1" + end device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE From 0d29bb72a18a5e4866c4494bf509f1e7dd954003 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 3 Nov 2020 13:27:43 -0600 Subject: [PATCH 047/262] mb/purism_librem_mini: Add child device, slot descriptions to PCIe RPs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Id306100fc691dcbde48b65092d0be9d7e73c0722 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47189 Reviewed-by: Stefan Reinauer Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../librem_cnl/variants/librem_mini/devicetree.cb | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index c69f3f635e..9fde5e97da 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -204,22 +204,29 @@ chip soc/intel/cannonlake device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on # PCI Express Port 8 (WLAN) + device pci 1c.7 on # PCI Express Port 8 + chip drivers/wifi/generic + device pci 00.0 on end # x1 M.2/E 2230 (WLAN) + end register "PcieRpSlotImplemented[7]" = "1" register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" end device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 on # PCI Express Port 10 (LAN) + device pci 1d.1 on # PCI Express Port 10 + device pci 00.0 on end # x1 (LAN) register "PcieRpSlotImplemented[9]" = "1" register "PcieRpEnable[9]" = "1" end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on # PCI Express Port 13 (NVMe) + device pci 1d.4 on # PCI Express Port 13 + device pci 00.0 on end # x4 M.2/M 2280 (NVMe) register "PcieRpSlotImplemented[12]" = "1" register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 From 7bb756fad72698ff6ddbb9a39ff33e1ba62355c9 Mon Sep 17 00:00:00 2001 From: Benjamin Doron Date: Thu, 22 Oct 2020 17:26:18 +0000 Subject: [PATCH 048/262] util/intelp2m: Update macros Change-Id: Ia0a7dea89fdb69e01f0abe577488f26a5d2bd6ed Signed-off-by: Benjamin Doron Reviewed-on: https://review.coreboot.org/c/coreboot/+/45008 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Maxim Polyakov Reviewed-by: Stefan Reinauer --- util/intelp2m/platforms/snr/macro.go | 32 +++++++++++++++------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go index 86cc7b727f..43d373ee84 100644 --- a/util/intelp2m/platforms/snr/macro.go +++ b/util/intelp2m/platforms/snr/macro.go @@ -59,13 +59,13 @@ func (PlatformSpecific) Pull() { dw1 := macro.Register(PAD_CFG_DW1) var pull = map[uint8]string{ 0x0: "NONE", - 0x2: "5K_PD", - 0x4: "20K_PD", - 0x9: "1K_PU", - 0xa: "5K_PU", - 0xb: "2K_PU", - 0xc: "20K_PU", - 0xd: "667_PU", + 0x2: "DN_5K", + 0x4: "DN_20K", + 0x9: "UP_1K", + 0xa: "UP_5K", + 0xb: "UP_2K", + 0xc: "UP_20K", + 0xd: "UP_667", 0xf: "NATIVE", } str, valid := pull[dw1.GetTermination()] @@ -91,7 +91,9 @@ func ioApicRoute() bool { if dw0.GetRXLevelEdgeConfiguration() == common.TRIG_LEVEL { if dw0.GetRxInvert() != 0 { // PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) - macro.Add("_INVERT") + macro.Add("_LOW") + } else { + macro.Add("_HIGH") } // PAD_CFG_GPI_APIC(pad, pull, rst) macro.Add("(").Id().Pull().Rstsrc().Add("),") @@ -121,16 +123,16 @@ func sciRoute() bool { if dw0.GetGPIOInputRouteSCI() == 0 { return false } + macro.Add("_SCI").Add("(").Id().Pull().Rstsrc() + if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) == 0 { + macro.Trig() + } // e.g. PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) != 0 { // e.g. PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES), // #define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \ // PAD_CFG_GPI_SCI(pad, pull, rst, EDGE_SINGLE, inv) - macro.Add("_ACPI") - } - macro.Add("_SCI").Add("(").Id().Pull().Rstsrc() - if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) == 0 { - macro.Trig() + macro.Add(",").Add("EDGE_SINGLE") } macro.Invert().Add("),") return true @@ -143,11 +145,11 @@ func smiRoute() bool { if dw0.GetGPIOInputRouteSMI() == 0 { return false } + macro.Add("_SMI").Add("(").Id().Pull().Rstsrc() if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) != 0 { // e.g. PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), - macro.Add("_ACPI") + macro.Add(",").Add("EDGE_SINGLE") } - macro.Add("_SMI").Add("(").Id().Pull().Rstsrc() if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) == 0 { // e.g. PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), macro.Trig() From aa11f9a826362b4eb2a513402e4cc4f8216140ca Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 4 Nov 2020 00:29:59 -0600 Subject: [PATCH 049/262] mb/purism/librem_mini: Update GPIO config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update GPIO config using a fresh dump of inteltool from the vendor (AMI) firmware on a Librem Mini v2, run through intelp2m with parameters '-p cnl -n -ii' Change-Id: I747415fb9ab7b21943d256d248729cb9e2b4b945 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47206 Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../librem_cnl/variants/librem_mini/gpio.c | 120 +++++++++--------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index 254510ead5..3a48dc57e1 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -38,8 +38,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* GPP_A7 - GPIO */ - /* DW0: 0x44000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_A7, 0, DEEP), + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), /* GPP_A8 - CLKRUN# */ /* DW0: 0x44000700, DW1: 0x00000000 */ @@ -54,7 +54,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* GPP_A11 - GPIO */ - /* DW0: 0x80880201, DW1: 0x00000000 */ + /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_A11, 1, PLTRST), /* GPP_A12 - GPIO */ @@ -74,8 +74,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_A15, 1, PLTRST), /* GPP_A16 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00003000 */ - PAD_CFG_TERM_GPO(GPP_A16, 0, UP_20K, PLTRST), + /* DW0: 0x84000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_A16, 1, UP_20K, PLTRST), /* GPP_A17 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ @@ -115,9 +115,9 @@ static const struct pad_config gpio_table[] = { /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), - /* GPP_B2 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_B2, 1, PLTRST), + /* GPP_B2 - VRALERT# */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* GPP_B3 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ @@ -167,17 +167,17 @@ static const struct pad_config gpio_table[] = { /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_B14, 1, PLTRST), - /* GPP_B15 - GSPI0_CS0# */ - /* DW0: 0x00000701, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B15, NONE, PWROK, NF1), + /* GPP_B15 - GPIO */ + /* DW0: 0x80000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_B15, 1, UP_20K, PLTRST), /* GPP_B16 - GSPI0_CLK */ /* DW0: 0x84000601, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B16, NONE, PLTRST, NF1), /* GPP_B17 - GSPI0_MISO */ - /* DW0: 0x44000502, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* DW0: 0x84000502, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B17, NONE, PLTRST, NF1), /* GPP_B18 - GSPI0_MOSI */ /* DW0: 0x84000601, DW1: 0x00000000 */ @@ -274,8 +274,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_D7, 1, PLTRST), /* GPP_D8 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D8, 0, PLTRST), + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D8, 1, PLTRST), /* GPP_D9 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ @@ -294,16 +294,16 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, NONE), /* GPP_D13 - GPIO */ - /* DW0: 0x04000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D13, 1, RSMRST), + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D13, NONE), /* GPP_D14 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D14, 1, PLTRST), /* GPP_D15 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D15, 1, DEEP), + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* GPP_D16 - GPIO */ /* DW0: 0x04000200, DW1: 0x00000000 */ @@ -352,8 +352,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), /* GPP_F3 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00003000 */ - PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST), + /* DW0: 0x84000300, DW1: 0x00003000 */ + PAD_NC(GPP_F3, UP_20K), /* GPP_F4 - CNV_BRI_DT */ /* DW0: 0x44000700, DW1: 0x00003000 */ @@ -494,20 +494,20 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPP_H14 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H14, 0, PLTRST), + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H14, 1, PLTRST), /* GPP_H15 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H15, 1, PLTRST), /* GPP_H16 - GPIO */ - /* DW0: 0x04000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H16, 1, RSMRST), + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_H16, NONE), /* GPP_H17 - GPIO */ - /* DW0: 0x04000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H17, 1, RSMRST), + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H17, 0, DEEP), /* GPP_H18 - CPU_C10_GATE# */ /* DW0: 0x44000700, DW1: 0x00000000 */ @@ -518,7 +518,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_H19, 1, PLTRST), /* GPP_H20 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: 0x84000300, DW1: 0x00000000 */ PAD_NC(GPP_H20, NONE), /* GPP_H21 - GPIO */ @@ -538,52 +538,52 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPD ------- */ /* GPD0 - BATLOW# */ - /* DW0: 0x04000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* GPD1 - ACPRESENT */ - /* DW0: 0x04000702, DW1: 0x00003c00 */ - PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), /* GPD2 - LAN_WAKE# */ - /* DW0: 0x04000702, DW1: 0x00003c00 */ - PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1), + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPD2, NATIVE, DEEP, NF1), /* GPD3 - PRWBTN# */ - /* DW0: 0x04000702, DW1: 0x00003000 */ - PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), + /* DW0: 0x44000702, DW1: 0x00003000 */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4 - SLP_S3# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), + /* DW0: 0x44000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5 - SLP_S4# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), + /* DW0: 0x44000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6 - SLP_A# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), + /* DW0: 0x44000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* GPD7 - GPIO */ - /* DW0: 0x04000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPD7, 0, RSMRST), + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPD7, 0, DEEP), /* GPD8 - SUSCLK */ - /* DW0: 0x04000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9 - SLP_WLAN# */ - /* DW0: 0x04000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* GPD10 - SLP_S5# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), + /* DW0: 0x44000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* GPD11 - LANPHYPC */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), + /* DW0: 0x44000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* ------- GPIO Community 4 ------- */ @@ -634,8 +634,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_C10, 0, PLTRST), /* GPP_C11 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_C11, 1, PLTRST), + /* DW0: 0x40100103, DW1: 0x00000000 */ + PAD_CFG_GPI_APIC(GPP_C11, NONE, DEEP, LEVEL, NONE), /* GPP_C12 - UART1_RXD */ /* DW0: 0x84000603, DW1: 0x00000000 */ @@ -650,8 +650,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* GPP_C15 - UART1_CTS# */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1), /* GPP_C16 - I2C0_SDA */ /* DW0: 0x84000402, DW1: 0x00000000 */ @@ -776,12 +776,12 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* GPP_E22 - DPPD_CTRLCLK */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E22, NONE, PLTRST, NF1), /* GPP_E23 - DPPD_CTRLDATA */ - /* DW0: 0x44000602, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E23, NONE, PLTRST, NF1), }; const struct pad_config *variant_gpio_table(size_t *num) From 47276639312e742076c2f731c92727f31c26da35 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 3 Nov 2020 13:57:44 -0600 Subject: [PATCH 050/262] mb/purism/librem_mini: Drop community comments in GPIO config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These add nothing useful to the GPIO config Change-Id: Ieecc9bd67d020e141c3a1f1d387034df5e563068 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47190 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../purism/librem_cnl/variants/librem_mini/gpio.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index 3a48dc57e1..283d646fde 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -5,8 +5,6 @@ /* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { - /* ------- GPIO Community 0 ------- */ - /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - RCIN# */ @@ -237,8 +235,6 @@ static const struct pad_config gpio_table[] = { /* DW0: 0x44000300, DW1: 0x00001000 */ PAD_NC(GPP_G7, DN_20K), - /* ------- GPIO Community 1 ------- */ - /* ------- GPIO Group GPP_D ------- */ /* GPP_D0 - GPIO */ @@ -533,8 +529,6 @@ static const struct pad_config gpio_table[] = { /* DW0: 0x44000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H23, 0, DEEP), - /* ------- GPIO Community 2 ------- */ - /* ------- GPIO Group GPD ------- */ /* GPD0 - BATLOW# */ @@ -585,8 +579,6 @@ static const struct pad_config gpio_table[] = { /* DW0: 0x44000600, DW1: 0x00000000 */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), - /* ------- GPIO Community 4 ------- */ - /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - SMBCLK */ From c5381e0f36b49356e965b9f82c5dbe66dc660a86 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 12:56:29 +0100 Subject: [PATCH 051/262] nb/intel/haswell/acpi: Align with Broadwell MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Align cosmetics and move CTDP-specific ASL into its own file. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I476a4e01016caa3658177b0fa8916576f4a5e0e5 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46755 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/acpi/ctdp.asl | 222 ++++++++++++++++ .../intel/haswell/acpi/haswell.asl | 26 +- .../intel/haswell/acpi/hostbridge.asl | 236 +----------------- 3 files changed, 245 insertions(+), 239 deletions(-) create mode 100644 src/northbridge/intel/haswell/acpi/ctdp.asl diff --git a/src/northbridge/intel/haswell/acpi/ctdp.asl b/src/northbridge/intel/haswell/acpi/ctdp.asl new file mode 100644 index 0000000000..7e59fb52ef --- /dev/null +++ b/src/northbridge/intel/haswell/acpi/ctdp.asl @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +//Scope (\_SB.PCI0.MCHC) +//{ + Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ + Name (CTCC, 0) /* CTDP Current Selection */ + Name (CTCN, 0) /* CTDP Nominal Select */ + Name (CTCD, 1) /* CTDP Down Select */ + Name (CTCU, 2) /* CTDP Up Select */ + Name (SPL1, 0) /* Saved PL1 value */ + + OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000) + Field (MCHB, DWordAcc, Lock, Preserve) + { + Offset (0x930), /* PACKAGE_POWER_SKU */ + CTDN, 15, /* CTDP Nominal PL1 */ + Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */ + PUNI, 4, /* Power Units */ + , 4, + EUNI, 5, /* Energy Units */ + , 3, + TUNI, 4, /* Time Units */ + Offset (0x958), /* PLATFORM_INFO */ + , 40, + LFM_, 8, /* Maximum Efficiency Ratio (LFM) */ + Offset (0x9a0), /* TURBO_POWER_LIMIT1 */ + PL1V, 15, /* Power Limit 1 Value */ + PL1E, 1, /* Power Limit 1 Enable */ + PL1C, 1, /* Power Limit 1 Clamp */ + PL1T, 7, /* Power Limit 1 Time */ + Offset (0x9a4), /* TURBO_POWER_LIMIT2 */ + PL2V, 15, /* Power Limit 2 Value */ + PL2E, 1, /* Power Limit 2 Enable */ + PL2C, 1, /* Power Limit 2 Clamp */ + PL2T, 7, /* Power Limit 2 Time */ + Offset (0xf3c), /* CONFIG_TDP_NOMINAL */ + TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ + Offset (0xf40), /* CONFIG_TDP_LEVEL1 */ + CTDD, 15, /* CTDP Down PL1 */ + , 1, + TARD, 8, /* CTDP Down Turbo Activation Ratio */ + Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */ + CTDU, 15, /* CTDP Up PL1 */ + , 1, + TARU, 8, /* CTDP Up Turbo Activation Ratio */ + Offset (0xf50), /* CONFIG_TDP_CONTROL */ + CTCS, 2, /* CTDP Select */ + Offset (0xf54), /* TURBO_ACTIVATION_RATIO */ + TARS, 8, /* Turbo Activation Ratio Select */ + } + + /* + * Search CPU0 _PSS looking for control = arg0 and then + * return previous P-state entry number for new _PPC + * + * Format of _PSS: + * Name (_PSS, Package () { + * Package (6) { freq, power, tlat, blat, control, status } + * } + */ + External (\_SB.CP00._PSS) + Method (PSSS, 1, NotSerialized) + { + Local0 = 1 /* Start at P1 */ + Local1 = SizeOf (\_SB.CP00._PSS) + + While (Local0 < Local1) { + /* Store _PSS entry Control value to Local2 */ + Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 + If (Local2 == Arg0) { + Return (Local0 - 1) + } + Local0++ + } + + Return (0) + } + + /* Calculate PL2 based on chip type */ + Method (CPL2, 1, NotSerialized) + { + If (\ISLP ()) { + /* Haswell ULT PL2 = 25W */ + Return (25 * 8) + } Else { + /* Haswell Mobile PL2 = 1.25 * PL1 */ + Return ((Arg0 * 125) / 100) + } + } + + /* Set Config TDP Down */ + Method (STND, 0, Serialized) + { + If (Acquire (CTCM, 100)) { + Return (0) + } + If (CTCD == CTCC) { + Release (CTCM) + Return (0) + } + + Debug = "Set TDP Down" + + /* Set CTC */ + CTCS = CTCD + + /* Set TAR */ + TARS = TARD + + /* Set PPC limit and notify OS */ + PPCM = PSSS (TARD) + PPCN () + + /* Set PL2 */ + PL2V = CPL2 (CTDD) + + /* Set PL1 */ + PL1V = CTDD + + /* Store the new TDP Down setting */ + CTCC = CTCD + + Release (CTCM) + Return (1) + } + + /* Set Config TDP Nominal from Down */ + Method (STDN, 0, Serialized) + { + If (Acquire (CTCM, 100)) { + Return (0) + } + If (CTCN == CTCC) { + Release (CTCM) + Return (0) + } + + Debug = "Set TDP Nominal" + + /* Set PL1 */ + PL1V = CTDN + + /* Set PL2 */ + PL2V = CPL2 (CTDN) + + /* Set PPC limit and notify OS */ + PPCM = PSSS (TARN) + PPCN () + + /* Set TAR */ + TARS = TARN + + /* Set CTC */ + CTCS = CTCN + + /* Store the new TDP Nominal setting */ + CTCC = CTCN + + Release (CTCM) + Return (1) + } + + /* Calculate PL1 value based on requested TDP */ + Method (TDPP, 1, NotSerialized) + { + Return (((PUNI - 1) << 2) * Arg0) + } + + /* Enable Controllable TDP to limit PL1 to requested value */ + Method (CTLE, 1, Serialized) + { + If (Acquire (CTCM, 100)) { + Return (0) + } + + Debug = "Enable PL1 Limit" + + /* Set _PPC to LFM */ + Local0 = PSSS (LFM_) + PPCM = Local0 + 1 + \PPCN () + + /* Set TAR to LFM-1 */ + TARS = LFM_ - 1 + + /* Set PL1 to desired value */ + SPL1 = PL1V + PL1V = TDPP (Arg0) + + /* Set PL1 CLAMP bit */ + PL1C = 1 + + Release (CTCM) + Return (1) + } + + /* Disable Controllable TDP */ + Method (CTLD, 0, Serialized) + { + If (Acquire (CTCM, 100)) { + Return (0) + } + + Debug = "Disable PL1 Limit" + + /* Clear PL1 CLAMP bit */ + PL1C = 0 + + /* Set PL1 to normal value */ + PL1V = SPL1 + + /* Set TAR to 0 */ + TARS = 0 + + /* Set _PPC to 0 */ + PPCM = 0 + \PPCN () + + Release (CTCM) + Return (1) + } +//} diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 4a9debfd3e..57344abc1d 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -8,28 +8,28 @@ /* PCI Device Resource Consumption */ Device (PDRC) { - Name (_HID, EISAID("PNP0C02")) + Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) - Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) - Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) - Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH - Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH - Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH + Name (PDRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) + Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) + Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) + Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH + Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH + Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH #if CONFIG(CHROMEOS_RAMOOPS) - Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) + Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif }) // Current Resource Settings Method (_CRS, 0, Serialized) { - Return(PDRS) + Return (PDRS) } } diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 1d4eba69ff..f36895d481 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,15 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI +Name (_HID, EISAID ("PNP0A08")) // PCIe +Name (_CID, EISAID ("PNP0A03")) // PCI -Name(_BBN, 0) +Name (_BBN, 0) Device (MCHC) { - Name(_ADR, 0x00000000) // 0:0.0 + Name (_ADR, 0x00000000) // 0:0.0 - OperationRegion(MCHP, PCI_Config, 0x00, 0x100) + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) Field (MCHP, DWordAcc, NoLock, Preserve) { Offset (0x40), // EPBAR @@ -81,223 +81,7 @@ Device (MCHC) TLUD, 32, } - Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ - Name (CTCC, 0) /* CTDP Current Selection */ - Name (CTCN, 0) /* CTDP Nominal Select */ - Name (CTCD, 1) /* CTDP Down Select */ - Name (CTCU, 2) /* CTDP Up Select */ - Name (SPL1, 0) /* Saved PL1 value */ - - OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000) - Field (MCHB, DWordAcc, Lock, Preserve) - { - Offset (0x930), /* PACKAGE_POWER_SKU */ - CTDN, 15, /* CTDP Nominal PL1 */ - Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */ - PUNI, 4, /* Power Units */ - , 4, - EUNI, 5, /* Energy Units */ - , 3, - TUNI, 4, /* Time Units */ - Offset (0x958), /* PLATFORM_INFO */ - , 40, - LFM_, 8, /* Maximum Efficiency Ratio (LFM) */ - Offset (0x9a0), /* TURBO_POWER_LIMIT1 */ - PL1V, 15, /* Power Limit 1 Value */ - PL1E, 1, /* Power Limit 1 Enable */ - PL1C, 1, /* Power Limit 1 Clamp */ - PL1T, 7, /* Power Limit 1 Time */ - Offset (0x9a4), /* TURBO_POWER_LIMIT2 */ - PL2V, 15, /* Power Limit 2 Value */ - PL2E, 1, /* Power Limit 2 Enable */ - PL2C, 1, /* Power Limit 2 Clamp */ - PL2T, 7, /* Power Limit 2 Time */ - Offset (0xf3c), /* CONFIG_TDP_NOMINAL */ - TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ - Offset (0xf40), /* CONFIG_TDP_LEVEL1 */ - CTDD, 15, /* CTDP Down PL1 */ - , 1, - TARD, 8, /* CTDP Down Turbo Activation Ratio */ - Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */ - CTDU, 15, /* CTDP Up PL1 */ - , 1, - TARU, 8, /* CTDP Up Turbo Activation Ratio */ - Offset (0xf50), /* CONFIG_TDP_CONTROL */ - CTCS, 2, /* CTDP Select */ - Offset (0xf54), /* TURBO_ACTIVATION_RATIO */ - TARS, 8, /* Turbo Activation Ratio Select */ - } - - /* - * Search CPU0 _PSS looking for control = arg0 and then - * return previous P-state entry number for new _PPC - * - * Format of _PSS: - * Name (_PSS, Package () { - * Package (6) { freq, power, tlat, blat, control, status } - * } - */ - External (\_SB.CP00._PSS) - Method (PSSS, 1, NotSerialized) - { - Local0 = 1 /* Start at P1 */ - Local1 = SizeOf (\_SB.CP00._PSS) - - While (Local0 < Local1) { - /* Store _PSS entry Control value to Local2 */ - Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 - If (Local2 == Arg0) { - Return (Local0 - 1) - } - Local0++ - } - - Return (0) - } - - /* Calculate PL2 based on chip type */ - Method (CPL2, 1, NotSerialized) - { - If (\ISLP ()) { - /* Haswell ULT PL2 = 25W */ - Return (25 * 8) - } Else { - /* Haswell Mobile PL2 = 1.25 * PL1 */ - Return ((Arg0 * 125) / 100) - } - } - - /* Set Config TDP Down */ - Method (STND, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - If (CTCD == CTCC) { - Release (CTCM) - Return (0) - } - - Debug = "Set TDP Down" - - /* Set CTC */ - CTCS = CTCD - - /* Set TAR */ - TARS = TARD - - /* Set PPC limit and notify OS */ - PPCM = PSSS (TARD) - PPCN () - - /* Set PL2 */ - PL2V = CPL2 (CTDD) - - /* Set PL1 */ - PL1V = CTDD - - /* Store the new TDP Down setting */ - CTCC = CTCD - - Release (CTCM) - Return (1) - } - - /* Set Config TDP Nominal from Down */ - Method (STDN, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - If (CTCN == CTCC) { - Release (CTCM) - Return (0) - } - - Debug = "Set TDP Nominal" - - /* Set PL1 */ - PL1V = CTDN - - /* Set PL2 */ - PL2V = CPL2 (CTDN) - - /* Set PPC limit and notify OS */ - PPCM = PSSS (TARN) - PPCN () - - /* Set TAR */ - TARS = TARN - - /* Set CTC */ - CTCS = CTCN - - /* Store the new TDP Nominal setting */ - CTCC = CTCN - - Release (CTCM) - Return (1) - } - - /* Calculate PL1 value based on requested TDP */ - Method (TDPP, 1, NotSerialized) - { - Return (((PUNI - 1) << 2) * Arg0) - } - - /* Enable Controllable TDP to limit PL1 to requested value */ - Method (CTLE, 1, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - - Debug = "Enable PL1 Limit" - - /* Set _PPC to LFM */ - Local0 = PSSS (LFM_) - PPCM = Local0 + 1 - \PPCN () - - /* Set TAR to LFM-1 */ - TARS = LFM_ - 1 - - /* Set PL1 to desired value */ - SPL1 = PL1V - PL1V = TDPP (Arg0) - - /* Set PL1 CLAMP bit */ - PL1C = 1 - - Release (CTCM) - Return (1) - } - - /* Disable Controllable TDP */ - Method (CTLD, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - - Debug = "Disable PL1 Limit" - - /* Clear PL1 CLAMP bit */ - PL1C = 0 - - /* Set PL1 to normal value */ - PL1V = SPL1 - - /* Set TAR to 0 */ - TARS = 0 - - /* Set _PPC to 0 */ - PPCM = 0 - \PPCN () - - Release (CTCM) - Return (1) - } + #include "ctdp.asl" } // Current Resource Settings @@ -418,9 +202,9 @@ Name (MCRS, ResourceTemplate() Method (_CRS, 0, Serialized) { // Find PCI resource area in MCRS - CreateDwordField(MCRS, ^PM01._MIN, PMIN) - CreateDwordField(MCRS, ^PM01._MAX, PMAX) - CreateDwordField(MCRS, ^PM01._LEN, PLEN) + CreateDwordField (MCRS, ^PM01._MIN, PMIN) + CreateDwordField (MCRS, ^PM01._MAX, PMAX) + CreateDwordField (MCRS, ^PM01._LEN, PLEN) // Fix up PCI memory region // Start with Top of Lower Usable DRAM @@ -439,7 +223,7 @@ Method (_CRS, 0, Serialized) PMIN = Local0 PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 - PLEN = PMAX - PMIN + 1 + PLEN = (PMAX - PMIN) + 1 Return (MCRS) } From f239b5a9f35faac861c8efd28d32c458e45cc890 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 12:58:32 +0100 Subject: [PATCH 052/262] nb/intel/haswell: Place CTDP ASL code in a separate scope MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is just to align the code with what Broadwell does. Change-Id: I52fb1546d049ca9fa09d0c54304ca1d79f6c4c3e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46756 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/acpi/ctdp.asl | 6 +++--- src/northbridge/intel/haswell/acpi/hostbridge.asl | 5 +++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/haswell/acpi/ctdp.asl b/src/northbridge/intel/haswell/acpi/ctdp.asl index 7e59fb52ef..84c0f2f20a 100644 --- a/src/northbridge/intel/haswell/acpi/ctdp.asl +++ b/src/northbridge/intel/haswell/acpi/ctdp.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -//Scope (\_SB.PCI0.MCHC) -//{ +Scope (\_SB.PCI0.MCHC) +{ Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ Name (CTCC, 0) /* CTDP Current Selection */ Name (CTCN, 0) /* CTDP Nominal Select */ @@ -219,4 +219,4 @@ Release (CTCM) Return (1) } -//} +} diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index f36895d481..dc3a36fc95 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -80,8 +80,6 @@ Device (MCHC) Offset (0xbc), // Top of Low Used Memory TLUD, 32, } - - #include "ctdp.asl" } // Current Resource Settings @@ -227,3 +225,6 @@ Method (_CRS, 0, Serialized) Return (MCRS) } + +/* Configurable TDP */ +#include "ctdp.asl" From 0d8924d880ff22d074d760925413bc4ddfb6cd82 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 13:11:46 +0100 Subject: [PATCH 053/262] soc/intel/broadwell: Align ACPI with Haswell/Lynxpoint MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop unnecessary smbus.asl in favor of southbridge common code. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change. Change-Id: I13b35d2155a2cede0a56846b8bf8a79d4ebfc7b3 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46757 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/acpi/ctdp.asl | 80 ++++++++++---------- src/soc/intel/broadwell/acpi/systemagent.asl | 8 +- src/soc/intel/broadwell/pch/acpi/lpc.asl | 4 +- src/soc/intel/broadwell/pch/acpi/pch.asl | 2 +- src/soc/intel/broadwell/pch/acpi/smbus.asl | 8 -- 5 files changed, 46 insertions(+), 56 deletions(-) delete mode 100644 src/soc/intel/broadwell/pch/acpi/smbus.asl diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl index 83914826f2..b18ec78ecd 100644 --- a/src/soc/intel/broadwell/acpi/ctdp.asl +++ b/src/soc/intel/broadwell/acpi/ctdp.asl @@ -9,8 +9,7 @@ Scope (\_SB.PCI0.MCHC) Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */ - OperationRegion (MCHB, SystemMemory, - Add (MCH_BASE_ADDRESS, 0x5000), 0x1000) + OperationRegion (MCHB, SystemMemory, MCH_BASE_ADDRESS + 0x5000, 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ @@ -51,7 +50,7 @@ Scope (\_SB.PCI0.MCHC) } /* - * Search CPU0 _PSS looking for control=arg0 and then + * Search CPU0 _PSS looking for control = arg0 and then * return previous P-state entry number for new _PPC * * Format of _PSS: @@ -62,17 +61,16 @@ Scope (\_SB.PCI0.MCHC) External (\_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { - Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_SB.CP00._PSS), Local1) + Local0 = 1 /* Start at P1 */ + Local1 = SizeOf (\_SB.CP00._PSS) - While (LLess (Local0, Local1)) { + While (Local0 < Local1) { /* Store _PSS entry Control value to Local2 */ - ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_SB.CP00._PSS, Local0)), 4)), 8, Local2) - If (LEqual (Local2, Arg0)) { - Return (Subtract (Local0, 1)) + Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 + If (Local2 == Arg0) { + Return (Local0 - 1) } - Increment (Local0) + Local0++ } Return (0) @@ -83,7 +81,7 @@ Scope (\_SB.PCI0.MCHC) { /* Haswell ULT PL2 = 25W */ /* FIXME: update for broadwell */ - Return (Multiply (25, 8)) + Return (25 * 8) } /* Set Config TDP Down */ @@ -92,31 +90,31 @@ Scope (\_SB.PCI0.MCHC) If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCD, CTCC)) { + If (CTCD == CTCC) { Release (CTCM) Return (0) } - Store ("Set TDP Down", Debug) + Debug = "Set TDP Down" /* Set CTC */ - Store (CTCD, CTCS) + CTCS = CTCD /* Set TAR */ - Store (TARD, TARS) + TARS = TARD /* Set PPC limit and notify OS */ - Store (PSSS (TARD), PPCM) + PPCM = PSSS (TARD) PPCN () /* Set PL2 */ - Store (CPL2 (CTDD), PL2V) + PL2V = CPL2 (CTDD) /* Set PL1 */ - Store (CTDD, PL1V) + PL1V = CTDD /* Store the new TDP Down setting */ - Store (CTCD, CTCC) + CTCC = CTCD Release (CTCM) Return (1) @@ -128,31 +126,31 @@ Scope (\_SB.PCI0.MCHC) If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCN, CTCC)) { + If (CTCN == CTCC) { Release (CTCM) Return (0) } - Store ("Set TDP Nominal", Debug) + Debug = "Set TDP Nominal" /* Set PL1 */ - Store (CTDN, PL1V) + PL1V = CTDN /* Set PL2 */ - Store (CPL2 (CTDN), PL2V) + PL2V = CPL2 (CTDN) /* Set PPC limit and notify OS */ - Store (PSSS (TARN), PPCM) + PPCM = PSSS (TARN) PPCN () /* Set TAR */ - Store (TARN, TARS) + TARS = TARN /* Set CTC */ - Store (CTCN, CTCS) + CTCS = CTCN /* Store the new TDP Nominal setting */ - Store (CTCN, CTCC) + CTCC = CTCN Release (CTCM) Return (1) @@ -161,7 +159,7 @@ Scope (\_SB.PCI0.MCHC) /* Calculate PL1 value based on requested TDP */ Method (TDPP, 1, NotSerialized) { - Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0)) + Return (((PUNI - 1) << 2) * Arg0) } /* Enable Controllable TDP to limit PL1 to requested value */ @@ -171,22 +169,22 @@ Scope (\_SB.PCI0.MCHC) Return (0) } - Store ("Enable PL1 Limit", Debug) + Debug = "Enable PL1 Limit" /* Set _PPC to LFM */ - Store (PSSS (LFM_), Local0) - Add (Local0, 1, PPCM) + Local0 = PSSS (LFM_) + PPCM = Local0 + 1 \PPCN () /* Set TAR to LFM-1 */ - Subtract (LFM_, 1, TARS) + TARS = LFM_ - 1 /* Set PL1 to desired value */ - Store (PL1V, SPL1) - Store (TDPP (Arg0), PL1V) + SPL1 = PL1V + PL1V = TDPP (Arg0) /* Set PL1 CLAMP bit */ - Store (One, PL1C) + PL1C = 1 Release (CTCM) Return (1) @@ -199,19 +197,19 @@ Scope (\_SB.PCI0.MCHC) Return (0) } - Store ("Disable PL1 Limit", Debug) + Debug = "Disable PL1 Limit" /* Clear PL1 CLAMP bit */ - Store (Zero, PL1C) + PL1C = 0 /* Set PL1 to normal value */ - Store (SPL1, PL1V) + PL1V = SPL1 /* Set TAR to 0 */ - Store (Zero, TARS) + TARS = 0 /* Set _PPC to 0 */ - Store (Zero, PPCM) + PPCM = 0 \PPCN () Release (CTCM) diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/soc/intel/broadwell/acpi/systemagent.asl index 258e6e7e7a..3e7ced0296 100644 --- a/src/soc/intel/broadwell/acpi/systemagent.asl +++ b/src/soc/intel/broadwell/acpi/systemagent.asl @@ -141,9 +141,9 @@ Name (MCRS, ResourceTemplate() Method (_CRS, 0, Serialized) { // Find PCI resource area in MCRS - CreateDwordField(MCRS, ^PM01._MIN, PMIN) - CreateDwordField(MCRS, ^PM01._MAX, PMAX) - CreateDwordField(MCRS, ^PM01._LEN, PLEN) + CreateDwordField (MCRS, ^PM01._MIN, PMIN) + CreateDwordField (MCRS, ^PM01._MAX, PMAX) + CreateDwordField (MCRS, ^PM01._LEN, PLEN) // Fix up PCI memory region // Start with Top of Lower Usable DRAM @@ -170,7 +170,7 @@ Method (_CRS, 0, Serialized) /* PCI Device Resource Consumption */ Device (PDRC) { - Name (_HID, EISAID("PNP0C02")) + Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) Name (PDRS, ResourceTemplate() { diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl index 5bdfea24ce..4422907f88 100644 --- a/src/soc/intel/broadwell/pch/acpi/lpc.asl +++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl @@ -181,6 +181,6 @@ Device (LPCB) #include "gpio.asl" #include "irqlinks.asl" - #include - #include + #include "acpi/ec.asl" + #include "acpi/superio.asl" } diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl index 07db9f7f24..5a94bca181 100644 --- a/src/soc/intel/broadwell/pch/acpi/pch.asl +++ b/src/soc/intel/broadwell/pch/acpi/pch.asl @@ -60,7 +60,7 @@ Scope (\) #include "sata.asl" // SMBus 0:1f.3 -#include "smbus.asl" +#include // Serial IO #include "serialio.asl" diff --git a/src/soc/intel/broadwell/pch/acpi/smbus.asl b/src/soc/intel/broadwell/pch/acpi/smbus.asl deleted file mode 100644 index 32b0b9cc62..0000000000 --- a/src/soc/intel/broadwell/pch/acpi/smbus.asl +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -// Intel SMBus Controller 0:1f.3 - -Device (SBUS) -{ - Name (_ADR, 0x001f0003) -} From 284b39f9c838c74571885ce6c8ef20fcb1d8e9f6 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 13:14:46 +0100 Subject: [PATCH 054/262] soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 2e1f764 (sb/intel/common/acpi/irqlinks.asl: Add missing IRQs) added these IRQs for Lynx Point and earlier southbridges. Follow suit for Broadwell, since it also supports them. Vendor firmware of the Asus X555LAB laptop also contains these IRQs, as per the disassembled DSDT. Change-Id: If857352dd25ba61c1f09c1ff4358efafdc3a5c73 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46758 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/pch/acpi/irqlinks.asl | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/broadwell/pch/acpi/irqlinks.asl b/src/soc/intel/broadwell/pch/acpi/irqlinks.asl index 0661ff8fce..8a63ba5f9d 100644 --- a/src/soc/intel/broadwell/pch/acpi/irqlinks.asl +++ b/src/soc/intel/broadwell/pch/acpi/irqlinks.asl @@ -15,7 +15,7 @@ Device (LNKA) Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link @@ -74,7 +74,7 @@ Device (LNKB) Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link @@ -133,7 +133,7 @@ Device (LNKC) Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link @@ -192,7 +192,7 @@ Device (LNKD) Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link @@ -251,7 +251,7 @@ Device (LNKE) Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link @@ -310,7 +310,7 @@ Device (LNKF) Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link @@ -369,7 +369,7 @@ Device (LNKG) Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link @@ -428,7 +428,7 @@ Device (LNKH) Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link From eeefb022ebd5052c948bd2c942ef67905acc2435 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 13:21:25 +0100 Subject: [PATCH 055/262] soc/intel/broadwell: Use common irqlinks.asl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I9179c1b449925cc66628fc3266652b8237ab49e5 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46759 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/pch/acpi/irqlinks.asl | 473 ------------------ src/soc/intel/broadwell/pch/acpi/lpc.asl | 2 +- 2 files changed, 1 insertion(+), 474 deletions(-) delete mode 100644 src/soc/intel/broadwell/pch/acpi/irqlinks.asl diff --git a/src/soc/intel/broadwell/pch/acpi/irqlinks.asl b/src/soc/intel/broadwell/pch/acpi/irqlinks.asl deleted file mode 100644 index 8a63ba5f9d..0000000000 --- a/src/soc/intel/broadwell/pch/acpi/irqlinks.asl +++ /dev/null @@ -1,473 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device (LNKA) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 1) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTA) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLA, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLA, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTA - ShiftLeft (1, And (PRTA, 0x0f), IRQ0) - - Return (RTLA) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTA) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTA, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKB) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 2) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTB) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLB, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLB, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTB - ShiftLeft (1, And (PRTB, 0x0f), IRQ0) - - Return (RTLB) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTB) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTB, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKC) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 3) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTC) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLC, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLC, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTC - ShiftLeft (1, And (PRTC, 0x0f), IRQ0) - - Return (RTLC) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTC) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTC, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKD) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 4) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTD) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLD, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLD, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTD - ShiftLeft (1, And (PRTD, 0x0f), IRQ0) - - Return (RTLD) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTD) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTD, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKE) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 5) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTE) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLE, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLE, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTE - ShiftLeft (1, And (PRTE, 0x0f), IRQ0) - - Return (RTLE) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTE) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTE, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKF) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 6) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTF) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLF, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLF, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTF - ShiftLeft (1, And (PRTF, 0x0f), IRQ0) - - Return (RTLF) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTF) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTF, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKG) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 7) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTG) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLG, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLG, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTG - ShiftLeft (1, And (PRTG, 0x0f), IRQ0) - - Return (RTLG) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTG) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTG, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKH) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 8) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTH) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLH, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLH, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTH - ShiftLeft (1, And (PRTH, 0x0f), IRQ0) - - Return (RTLH) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTH) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTH, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl index 4422907f88..01e1bebaf9 100644 --- a/src/soc/intel/broadwell/pch/acpi/lpc.asl +++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl @@ -180,7 +180,7 @@ Device (LPCB) } #include "gpio.asl" - #include "irqlinks.asl" + #include #include "acpi/ec.asl" #include "acpi/superio.asl" } From f1e81e6eb969cde5a48c69dcb44365c77b9b8419 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 13:29:12 +0100 Subject: [PATCH 056/262] sb/intel/common/acpi/irqlinks.asl: Clean up cosmetics MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I8562fc3278144380b0ab842d88176114821be823 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46760 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../intel/common/acpi/irqlinks.asl | 176 +++++++++--------- 1 file changed, 88 insertions(+), 88 deletions(-) diff --git a/src/southbridge/intel/common/acpi/irqlinks.asl b/src/southbridge/intel/common/acpi/irqlinks.asl index 3f3386d908..54c6989ff6 100644 --- a/src/southbridge/intel/common/acpi/irqlinks.asl +++ b/src/southbridge/intel/common/acpi/irqlinks.asl @@ -8,13 +8,13 @@ Device (LNKA) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTA) + PRTA = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -23,15 +23,15 @@ Device (LNKA) { Name (RTLA, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLA, 1, IRQ0) + CreateWordField (RTLA, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTA - ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + IRQ0 = 1 << (PRTA & 0x0f) Return (RTLA) } @@ -39,19 +39,19 @@ Device (LNKA) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTA) + Local0-- + PRTA = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTA, 0x80)) { + If (PRTA & 0x80) { Return (0x9) } Else { Return (0xb) @@ -67,13 +67,13 @@ Device (LNKB) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTB) + PRTB = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -82,15 +82,15 @@ Device (LNKB) { Name (RTLB, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLB, 1, IRQ0) + CreateWordField (RTLB, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTB - ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + IRQ0 = 1 << (PRTB & 0x0f) Return (RTLB) } @@ -98,19 +98,19 @@ Device (LNKB) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTB) + Local0-- + PRTB = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTB, 0x80)) { + If (PRTB & 0x80) { Return (0x9) } Else { Return (0xb) @@ -126,13 +126,13 @@ Device (LNKC) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTC) + PRTC = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -141,15 +141,15 @@ Device (LNKC) { Name (RTLC, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLC, 1, IRQ0) + CreateWordField (RTLC, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTC - ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + IRQ0 = 1 << (PRTC & 0x0f) Return (RTLC) } @@ -157,19 +157,19 @@ Device (LNKC) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTC) + Local0-- + PRTC = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTC, 0x80)) { + If (PRTC & 0x80) { Return (0x9) } Else { Return (0xb) @@ -185,13 +185,13 @@ Device (LNKD) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTD) + PRTD = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -200,15 +200,15 @@ Device (LNKD) { Name (RTLD, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLD, 1, IRQ0) + CreateWordField (RTLD, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTD - ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + IRQ0 = 1 << (PRTD & 0x0f) Return (RTLD) } @@ -216,19 +216,19 @@ Device (LNKD) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTD) + Local0-- + PRTD = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTD, 0x80)) { + If (PRTD & 0x80) { Return (0x9) } Else { Return (0xb) @@ -244,13 +244,13 @@ Device (LNKE) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTE) + PRTE = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -259,15 +259,15 @@ Device (LNKE) { Name (RTLE, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLE, 1, IRQ0) + CreateWordField (RTLE, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTE - ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + IRQ0 = 1 << (PRTE & 0x0f) Return (RTLE) } @@ -275,19 +275,19 @@ Device (LNKE) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTE) + Local0-- + PRTE = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTE, 0x80)) { + If (PRTE & 0x80) { Return (0x9) } Else { Return (0xb) @@ -303,13 +303,13 @@ Device (LNKF) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTF) + PRTF = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -318,15 +318,15 @@ Device (LNKF) { Name (RTLF, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLF, 1, IRQ0) + CreateWordField (RTLF, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTF - ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + IRQ0 = 1 << (PRTF & 0x0f) Return (RTLF) } @@ -334,19 +334,19 @@ Device (LNKF) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTF) + Local0-- + PRTF = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTF, 0x80)) { + If (PRTF & 0x80) { Return (0x9) } Else { Return (0xb) @@ -362,13 +362,13 @@ Device (LNKG) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTG) + PRTG = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -377,15 +377,15 @@ Device (LNKG) { Name (RTLG, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLG, 1, IRQ0) + CreateWordField (RTLG, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTG - ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + IRQ0 = 1 << (PRTG & 0x0f) Return (RTLG) } @@ -393,19 +393,19 @@ Device (LNKG) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTG) + Local0-- + PRTG = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTG, 0x80)) { + If (PRTG & 0x80) { Return (0x9) } Else { Return (0xb) @@ -421,13 +421,13 @@ Device (LNKH) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTH) + PRTH = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -436,15 +436,15 @@ Device (LNKH) { Name (RTLH, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLH, 1, IRQ0) + CreateWordField (RTLH, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTH - ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + IRQ0 = 1 << (PRTH & 0x0f) Return (RTLH) } @@ -452,19 +452,19 @@ Device (LNKH) // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTH) + Local0-- + PRTH = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTH, 0x80)) { + If (PRTH & 0x80) { Return (0x9) } Else { Return (0xb) From 2ac4cc65955833fc48d44302cef26b6fd17341c2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 13:35:36 +0100 Subject: [PATCH 057/262] sb/intel/common/acpi/pcie.asl: Generalise file comment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This file is no longer specific to 6 and 7 series PCHs. Change-Id: Ib89378bd6ba1d80281b92a79d37b9fdeaaed40fb Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46762 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/southbridge/intel/common/acpi/pcie.asl | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/southbridge/intel/common/acpi/pcie.asl b/src/southbridge/intel/common/acpi/pcie.asl index 8f496d38d8..c1bfcfda27 100644 --- a/src/southbridge/intel/common/acpi/pcie.asl +++ b/src/southbridge/intel/common/acpi/pcie.asl @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Intel 6/7 Series PCH PCIe support */ - -// PCI Express Ports +/* Intel southbridge PCIe support */ Method (IRQM, 1, Serialized) { From 257b00f3575ccf7853061d75fbb4f0b362a88b36 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 02:49:29 +0200 Subject: [PATCH 058/262] soc/intel/broadwell/gma.c: Align struct with Haswell MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ifd1fb02497e1d326b6b9c5752f471f52b145a8ef Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46732 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber --- src/soc/intel/broadwell/gma.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index 3889be3513..d42eebc4f1 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -588,12 +588,12 @@ static void gma_generate_ssdt(const struct device *dev) } static struct device_operations igd_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = &igd_init, - .ops_pci = &pci_dev_ops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = igd_init, .acpi_fill_ssdt = gma_generate_ssdt, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { From fcc26f54a0dc5db0845946b20e1a03b77a8877ae Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 13:32:46 +0100 Subject: [PATCH 059/262] soc/intel/broadwell/pch/acpi: Add PCIe register offsets These are present in common southbridge ACPI code, and also exist on Broadwell. Thus, add the definitions to align with common ACPI code. Change-Id: Ib0ad9da80920fe7c70986e541c50f6adccb49d0c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46761 Reviewed-by: Nico Huber Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/pch/acpi/pcie_port.asl | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl index d48ecd036e..988c8170e9 100644 --- a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl +++ b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl @@ -8,4 +8,10 @@ Field (RPCS, AnyAcc, NoLock, Preserve) Offset (0x4c), // Link Capabilities , 24, RPPN, 8, // Root Port Number + Offset (0x5A), + , 3, + PDC, 1, + Offset (0xDF), + , 6, + HPCS, 1, } From 34c0b26193ea9424a7eaba4d0a4ab2d5925c2f91 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 13:38:00 +0100 Subject: [PATCH 060/262] soc/intel/broadwell/pch: Use common PCIe ACPI code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change. Change-Id: I1f41ce943e25dceab79c7d7ee2ed797c392dcd52 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46763 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/pch/acpi/pch.asl | 2 +- src/soc/intel/broadwell/pch/acpi/pcie.asl | 196 ------------------ .../intel/broadwell/pch/acpi/pcie_port.asl | 17 -- 3 files changed, 1 insertion(+), 214 deletions(-) delete mode 100644 src/soc/intel/broadwell/pch/acpi/pcie.asl delete mode 100644 src/soc/intel/broadwell/pch/acpi/pcie_port.asl diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl index 5a94bca181..7b57859672 100644 --- a/src/soc/intel/broadwell/pch/acpi/pch.asl +++ b/src/soc/intel/broadwell/pch/acpi/pch.asl @@ -45,7 +45,7 @@ Scope (\) #include "adsp.asl" // PCI Express Ports 0:1c.x -#include "pcie.asl" +#include // USB EHCI 0:1d.0 #include "ehci.asl" diff --git a/src/soc/intel/broadwell/pch/acpi/pcie.asl b/src/soc/intel/broadwell/pch/acpi/pcie.asl deleted file mode 100644 index 72993f9372..0000000000 --- a/src/soc/intel/broadwell/pch/acpi/pcie.asl +++ /dev/null @@ -1,196 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel PCH PCIe support */ - -Method (IRQM, 1, Serialized) { - - /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ - Name (IQAA, Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } }) - Name (IQAP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) - - /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ - Name (IQBA, Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } }) - Name (IQBP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } }) - - /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ - Name (IQCA, Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } }) - Name (IQCP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } }) - - /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ - Name (IQDA, Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } }) - Name (IQDP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } }) - - Switch (ToInteger (Arg0)) { - /* PCIe Root Port 1 and 5 */ - Case (Package() { 1, 5 }) { - If (PICM) { - Return (IQAA) - } Else { - Return (IQAP) - } - } - - /* PCIe Root Port 2 and 6 */ - Case (Package() { 2, 6 }) { - If (PICM) { - Return (IQBA) - } Else { - Return (IQBP) - } - } - - /* PCIe Root Port 3 and 7 */ - Case (Package() { 3, 7 }) { - If (PICM) { - Return (IQCA) - } Else { - Return (IQCP) - } - } - - /* PCIe Root Port 4 and 8 */ - Case (Package() { 4, 8 }) { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - - Default { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - } -} - -Device (RP01) -{ - Name (_ADR, 0x001c0000) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001c0001) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001c0002) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001c0003) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001c0004) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001c0005) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001c0006) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001c0007) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} diff --git a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl deleted file mode 100644 index 988c8170e9..0000000000 --- a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Included in each PCIe Root Port device */ - -OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) -Field (RPCS, AnyAcc, NoLock, Preserve) -{ - Offset (0x4c), // Link Capabilities - , 24, - RPPN, 8, // Root Port Number - Offset (0x5A), - , 3, - PDC, 1, - Offset (0xDF), - , 6, - HPCS, 1, -} From 9f8e92bae32129883bc1e16ef40915963bf4b17b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 13:49:09 +0100 Subject: [PATCH 061/262] sb/intel/lynxpoint: Expose full LPC device ID in ACPI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is merely to align ACPI files with Broadwell. It is unused. Change-Id: I8aa297bd3c3734bbd438ff84742aadfc661adcf7 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46764 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/acpi/lpc.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index bc1d73cddf..0e8bad3f72 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -9,8 +9,8 @@ Device (LPCB) OperationRegion(LPC0, PCI_Config, 0x00, 0x100) Field (LPC0, AnyAcc, NoLock, Preserve) { - Offset (0x3), - DIDH, 8, // Device ID High Byte + Offset (0x02), + PDID, 16, // Device ID Offset (0x40), PMBS, 16, // PMBASE Offset (0x48), From a42d37ac3f8bf5ffdfa7f2d3416d35769b65dc3b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 13:54:38 +0100 Subject: [PATCH 062/262] sb/intel/*/acpi/lpc.asl: Drop unnecessary RCBA offset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Nothing should be using this offset. Change-Id: Ia4736471e2ac53bec18bfe073f4aa49e3fc524a8 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46765 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/southbridge/intel/bd82x6x/acpi/lpc.asl | 5 ----- src/southbridge/intel/i82801gx/acpi/lpc.asl | 5 ----- src/southbridge/intel/i82801ix/acpi/lpc.asl | 5 ----- src/southbridge/intel/i82801jx/acpi/lpc.asl | 5 ----- src/southbridge/intel/lynxpoint/acpi/lpc.asl | 5 ----- 5 files changed, 25 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl index 85e8d24490..7dd9623e16 100644 --- a/src/southbridge/intel/bd82x6x/acpi/lpc.asl +++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl @@ -43,11 +43,6 @@ Device (LPCB) GR13, 2, GR14, 2, GR15, 2, - - Offset (0xf0), // RCBA - RCEN, 1, - , 13, - RCBA, 18, } #include diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index 1f9e701e84..ab6ffae95d 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -25,11 +25,6 @@ Device (LPCB) Offset (0x80), // IO Decode Ranges IOD0, 8, IOD1, 8, - - Offset (0xf0), // RCBA - RCEN, 1, - , 13, - RCBA, 18, } #include diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl index b93fa96d23..c351c531ad 100644 --- a/src/southbridge/intel/i82801ix/acpi/lpc.asl +++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl @@ -25,11 +25,6 @@ Device (LPCB) Offset (0x80), // IO Decode Ranges IOD0, 8, IOD1, 8, - - Offset (0xf0), // RCBA - RCEN, 1, - , 13, - RCBA, 18, } #include diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl index b93fa96d23..c351c531ad 100644 --- a/src/southbridge/intel/i82801jx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl @@ -25,11 +25,6 @@ Device (LPCB) Offset (0x80), // IO Decode Ranges IOD0, 8, IOD1, 8, - - Offset (0xf0), // RCBA - RCEN, 1, - , 13, - RCBA, 18, } #include diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index 0e8bad3f72..b95c2f06b1 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -29,11 +29,6 @@ Device (LPCB) Offset (0x80), // IO Decode Ranges IOD0, 8, IOD1, 8, - - Offset (0xf0), // RCBA - RCEN, 1, - , 13, - RCBA, 18, } #include From 040f3be59e592311bf7d8f658b2cca1189d62f2c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 14:01:06 +0100 Subject: [PATCH 063/262] soc/intel/broadwell: Include EC and IRQ links ACPI early MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Other southbridges such as Lynx Point do it. This eases merging later. Change-Id: I10196bbc44ce859c2747755845378351f45944ae Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46766 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/pch/acpi/lpc.asl | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl index 01e1bebaf9..0af85e62cc 100644 --- a/src/soc/intel/broadwell/pch/acpi/lpc.asl +++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl @@ -31,6 +31,10 @@ Device (LPCB) IOD1, 8, } + #include + + #include "acpi/ec.asl" + Device (DMAC) // DMA Controller { Name (_HID, EISAID("PNP0200")) @@ -180,7 +184,5 @@ Device (LPCB) } #include "gpio.asl" - #include - #include "acpi/ec.asl" #include "acpi/superio.asl" } From aacabd0bd634f53d43cc5bde8ae4170d7b47144b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 18:26:00 +0100 Subject: [PATCH 064/262] soc/intel/broadwell: Merge `device_nvs.asl` into `globalnvs.asl` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change. Change-Id: If5f1feb0cd43fe1e0514b4e3fa766da60e2b7603 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46773 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../intel/broadwell/pch/acpi/device_nvs.asl | 37 ------------------- .../intel/broadwell/pch/acpi/globalnvs.asl | 34 ++++++++++++++++- 2 files changed, 32 insertions(+), 39 deletions(-) delete mode 100644 src/soc/intel/broadwell/pch/acpi/device_nvs.asl diff --git a/src/soc/intel/broadwell/pch/acpi/device_nvs.asl b/src/soc/intel/broadwell/pch/acpi/device_nvs.asl deleted file mode 100644 index 76cdafc3c0..0000000000 --- a/src/soc/intel/broadwell/pch/acpi/device_nvs.asl +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Device Enabled in ACPI Mode */ - -S0EN, 8, // DMA Enable -S1EN, 8, // I2C0 Enable -S2EN, 8, // I2C1 Enable -S3EN, 8, // SPI0 Enable -S4EN, 8, // SPI1 Enable -S5EN, 8, // UART0 Enable -S6EN, 8, // UART1 Enable -S7EN, 8, // SDIO Enable -S8EN, 8, // ADSP Enable - -/* BAR 0 */ - -S0B0, 32, // DMA BAR0 -S1B0, 32, // I2C0 BAR0 -S2B0, 32, // I2C1 BAR0 -S3B0, 32, // SPI0 BAR0 -S4B0, 32, // SPI1 BAR0 -S5B0, 32, // UART0 BAR0 -S6B0, 32, // UART1 BAR0 -S7B0, 32, // SDIO BAR0 -S8B0, 32, // ADSP BAR0 - -/* BAR 1 */ - -S0B1, 32, // DMA BAR1 -S1B1, 32, // I2C0 BAR1 -S2B1, 32, // I2C1 BAR1 -S3B1, 32, // SPI0 BAR1 -S4B1, 32, // SPI1 BAR1 -S5B1, 32, // UART0 BAR1 -S6B1, 32, // UART1 BAR1 -S7B1, 32, // SDIO BAR1 -S8B1, 32, // ADSP BAR1 diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl index 3c6c5f5998..15f69dd09f 100644 --- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl @@ -49,9 +49,39 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0x100), #include - /* Device specific */ Offset (0x1000), - #include "device_nvs.asl" + /* Device enables in ACPI mode */ + S0EN, 8, // DMA Enable + S1EN, 8, // I2C0 Enable + S2EN, 8, // I2C1 Enable + S3EN, 8, // SPI0 Enable + S4EN, 8, // SPI1 Enable + S5EN, 8, // UART0 Enable + S6EN, 8, // UART1 Enable + S7EN, 8, // SDIO Enable + S8EN, 8, // ADSP Enable + + /* BAR 0 */ + S0B0, 32, // DMA BAR0 + S1B0, 32, // I2C0 BAR0 + S2B0, 32, // I2C1 BAR0 + S3B0, 32, // SPI0 BAR0 + S4B0, 32, // SPI1 BAR0 + S5B0, 32, // UART0 BAR0 + S6B0, 32, // UART1 BAR0 + S7B0, 32, // SDIO BAR0 + S8B0, 32, // ADSP BAR0 + + /* BAR 1 */ + S0B1, 32, // DMA BAR1 + S1B1, 32, // I2C0 BAR1 + S2B1, 32, // I2C1 BAR1 + S3B1, 32, // SPI0 BAR1 + S4B1, 32, // SPI1 BAR1 + S5B1, 32, // UART0 BAR1 + S6B1, 32, // UART1 BAR1 + S7B1, 32, // SDIO BAR1 + S8B1, 32, // ADSP BAR1 } /* Set flag to enable USB charging in S3 */ From b0d342028ddbc47e8b21d43d47c48be3066c350a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 18:45:45 +0100 Subject: [PATCH 065/262] sb/intel/lynxpoint/acpi: Put together LP GPIO code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename `lpt_lp.asl` and place all Lynxpoint-LP GPIO ASL there. It has been named `gpio.asl` to ease diffs between Lynxpoint and Broadwell. Tested with BUILD_TIMELESS=1, Google Panther does not change. Change-Id: I7cc4ab3371014be783761f110542471a8c0157a3 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46774 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../lynxpoint/acpi/{lpt_lp.asl => gpio.asl} | 53 ++++++++++++++++++- src/southbridge/intel/lynxpoint/acpi/pch.asl | 2 +- .../intel/lynxpoint/acpi/serialio.asl | 53 ------------------- 3 files changed, 53 insertions(+), 55 deletions(-) rename src/southbridge/intel/lynxpoint/acpi/{lpt_lp.asl => gpio.asl} (60%) diff --git a/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl b/src/southbridge/intel/lynxpoint/acpi/gpio.asl similarity index 60% rename from src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl rename to src/southbridge/intel/lynxpoint/acpi/gpio.asl index b258900a36..3650b701e3 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl +++ b/src/southbridge/intel/lynxpoint/acpi/gpio.asl @@ -1,6 +1,57 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* LynxPoint-H */ +Device (GPIO) +{ + // GPIO Controller + Name (_HID, "INT33C7") + Name (_CID, "INT33C7") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate() + { + DWordIo (ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + EntireRange, // ISARanges + 0x00000000, // AddressGranularity + 0x00000000, // AddressMinimum + 0x00000000, // AddressMaximum + 0x00000000, // AddressTranslation + 0x00000001, // RangeLength + , // ResourceSourceIndex + , // ResourceSource + BAR0) + // Disabled due to IRQ storm: http://crosbug.com/p/29548 + //Interrupt (ResourceConsumer, + // Level, ActiveHigh, Shared, , , ) {14} + }) + + Method (_CRS, 0, NotSerialized) + { + If (\ISLP ()) { + CreateDwordField (^RBUF, ^BAR0._MIN, BMIN) + CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) + CreateDwordField (^RBUF, ^BAR0._LEN, BLEN) + + Store (DEFAULT_GPIOSIZE, BLEN) + Store (DEFAULT_GPIOBASE, BMIN) + Store (Subtract (Add (DEFAULT_GPIOBASE, + DEFAULT_GPIOSIZE), 1), BMAX) + } + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + If (\ISLP ()) { + Return (0xF) + } Else { + Return (0x0) + } + } +} Scope (\_SB.PCI0.LPCB) { diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index bace058387..5ac83a4ae7 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -76,7 +76,7 @@ Scope (\) // Serial IO #if CONFIG(INTEL_LYNXPOINT_LP) #include "serialio.asl" -#include "lpt_lp.asl" +#include "gpio.asl" #endif Method (_OSC, 4) diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 8956563cd9..164b623584 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -510,56 +510,3 @@ Device (SDIO) } } } - -Device (GPIO) -{ - // GPIO Controller - Name (_HID, "INT33C7") - Name (_CID, "INT33C7") - Name (_UID, 1) - - Name (RBUF, ResourceTemplate() - { - DWordIo (ResourceProducer, - MinFixed, // IsMinFixed - MaxFixed, // IsMaxFixed - PosDecode, // Decode - EntireRange, // ISARanges - 0x00000000, // AddressGranularity - 0x00000000, // AddressMinimum - 0x00000000, // AddressMaximum - 0x00000000, // AddressTranslation - 0x00000001, // RangeLength - , // ResourceSourceIndex - , // ResourceSource - BAR0) - // Disabled due to IRQ storm: http://crosbug.com/p/29548 - //Interrupt (ResourceConsumer, - // Level, ActiveHigh, Shared, , , ) {14} - }) - - Method (_CRS, 0, NotSerialized) - { - If (\ISLP ()) { - CreateDwordField (^RBUF, ^BAR0._MIN, BMIN) - CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) - CreateDwordField (^RBUF, ^BAR0._LEN, BLEN) - - Store (DEFAULT_GPIOSIZE, BLEN) - Store (DEFAULT_GPIOBASE, BMIN) - Store (Subtract (Add (DEFAULT_GPIOBASE, - DEFAULT_GPIOSIZE), 1), BMAX) - } - - Return (RBUF) - } - - Method (_STA, 0, NotSerialized) - { - If (\ISLP ()) { - Return (0xF) - } Else { - Return (0x0) - } - } -} From df7a887cb56b8e8f4a6734b2a2cca96517587bfa Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 19:24:44 +0100 Subject: [PATCH 066/262] sb/intel/lynxpoint: Align LP GPIO ACPI with Broadwell MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the `GWAK` method into the GPIO device, and have lpc.c include the LP GPIO code. All usages of `GWAK` on mainboards need to be updated. Change-Id: Id6a41f553d133f960de8b232205ed43b832a83d2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46775 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/google/beltino/acpi/mainboard.asl | 4 ++-- .../variants/falco/include/variant/acpi/mainboard.asl | 2 +- .../slippy/variants/leon/include/variant/acpi/mainboard.asl | 2 +- .../variants/peppy/include/variant/acpi/mainboard.asl | 6 +++--- .../slippy/variants/wolf/include/variant/acpi/mainboard.asl | 2 +- src/southbridge/intel/lynxpoint/acpi/gpio.asl | 3 --- src/southbridge/intel/lynxpoint/acpi/lpc.asl | 3 +++ src/southbridge/intel/lynxpoint/acpi/pch.asl | 1 - 8 files changed, 11 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/beltino/acpi/mainboard.asl b/src/mainboard/google/beltino/acpi/mainboard.asl index 10696ff9fc..f6adb63ca5 100644 --- a/src/mainboard/google/beltino/acpi/mainboard.asl +++ b/src/mainboard/google/beltino/acpi/mainboard.asl @@ -18,7 +18,7 @@ Scope (\_SB.PCI0.RP01) If (Arg0 == 1) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } } @@ -40,7 +40,7 @@ Scope (\_SB.PCI0.RP02) If (Arg0 == 1) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } } diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl index d395a317ed..0ee0eb0796 100644 --- a/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl @@ -40,7 +40,7 @@ Scope (\_SB.PCI0.I2C0) Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) If (LEqual (Arg0, 1)) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl index bf4adfdcbf..e149559a6a 100644 --- a/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl @@ -40,7 +40,7 @@ Scope (\_SB.PCI0.I2C0) Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) If (LEqual (Arg0, 1)) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl index 8bbb19a2ed..babf9a0a37 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl @@ -40,7 +40,7 @@ Scope (\_SB.PCI0.I2C0) Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) If (LEqual (Arg0, 1)) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } } @@ -82,7 +82,7 @@ Scope (\_SB.PCI0.I2C0) Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) If (LEqual (Arg0, 1)) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } @@ -122,7 +122,7 @@ Scope (\_SB.PCI0.I2C1) Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) If (LEqual (Arg0, 1)) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl index bf4adfdcbf..e149559a6a 100644 --- a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl @@ -40,7 +40,7 @@ Scope (\_SB.PCI0.I2C0) Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) If (LEqual (Arg0, 1)) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } } diff --git a/src/southbridge/intel/lynxpoint/acpi/gpio.asl b/src/southbridge/intel/lynxpoint/acpi/gpio.asl index 3650b701e3..1eefcdd197 100644 --- a/src/southbridge/intel/lynxpoint/acpi/gpio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/gpio.asl @@ -51,10 +51,7 @@ Device (GPIO) Return (0x0) } } -} -Scope (\_SB.PCI0.LPCB) -{ // GWAK: Setup GPIO as ACPI GPE for Wake // Arg0: GPIO Number Method (GWAK, 1, NotSerialized) diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index b95c2f06b1..8410d7ab39 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -199,5 +199,8 @@ Device (LPCB) }) } +#if CONFIG(INTEL_LYNXPOINT_LP) + #include "gpio.asl" +#endif #include "acpi/superio.asl" } diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index 5ac83a4ae7..a3c81887e7 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -76,7 +76,6 @@ Scope (\) // Serial IO #if CONFIG(INTEL_LYNXPOINT_LP) #include "serialio.asl" -#include "gpio.asl" #endif Method (_OSC, 4) From 527647677a8da418bf4854eada32d9090393ee5f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 19:44:16 +0100 Subject: [PATCH 067/262] sb/intel/lynxpoint/acpi/gpio.asl: Simplify constants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only LPT-LP includes this file, so `ISLP` is effectively constant. Thus, eliminate some unnecessary if-blocks, since only one branch gets taken. Change-Id: Ie8ba787bf5c021845e1e47256a6303697aa97fe1 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46776 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/acpi/gpio.asl | 20 +++++++------------ 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/gpio.asl b/src/southbridge/intel/lynxpoint/acpi/gpio.asl index 1eefcdd197..7f30307cab 100644 --- a/src/southbridge/intel/lynxpoint/acpi/gpio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/gpio.asl @@ -29,27 +29,21 @@ Device (GPIO) Method (_CRS, 0, NotSerialized) { - If (\ISLP ()) { - CreateDwordField (^RBUF, ^BAR0._MIN, BMIN) - CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) - CreateDwordField (^RBUF, ^BAR0._LEN, BLEN) + CreateDwordField (^RBUF, ^BAR0._MIN, BMIN) + CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) + CreateDwordField (^RBUF, ^BAR0._LEN, BLEN) - Store (DEFAULT_GPIOSIZE, BLEN) - Store (DEFAULT_GPIOBASE, BMIN) - Store (Subtract (Add (DEFAULT_GPIOBASE, + Store (DEFAULT_GPIOSIZE, BLEN) + Store (DEFAULT_GPIOBASE, BMIN) + Store (Subtract (Add (DEFAULT_GPIOBASE, DEFAULT_GPIOSIZE), 1), BMAX) - } Return (RBUF) } Method (_STA, 0, NotSerialized) { - If (\ISLP ()) { - Return (0xF) - } Else { - Return (0x0) - } + Return (0xF) } // GWAK: Setup GPIO as ACPI GPE for Wake From 5725ee4f9f056b4ea62efe205d823a6132b56971 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 21 Oct 2020 00:23:29 +0200 Subject: [PATCH 068/262] sec/intel/txt: Add support for running SCLEAN in romstage SCLEAN has specific requirements and needs to run in early romstage, since the DRAM would be locked when SCLEAN needs to be executed. Change-Id: I77b237342e0c98eda974f87944f1948d197714db Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46607 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/security/intel/txt/Makefile.inc | 2 + src/security/intel/txt/getsec_sclean.S | 181 +++++++++++++++++++++++++ src/security/intel/txt/txt_getsec.h | 3 + 3 files changed, 186 insertions(+) create mode 100644 src/security/intel/txt/getsec_sclean.S diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index 712ab589d5..762256f6e3 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -1,5 +1,7 @@ ifeq ($(CONFIG_INTEL_TXT),y) +romstage-y += getsec_sclean.S + romstage-y += common.c romstage-$(CONFIG_INTEL_TXT_LOGGING) += logging.c diff --git a/src/security/intel/txt/getsec_sclean.S b/src/security/intel/txt/getsec_sclean.S new file mode 100644 index 0000000000..e240a2faaa --- /dev/null +++ b/src/security/intel/txt/getsec_sclean.S @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include "getsec_mtrr_setup.inc" + +#define MTRR_HIGH_MASK $((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1) + +#define NO_EVICT_MODE 0x2e0 + +.align 4 +.text + +/* + * void getsec_sclean(const uint32_t acm_base, const uint32_t acm_size); + */ +.global getsec_sclean +getsec_sclean: + /* + * At this point, it is certain that the BIOS ACM will be run. + * This requires tearing down CAR, which cannot be undone. + * + * From here onwards, the only way out is to reset the system. + */ + + /* Enable SMXE, SSE and debug extensions */ + movl %cr4, %eax + orl $(CR4_OSFXSR | CR4_DE | CR4_SMXE), %eax + movl %eax, %cr4 + + /* + * Save arguments into SSE registers. We need to tear down CAR + * before launching the BIOS ACM, which will destroy the stack. + */ + movd 4(%esp), %xmm2 /* acm_base */ + movd 8(%esp), %xmm3 /* acm_size */ + + /* Disable cache */ + movl %cr0, %eax + orl $(CR0_CD | CR0_NE), %eax + andl $(~(CR0_NW)), %eax + movl %eax, %cr0 + + /* Invalidate the cache */ + invd + + /* Disable MTRRs */ + movl $(MTRR_DEF_TYPE_MSR), %ecx + xorl %eax, %eax + xorl %edx, %edx + wrmsr + + /* Disable NEM, needs to be done in two steps */ + movl $NO_EVICT_MODE, %ecx + rdmsr + andl $~2, %eax /* Clear NEM Run bit */ + wrmsr + andl $~1, %eax /* Clear NEM Setup bit */ + wrmsr + + /* Invalidate the cache, again */ + invd + + /* + * Clear variable MTRRs + * Chapter 2.2.5.1 + * Intel TXT Software Development Guide (Document: 315168-015) + */ + movl $(MTRR_CAP_MSR), %ecx + rdmsr + andl $(0xff), %eax + movl %eax, %ebx + + xorl %eax, %eax + xorl %edx, %edx + + jmp cond_clear_var_mtrrs + +body_clear_var_mtrrs: + + decl %ebx + movl %ebx, %ecx + shll %ecx + addl $(MTRR_PHYS_BASE(0)), %ecx + wrmsr + incl %ecx /* MTRR_PHYS_MASK */ + wrmsr + +cond_clear_var_mtrrs: + + cmpl $0, %ebx + jnz body_clear_var_mtrrs + + /* + * Setup BIOS ACM as WB + * Chapter A.1.1 + * Intel TXT Software Development Guide (Document: 315168-015) + */ + + /* Determine size of AC module */ + movd %xmm2, %eax /* acm_base */ + movd %xmm3, %ebx /* acm_size */ + + /* Round up to page size */ + addl $(0xfff), %ebx + andl $(~0xfff), %ebx /* Aligned to a page (4 KiB) */ + + /* Use SSE registers to store local variables */ + movd %eax, %xmm0 + movd %ebx, %xmm1 + + /* + * Important note: The MTRRs must cache less than a page (4 KiB) + * of unused memory after the BIOS ACM. Not doing so on Haswell + * will cause a TXT reset with Class Code 5, Major Error Code 2. + * + * The caller must have checked that there are enough variable + * MTRRs to cache the ACM size prior to invoking this routine. + */ + SET_UP_MTRRS_FOR_BIOS_ACM + + /* Enable variable MTRRs */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + orl $MTRR_DEF_TYPE_EN, %eax + wrmsr + + /* Enable cache - CR0_NW is and stays clear */ + movl %cr0, %eax + andl $~(CR0_CD), %eax + movl %eax, %cr0 + + /* + * Get function arguments. + * It's important to pass the exact ACM size as it's used by getsec to verify + * the integrity of ACM. Unlike the size for MTRR programming, which needs to + * be power of two. + * + * Note: Do not forget that CAR has been torn down, so the stack doesn't exist. + */ + movl $2, %eax /* GETSEC[ENTERACCS] */ + movd %xmm2, %ebx /* acm_base */ + movd %xmm3, %ecx /* acm_size */ + movl $0, %edx /* reserved, must be zero */ + movl $0, %edi /* must be zero */ + movl $0, %esi /* SCLEAN */ + + getsec + + /* + * The platform state after SCLEAN is undefined. The only sane + * thing to do afterwards is to reset the platform. Note that + * the BIOS ACM should already reset the platform, so this code + * may not always be reached, but keep it here just to be sure. + */ +#if 1 + movw $0xcf8, %dx + movl $0x8000F8AC, %eax + outl %eax, %dx + + movw $0xcfc, %dx + inl %dx, %eax + andl $~(1 << 20), %eax + outl %eax, %dx +#endif + + movw $0xcf9, %dx + movb $0, %al + outb %al, %dx + + movw $0xcf9, %dx + movb $0x0e, %al + outb %al, %dx + + cli + + hlt + + ret diff --git a/src/security/intel/txt/txt_getsec.h b/src/security/intel/txt/txt_getsec.h index 78171a7d5a..f949c7d361 100644 --- a/src/security/intel/txt/txt_getsec.h +++ b/src/security/intel/txt/txt_getsec.h @@ -20,4 +20,7 @@ void getsec_enteraccs(const uint32_t esi, const uint32_t acm_base, const uint32_t acm_size); +void getsec_sclean(const uint32_t acm_base, + const uint32_t acm_size); + #endif /* SECURITY_INTEL_TXT_REGISTER_H_ */ From 35597435d023150d847ec11019cb19cba29397bf Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 1 Nov 2020 22:39:15 +0100 Subject: [PATCH 069/262] mb/purism/librem_cnl: Set SaGv to FixedHigh Since the Librem Mini does not run on battery power, SaGv has little benefits and noticeably slows down testing, since memory training is run twice. Disabling SaGv cuts the 30-second cold boot time in half. Change-Id: Ib02e42dcb4f20fdbdca85456c0dceafc59c782d8 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47082 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- .../purism/librem_cnl/variants/librem_mini/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 9fde5e97da..918fa0ef0e 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -15,7 +15,7 @@ chip soc/intel/cannonlake register "eist_enable" = "1" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "SaGv" = "SaGv_Enabled" + register "SaGv" = "SaGv_FixedHigh" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) From 6c49f40b6e6342b7acb47cb0a57fa10269e3d4c9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 28 Aug 2020 02:02:00 +0200 Subject: [PATCH 070/262] haswell: Add Intel TXT support in romstage Provide necessary romstage hooks to allow unblocking the memory with SCLEAN. Note that this is slow, and took four minutes with 4 GiB of RAM. Tested on Asrock B85M Pro4 with tboot. When Linux has tboot support compiled in, booting as well as S3 suspend and resume are functional. However, SINIT will TXT reset when the iGPU is enabled, and using a dGPU will result in DMAR-related problems as soon as the IOMMU is enabled. However, SCLEAN seems to hang sometimes. This may be because the AP initialization that reference code does before SCLEAN is missing, but the ACM is still able to unblock the memory. Considering that SCLEAN is critical to recover an otherwise-bricked platform but is hardly ever necessary, prefer having a partially-working solution over none at all. Change-Id: I60beb7d79a30f460bbd5d94e4cba0244318c124e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46608 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/haswell/romstage.c | 18 ++++ src/security/intel/txt/Makefile.inc | 2 + src/security/intel/txt/common.c | 42 ++++++++ src/security/intel/txt/romstage.c | 125 +++++++++++++++++++++++ src/security/intel/txt/txt.h | 3 + src/security/intel/txt/txt_register.h | 10 ++ 6 files changed, 200 insertions(+) create mode 100644 src/security/intel/txt/romstage.c diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 5b025eba24..3227c02287 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -4,11 +4,14 @@ #include #include #include +#include #include #include #include #include #include +#include +#include #include #include #include @@ -108,12 +111,27 @@ void mainboard_romstage_entry(void) report_platform_info(); + if (CONFIG(INTEL_TXT)) + intel_txt_romstage_init(); + copy_spd(&pei_data); sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); + if (CONFIG(INTEL_TXT)) { + printk(BIOS_DEBUG, "Check TXT_ERROR register after MRC\n"); + + intel_txt_log_acm_error(read32((void *)TXT_ERROR)); + + intel_txt_log_spad(); + + intel_txt_memory_has_secrets(); + + txt_dump_regions(); + } + post_code(0x3b); intel_early_me_status(); diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index 762256f6e3..eab47b95f9 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -1,6 +1,8 @@ ifeq ($(CONFIG_INTEL_TXT),y) +romstage-y += romstage.c romstage-y += getsec_sclean.S +romstage-y += getsec.c romstage-y += common.c romstage-$(CONFIG_INTEL_TXT_LOGGING) += logging.c diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 88e2b5dddb..4dd4ad3ddf 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -290,6 +290,48 @@ static void *intel_txt_prepare_bios_acm(struct region_device *acm, size_t *acm_l return acm_data; } +#define MCU_BASE_ADDR (TXT_BASE + 0x278) +#define BIOACM_ADDR (TXT_BASE + 0x27c) +#define APINIT_ADDR (TXT_BASE + 0x290) +#define SEMAPHORE (TXT_BASE + 0x294) + +/* Returns on failure, resets the computer on success */ +void intel_txt_run_sclean(void) +{ + struct region_device acm; + size_t acm_len; + + void *acm_data = intel_txt_prepare_bios_acm(&acm, &acm_len); + + if (!acm_data) + return; + + /* FIXME: Do we need to program these two? */ + //write32((void *)MCU_BASE_ADDR, 0xffe1a990); + //write32((void *)APINIT_ADDR, 0xfffffff0); + + write32((void *)BIOACM_ADDR, (uintptr_t)acm_data); + write32((void *)SEMAPHORE, 0); + + /* + * The time SCLEAN will take depends on the installed RAM size. + * On Haswell with 8 GiB of DDR3, it takes five or ten minutes. (rough estimate) + */ + printk(BIOS_ALERT, "TEE-TXT: Invoking SCLEAN. This can take several minutes.\n"); + + /* + * Invoke the BIOS ACM. If successful, the system will reset with memory unlocked. + */ + getsec_sclean((uintptr_t)acm_data, acm_len); + + /* + * However, if this function returns, the BIOS ACM could not be invoked. This is bad. + */ + printk(BIOS_CRIT, "TEE-TXT: getsec_sclean could not launch the BIOS ACM.\n"); + + rdev_munmap(&acm, acm_data); +} + /* * Test all bits for TXT execution. * diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c new file mode 100644 index 0000000000..7a12debd6d --- /dev/null +++ b/src/security/intel/txt/romstage.c @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "txt.h" +#include "txt_register.h" +#include "txt_getsec.h" + +static bool is_establishment_bit_asserted(void) +{ + struct stopwatch timer; + uint8_t access; + + /* Spec says no less than 30 milliseconds */ + stopwatch_init_msecs_expire(&timer, 50); + + while (true) { + access = read8((void *)TPM_ACCESS_REG); + + /* Register returns all ones if TPM is missing */ + if (access == 0xff) + return false; + + if (access & TPM_ACCESS_VALID) + break; + + /* On timeout, assume that the TPM is not working */ + if (stopwatch_expired(&timer)) + return false; + } + + /* This bit uses inverted logic: if cleared, establishment is asserted */ + return !(access & TPM_ACCESS_ESTABLISHMENT); +} + +static bool is_txt_cpu(void) +{ + const uint32_t ecx = cpu_get_feature_flags_ecx(); + + return (ecx & (CPUID_SMX | CPUID_VMX)) == (CPUID_SMX | CPUID_VMX); +} + +static bool is_txt_chipset(void) +{ + uint32_t eax; + + const bool success = getsec_capabilities(&eax); + + return success && eax & 1; +} + +/* Print the bad news */ +static void print_memory_is_locked(void) +{ + if (!CONFIG(INTEL_TXT_LOGGING)) + return; + + printk(BIOS_EMERG, "FATAL: Cannot run SCLEAN. Memory will remain locked.\n"); + printk(BIOS_EMERG, "\n"); + printk(BIOS_EMERG, "If you still want to boot, your options are:\n"); + printk(BIOS_EMERG, "\n"); + printk(BIOS_EMERG, " 1. Flash a coreboot image with a valid BIOS ACM.\n"); + printk(BIOS_EMERG, " Then, try again and hope it works this time.\n"); + printk(BIOS_EMERG, "\n"); + printk(BIOS_EMERG, " 2. If possible, remove the TPM from the system.\n"); + printk(BIOS_EMERG, " Reinstalling the TPM might lock memory again.\n"); + printk(BIOS_EMERG, "\n"); + printk(BIOS_EMERG, " 3. Disconnect all power sources, and RTC battery.\n"); + printk(BIOS_EMERG, " This may not work on all TXT-enabled platforms.\n"); + printk(BIOS_EMERG, "\n"); +} + +void intel_txt_romstage_init(void) +{ + /* Bail early if the CPU doesn't support TXT */ + if (!is_txt_cpu()) + return; + + /* We need to use GETSEC here, so enable it */ + enable_getsec_or_reset(); + + if (!is_txt_chipset()) + return; + + const uint8_t txt_ests = read8((void *)TXT_ESTS); + + const bool establishment = is_establishment_bit_asserted(); + const bool is_wake_error = !!(txt_ests & TXT_ESTS_WAKE_ERROR_STS); + + if (CONFIG(INTEL_TXT_LOGGING)) { + + printk(BIOS_INFO, "TEE-TXT: TPM established: %s\n", + establishment ? "true" : "false"); + } + + if (establishment && is_wake_error) { + + printk(BIOS_ERR, "TEE-TXT: Secrets remain in memory. SCLEAN is required.\n"); + + if (txt_ests & TXT_ESTS_TXT_RESET_STS) { + printk(BIOS_ERR, "TEE-TXT: TXT_RESET bit set, doing full reset!\n"); + full_reset(); + } + + /* FIXME: Clear SLP_TYP# */ + write_pmbase32(4, read_pmbase32(4) & ~(0x7 << 10)); + + intel_txt_run_sclean(); + + /* If running the BIOS ACM is impossible, manual intervention is required */ + print_memory_is_locked(); + + /* FIXME: vboot A/B could be used to recover, but has not been tested */ + die("Could not execute BIOS ACM to unlock the memory.\n"); + } +} diff --git a/src/security/intel/txt/txt.h b/src/security/intel/txt/txt.h index fc5c49e67e..976cc7458e 100644 --- a/src/security/intel/txt/txt.h +++ b/src/security/intel/txt/txt.h @@ -17,10 +17,13 @@ #define ACM_E_UUID_NOT_MATCH 0x09 #define ACM_E_PLATFORM_IS_NOT_PROD 0x10 +void intel_txt_romstage_init(void); + void intel_txt_log_bios_acm_error(void); int intel_txt_log_acm_error(const uint32_t acm_error); void intel_txt_log_spad(void); bool intel_txt_memory_has_secrets(void); +void intel_txt_run_sclean(void); int intel_txt_run_bios_acm(const u8 input_params); bool intel_txt_prepare_txt_env(void); diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h index c19ec13799..bb735b6cfd 100644 --- a/src/security/intel/txt/txt_register.h +++ b/src/security/intel/txt/txt_register.h @@ -98,6 +98,16 @@ #define TXT_E2STS (TXT_BASE + 0x8f0) #define TXT_E2STS_SECRET_STS (1ull << 1) +/* + * TCG PC Client Platform TPM Profile (PTP) Specification + * + * Note: Only locality 0 registers are publicly accessible. + */ + +#define TPM_BASE 0xfed40000UL + +#define TPM_ACCESS_REG (TPM_BASE + 0x00) + /* * TXT Memory regions * Chapter 5.3 From 1410224cf476ed5e666deffcbbc455055632add1 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 22 Oct 2020 14:13:14 +0200 Subject: [PATCH 071/262] soc/intel/xeon_sp: Use common cpu/intel romstage entry This removes some boilerplate like starting the console and also adds a "start of romstage" timestamp. Change-Id: Ie85df5d244fa37c41f0b3177ca325c607fa54593 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/46658 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/Kconfig | 1 + src/soc/intel/xeon_sp/Makefile.inc | 1 + src/soc/intel/xeon_sp/memmap.c | 21 +++++++++++++++++++++ src/soc/intel/xeon_sp/romstage.c | 25 +------------------------ 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index a83a3c3572..3d3e8037db 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -55,6 +55,7 @@ config CPU_SPECIFIC_OPTIONS select MICROCODE_BLOB_NOT_HOOKED_UP select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_CAR + select NO_SMM config MAINBOARD_USES_FSP2_0 bool diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 07fe3debb4..a10075ab04 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -7,6 +7,7 @@ subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c +romstage-y += ../../../cpu/intel/car/romstage.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c chip_common.c ramstage-y += memmap.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index 79ab47eaed..edc62cf881 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include #include #include #include @@ -20,3 +23,21 @@ void smm_region(uintptr_t *start, size_t *size) *start = tseg_base; *size = tseg_limit - tseg_base; } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + top_of_ram -= 16 * MiB; + postcar_frame_add_mtrr(pcf, top_of_ram, 16 * MiB, MTRR_TYPE_WRBACK); + /* Cache the TSEG region */ + if (CONFIG(TSEG_STAGE_CACHE)) + postcar_enable_tseg_cache(pcf); +} diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index f3e32fd9ca..2540c5c291 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include #include #include #include @@ -9,14 +8,8 @@ #include #include -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { - struct postcar_frame pcf; - uintptr_t top_of_ram; - - printk(BIOS_DEBUG, "FSP TempRamInit was successful...\n"); - - console_init(); rtc_init(); if (soc_get_rtc_failed()) mainboard_rtc_failed(); @@ -26,23 +19,7 @@ asmlinkage void car_stage_entry(void) unlock_pam_regions(); - if (postcar_frame_init(&pcf, 1 * KiB)) - die("Unable to initialize postcar frame.\n"); - - /* - * We need to make sure ramstage will be run cached. At this point exact - * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t)cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram: 0x%lx\n", top_of_ram); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB, - MTRR_TYPE_WRBACK); - - /* Cache the memory-mapped boot media. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); save_dimm_info(); - run_postcar_phase(&pcf); } __weak void mainboard_memory_init_params(FSPM_UPD *mupd) From 70296654825ddf5dfbe4980f385e8617c009a97e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 28 Oct 2020 13:50:19 +0530 Subject: [PATCH 072/262] mb/intel/adlrvp: Add support for DDR5 memory This patch adds DDR5 memory configuration parameters to FSP. TEST=Able to build and boot ADLRVP with DDR5 memory. Change-Id: I4711d66c7b4b7b09e15a4d06e28c876ec35bc192 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46485 Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/intel/adlrvp/romstage_fsp_params.c | 5 +++-- .../intel/adlrvp/variants/adlrvp_p/memory.c | 16 ++++++++++++++++ .../baseboard/include/baseboard/variants.h | 2 ++ 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 209ee6a222..672c59743e 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -36,7 +36,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) .spd_spec.spd_index = get_spd_index(), }; - const struct spd_info ddr4_spd_info = { + const struct spd_info ddr4_ddr5_spd_info = { .read_type = READ_SMBUS, .spd_spec = { .spd_smbus_address = { @@ -51,7 +51,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) switch (board_id) { case ADL_P_DDR4_1: case ADL_P_DDR4_2: - memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated); + case ADL_P_DDR5: + memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_ddr5_spd_info, half_populated); break; case ADL_P_LP4_1: case ADL_P_LP4_2: diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c index c730b995bc..ec7ae88135 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c @@ -54,6 +54,20 @@ static const struct mb_cfg lpddr4_mem_config = { .UserBd = BOARD_TYPE_MOBILE, }; +static const struct mb_cfg ddr5_mem_config = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* Baseboard Rcomp target values */ + .rcomp_targets = {50, 30, 30, 30, 27}, + + .dq_pins_interleaved = true, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + const struct mb_cfg *variant_memory_params(void) { int board_id = get_board_id(); @@ -62,6 +76,8 @@ const struct mb_cfg *variant_memory_params(void) return &lpddr4_mem_config; else if (board_id == ADL_P_DDR4_1 || board_id == ADL_P_DDR4_2) return &ddr4_mem_config; + else if (board_id == ADL_P_DDR5) + return &ddr5_mem_config; die("unsupported board id : 0x%x\n", board_id); } diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h index 005ec83a56..537e62451a 100644 --- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h @@ -12,6 +12,8 @@ enum adl_boardid { /* ADL-P LPDDR4 RVPs */ ADL_P_LP4_1 = 0x10, ADL_P_LP4_2 = 0x11, + /* ADL-P DDR5 RVPs */ + ADL_P_DDR5 = 0x12, /* ADL-P DDR4 RVPs */ ADL_P_DDR4_1 = 0x14, ADL_P_DDR4_2 = 0x3F, From 6b495bcf1610a26ed9c7c0ec36a360c324b2e9b1 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 4 Nov 2020 00:35:57 -0600 Subject: [PATCH 073/262] mb/purism/librem_mini: Drop DW0/DW1 from GPIO config comments MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are generated by inteltool + intelp2m and reflect the pad configuration of the vendor (AMI) firmware at a specific point in time, but do not always reflect the correct configuration of a given pad as per the schematics, so drop them. Change-Id: Ie337cca5bc0e87a5426cceae8d7ec29ab14a1729 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47200 Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../librem_cnl/variants/librem_mini/gpio.c | 188 ------------------ 1 file changed, 188 deletions(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index 283d646fde..4c735c5168 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -8,771 +8,583 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - RCIN# */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* GPP_A1 - LAD0 */ - /* DW0: 0x44000702, DW1: 0x00003c00 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* GPP_A2 - LAD1 */ - /* DW0: 0x44000702, DW1: 0x00003c00 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* GPP_A3 - LAD2 */ - /* DW0: 0x44000702, DW1: 0x00003c00 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* GPP_A4 - LAD3 */ - /* DW0: 0x44000702, DW1: 0x00003c00 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* GPP_A5 - LFRAME# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* GPP_A6 - SERIRQ */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* GPP_A7 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_A7, 1, DEEP), /* GPP_A8 - CLKRUN# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - /* DW0: 0x44000700, DW1: 0x00001000 */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* GPP_A10 - CLKOUT_LPC1 */ - /* DW0: 0x44000700, DW1: 0x00001000 */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* GPP_A11 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_A11, 1, PLTRST), /* GPP_A12 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_A12, 1, PLTRST), /* GPP_A13 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_A13, 1, PLTRST), /* GPP_A14 - SUS_STAT# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* GPP_A15 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_A15, 1, PLTRST), /* GPP_A16 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00003000 */ PAD_CFG_TERM_GPO(GPP_A16, 1, UP_20K, PLTRST), /* GPP_A17 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_A17, 1, PLTRST), /* GPP_A18 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_A18, UP_20K), /* GPP_A19 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_A19, UP_20K), /* GPP_A20 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_A20, UP_20K), /* GPP_A21 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_A21, UP_20K), /* GPP_A22 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_A22, UP_20K), /* GPP_A23 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_A23, UP_20K), /* ------- GPIO Group GPP_B ------- */ /* GPP_B0 - Reserved */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* GPP_B1 - Reserved */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* GPP_B2 - VRALERT# */ - /* DW0: 0x84000603, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* GPP_B3 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_B3, 1, PLTRST), /* GPP_B4 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* GPP_B5 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_B5, NONE), /* GPP_B6 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_B6, NONE), /* GPP_B7 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_B7, NONE), /* GPP_B8 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_B8, NONE), /* GPP_B9 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_B9, NONE), /* GPP_B10 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_B10, NONE), /* GPP_B11 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_B11, 1, PLTRST), /* GPP_B12 - SLP_S0# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13 - PLTRST# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* GPP_B14 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_B14, 1, PLTRST), /* GPP_B15 - GPIO */ - /* DW0: 0x80000201, DW1: 0x00003000 */ PAD_CFG_TERM_GPO(GPP_B15, 1, UP_20K, PLTRST), /* GPP_B16 - GSPI0_CLK */ - /* DW0: 0x84000601, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B16, NONE, PLTRST, NF1), /* GPP_B17 - GSPI0_MISO */ - /* DW0: 0x84000502, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B17, NONE, PLTRST, NF1), /* GPP_B18 - GSPI0_MOSI */ - /* DW0: 0x84000601, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1), /* GPP_B19 - GSPI1_CS0# */ - /* DW0: 0x84000400, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B19, NONE, PLTRST, NF1), /* GPP_B20 - GSPI1_CLK */ - /* DW0: 0x84000400, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B20, NONE, PLTRST, NF1), /* GPP_B21 - GSPI1_MISO */ - /* DW0: 0x84000402, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B21, NONE, PLTRST, NF1), /* GPP_B22 - GSPI1_MOSI */ - /* DW0: 0x84000400, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B22, NONE, PLTRST, NF1), /* GPP_B23 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_B23, 1, DEEP), /* ------- GPIO Group GPP_G ------- */ /* GPP_G0 - GPIO */ - /* DW0: 0x04000200, DW1: 0x00001000 */ PAD_CFG_TERM_GPO(GPP_G0, 0, DN_20K, PWROK), /* GPP_G1 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_G1, NONE), /* GPP_G2 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_G2, NONE), /* GPP_G3 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_G3, NONE), /* GPP_G4 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_G4, NONE), /* GPP_G5 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_G5, UP_20K), /* GPP_G6 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_G6, NONE), /* GPP_G7 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00001000 */ PAD_NC(GPP_G7, DN_20K), /* ------- GPIO Group GPP_D ------- */ /* GPP_D0 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D0, NONE), /* GPP_D1 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D1, NONE), /* GPP_D2 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D2, NONE), /* GPP_D3 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D3, NONE), /* GPP_D4 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D4, NONE), /* GPP_D5 - ISH_I2C0_SDA */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* GPP_D6 - ISH_I2C0_SCL */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* GPP_D7 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D7, 1, PLTRST), /* GPP_D8 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D8, 1, PLTRST), /* GPP_D9 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D9, 1, PLTRST), /* GPP_D10 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D10, 1, PLTRST), /* GPP_D11 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00003000 */ PAD_CFG_TERM_GPO(GPP_D11, 1, UP_20K, DEEP), /* GPP_D12 - GPIO */ - /* DW0: 0x42100102, DW1: 0x00003000 */ PAD_CFG_GPI_APIC(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, NONE), /* GPP_D13 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D13, NONE), /* GPP_D14 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D14, 1, PLTRST), /* GPP_D15 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* GPP_D16 - GPIO */ - /* DW0: 0x04000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D16, 0, RSMRST), /* GPP_D17 - DMIC_CLK1 */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* GPP_D18 - DMIC_DATA1 */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* GPP_D19 - DMIC_CLK0 */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* GPP_D20 - DMIC_DATA0 */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* GPP_D21 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D21, NONE), /* GPP_D22 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D22, NONE), /* GPP_D23 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D23, NONE), /* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - GPIO */ - /* DW0: 0x00000301, DW1: 0x00000000 */ PAD_NC(GPP_F0, NONE), /* GPP_F1 - GPIO */ - /* DW0: 0x04000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_F1, 0, RSMRST), /* GPP_F2 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00003000 */ PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), /* GPP_F3 - GPIO */ - /* DW0: 0x84000300, DW1: 0x00003000 */ PAD_NC(GPP_F3, UP_20K), /* GPP_F4 - CNV_BRI_DT */ - /* DW0: 0x44000700, DW1: 0x00003000 */ PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1), /* GPP_F5 - CNV_BRI_RSP */ - /* DW0: 0x44000702, DW1: 0x00003000 */ PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), /* GPP_F6 - CNV_RGI_DT */ - /* DW0: 0x44000700, DW1: 0x00003000 */ PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1), /* GPP_F7 - CNV_RGI_RSP */ - /* DW0: 0x44000702, DW1: 0x00003000 */ PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), /* GPP_F8 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F8, NONE), /* GPP_F9 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F9, NONE), /* GPP_F10 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_F10, 1, PLTRST), /* GPP_F11 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F11, NONE), /* GPP_F12 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F12, NONE), /* GPP_F13 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F13, NONE), /* GPP_F14 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F14, NONE), /* GPP_F15 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F15, NONE), /* GPP_F16 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F16, NONE), /* GPP_F17 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F17, NONE), /* GPP_F18 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F18, NONE), /* GPP_F19 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F19, NONE), /* GPP_F20 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F20, NONE), /* GPP_F21 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F21, NONE), /* GPP_F22 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F22, NONE), /* GPP_F23 - A4WP_PRESENT */ - /* DW0: 0x44000700, DW1: 0x00001000 */ PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1), /* ------- GPIO Group GPP_H ------- */ /* GPP_H0 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_H0, UP_20K), /* GPP_H1 - CNV_RF_RESET# */ - /* DW0: 0x44000f00, DW1: 0x00003000 */ PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3), /* GPP_H2 - MODEM_CLKREQ */ - /* DW0: 0x44000f00, DW1: 0x00003000 */ PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3), /* GPP_H3 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_H3, UP_20K), /* GPP_H4 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_H4, NONE), /* GPP_H5 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_H5, NONE), /* GPP_H6 - I2C3_SDA */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* GPP_H7 - I2C3_SCL */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* GPP_H8 - I2C4_SDA */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* GPP_H9 - I2C4_SCL */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* GPP_H10 - I2C5_SDA */ - /* DW0: 0x84000603, DW1: 0x00000000 */ PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1), /* GPP_H11 - I2C5_SCL */ - /* DW0: 0x84000603, DW1: 0x00000000 */ PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF1), /* GPP_H12 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H12, 1, PLTRST), /* GPP_H13 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPP_H14 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H14, 1, PLTRST), /* GPP_H15 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H15, 1, PLTRST), /* GPP_H16 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_H16, NONE), /* GPP_H17 - GPIO */ - /* DW0: 0x44000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H17, 0, DEEP), /* GPP_H18 - CPU_C10_GATE# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* GPP_H19 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H19, 1, PLTRST), /* GPP_H20 - GPIO */ - /* DW0: 0x84000300, DW1: 0x00000000 */ PAD_NC(GPP_H20, NONE), /* GPP_H21 - GPIO */ - /* DW0: 0x44000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H21, 0, DEEP), /* GPP_H22 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H22, 1, PLTRST), /* GPP_H23 - GPIO */ - /* DW0: 0x44000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H23, 0, DEEP), /* ------- GPIO Group GPD ------- */ /* GPD0 - BATLOW# */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* GPD1 - ACPRESENT */ - /* DW0: 0x44000702, DW1: 0x00003c00 */ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), /* GPD2 - LAN_WAKE# */ - /* DW0: 0x44000702, DW1: 0x00003c00 */ PAD_CFG_NF(GPD2, NATIVE, DEEP, NF1), /* GPD3 - PRWBTN# */ - /* DW0: 0x44000702, DW1: 0x00003000 */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4 - SLP_S3# */ - /* DW0: 0x44000600, DW1: 0x00000000 */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5 - SLP_S4# */ - /* DW0: 0x44000600, DW1: 0x00000000 */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6 - SLP_A# */ - /* DW0: 0x44000600, DW1: 0x00000000 */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* GPD7 - GPIO */ - /* DW0: 0x44000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPD7, 0, DEEP), /* GPD8 - SUSCLK */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9 - SLP_WLAN# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* GPD10 - SLP_S5# */ - /* DW0: 0x44000600, DW1: 0x00000000 */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* GPD11 - LANPHYPC */ - /* DW0: 0x44000600, DW1: 0x00000000 */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - SMBCLK */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* GPP_C1 - SMBDATA */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* GPP_C2 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_C2, 1, DEEP), /* GPP_C3 - SML0CLK */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* GPP_C4 - SML0DATA */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* GPP_C5 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_C5, 1, PLTRST), /* GPP_C6 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_C6, NONE), /* GPP_C7 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_C7, NONE), /* GPP_C8 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_C8, 1, PLTRST), /* GPP_C9 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_C9, 1, PLTRST), /* GPP_C10 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_C10, 0, PLTRST), /* GPP_C11 - GPIO */ - /* DW0: 0x40100103, DW1: 0x00000000 */ PAD_CFG_GPI_APIC(GPP_C11, NONE, DEEP, LEVEL, NONE), /* GPP_C12 - UART1_RXD */ - /* DW0: 0x84000603, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), /* GPP_C13 - UART1_TXD */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* GPP_C14 - UART1_RTS# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* GPP_C15 - UART1_CTS# */ - /* DW0: 0x84000603, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1), /* GPP_C16 - I2C0_SDA */ - /* DW0: 0x84000402, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), /* GPP_C17 - I2C0_SCL */ - /* DW0: 0x84000402, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), /* GPP_C18 - I2C1_SDA */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* GPP_C19 - I2C1_SCL */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GPP_C20 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_C20, NONE), /* GPP_C21 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_C21, NONE), /* GPP_C22 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_C22, 1, PLTRST), /* GPP_C23 - GPIO */ - /* DW0: 0x40100102, DW1: 0x00001000 */ PAD_CFG_GPI_APIC(GPP_C23, DN_20K, DEEP, LEVEL, NONE), /* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_E0, NONE), /* GPP_E1 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_E1, NONE), /* GPP_E2 - SATAXPCIE2 */ - /* DW0: 0x84000502, DW1: 0x00003000 */ PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), /* GPP_E3 - GPIO */ - /* DW0: 0x82040102, DW1: 0x00000000 */ PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), /* GPP_E4 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_E4, 1, PLTRST), /* GPP_E5 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_E5, NONE), /* GPP_E6 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_E6, NONE), /* GPP_E7 - GPIO */ - /* DW0: 0x82000102, DW1: 0x00000000 */ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, EDGE_SINGLE, ACPI), /* GPP_E8 - SATALED# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* GPP_E9 - RESERVED */ - /* DW0: 0x44001700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF5), /* GPP_E10 - RESERVED */ - /* DW0: 0x44001700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF5), /* GPP_E11 - USB2_OC2# */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* GPP_E12 - USB2_OC3# */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* GPP_E13 - DDPB_HPD0 */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* GPP_E14 - DDPC_HPD1 */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* GPP_E15 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_E15, 1, PLTRST), /* GPP_E16 - GPIO */ - /* DW0: 0x80880102, DW1: 0x00003000 */ PAD_CFG_GPI_SCI(GPP_E16, UP_20K, PLTRST, LEVEL, INVERT), /* GPP_E17 - EDP_HPD */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* GPP_E18 - DPPB_CTRLCLK */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* GPP_E19 - DPPB_CTRLDATA */ - /* DW0: 0x44000602, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* GPP_E20 - DPPC_CTRLCLK */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* GPP_E21 - DPPC_CTRLDATA */ - /* DW0: 0x44000602, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* GPP_E22 - DPPD_CTRLCLK */ - /* DW0: 0x84000603, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E22, NONE, PLTRST, NF1), /* GPP_E23 - DPPD_CTRLDATA */ - /* DW0: 0x84000603, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E23, NONE, PLTRST, NF1), }; From ce1d588f071dd3c6917a6423f2908dabe824a773 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 24 Sep 2020 02:22:45 +0200 Subject: [PATCH 074/262] mb/msi/ms7707/Kconfig: Drop invalid defaults The PCI ID corresponds to the iGPU, which is disabled in the devicetree. Also, the VBIOS file does not exist at the specified location. Change-Id: I4f128d3057dc7218f32320c4e23466eb31af4e54 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45672 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/msi/ms7707/Kconfig | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/mainboard/msi/ms7707/Kconfig b/src/mainboard/msi/ms7707/Kconfig index e6095ba305..93a43f9517 100644 --- a/src/mainboard/msi/ms7707/Kconfig +++ b/src/mainboard/msi/ms7707/Kconfig @@ -33,12 +33,4 @@ config CBFS_SIZE hex default 0x200000 -config VGA_BIOS_FILE - string - default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/vgabios.bin" - -config VGA_BIOS_ID - string - default "8086,0102" - endif From b5d9f4a1cfc4022e63a3d47e817920fc5375c952 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 3 Nov 2020 11:38:05 -0700 Subject: [PATCH 075/262] ec/google/chromeec: Remove the check for Internal TypeC MUX Integrated TypeC MUX is used only in certain SoCs and hence the missing devicetree configuration is not an error. Remove the check for internal TypeC MUX device and the associated debug statement. BUG=b:172186858 TEST=Build and boot to OS in Drawlat. Change-Id: Ieb76e1ccfd04f1628617b2665b05be6718a25f81 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47175 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/ec_acpi.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 344f5f42e5..448ea4dadd 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -140,10 +140,6 @@ static void fill_ssdt_typec_device(const struct device *dev) if (rv) continue; - if (!config->mux_conn[i]) - printk(BIOS_ERR, "ERROR: Mux connector info missing for Type-C port " - "#%d\n", i); - usb2_port = NULL; usb3_port = NULL; usb4_port = NULL; From 1032d22152f1889246cda62e767af1da24407089 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 4 Nov 2020 16:19:35 +0100 Subject: [PATCH 076/262] soc/amd/picasso: move MAX_CPUS setting from mainboard to SoC Kconfig Since the mainboard Kconfig is sourced before the SoC one, it would still be possible to override this setting at mainboard level, even though that shouldn't be needed. The maximum CPU count for Picasso is 8, since the chips have only up to 4 cores with up to two threads each. Change-Id: I53449b8fa73c5d13e6ea77bee6eed8896b7d3ec3 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47205 Reviewed-by: Marshall Dawson Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/amd/mandolin/Kconfig | 4 ---- src/mainboard/google/zork/Kconfig | 4 ---- src/soc/amd/picasso/Kconfig | 4 ++++ 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 8e2bd8ba28..f4032d4e1d 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -52,10 +52,6 @@ config DEVICETREE string default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" -config MAX_CPUS - int - default 8 - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index c4f6bf73c4..eb9092a6d1 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -96,10 +96,6 @@ config MAINBOARD_FAMILY string default "Google_Zork" -config MAX_CPUS - int - default 8 - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 605b0eacea..bae2d2868a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -193,6 +193,10 @@ config VERSTAGE_ADDR hex default 0x4000000 +config MAX_CPUS + int + default 8 + config VGA_BIOS_ID string default "1002,15d8,c1" From d83e24d9d562bf9697a3fb8b02736e09d5cdafb0 Mon Sep 17 00:00:00 2001 From: Ravi Sarawadi Date: Wed, 14 Oct 2020 16:30:38 -0700 Subject: [PATCH 077/262] soc/intel/tigerlake: Disable C1 C-state Demotion Disable C1 C-state auto demotion to decrease SoC power usage. When set, processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information. BUG=b:161215906 TEST=Measure and confirm SoC power usage reduction for key use cases eg 'Google Meets video call' Measured on instrumented boards for Volteer EVT and Delbin. Below measurements for Volteer: Google meets with 720p w/ auto-demotion w/o auto-demotion System Power 13.14W 9.4W SOC Power 7.9W 5.4W Signed-off-by: Ravi Sarawadi Signed-off-by: Shweta Malik Change-Id: I649cafbaf03917d76521aa5f76ec58d218e1a1b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46438 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/fsp_params.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 887241b5c2..3427a61792 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -365,6 +365,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ params->EnableMultiPhaseSiliconInit = 1; + + /* Disable C1 C-state Demotion */ + params->C1StateAutoDemotion = 0; + mainboard_silicon_init_params(params); } From 0cae9008f01af3cd89dad317d42292c04b53bb51 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Fri, 30 Oct 2020 18:00:51 +0800 Subject: [PATCH 078/262] mb/google/octopus/variants/garg: Add new LTE SKU Add new SKU definition: Garg360 (LTE DB,1A2C,TS, no stylus, rear camera) SKU ID - 39 BUG=b:170708728 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: Ifec4e1360bd1aff3825bc6413b0a2ccd8b822075 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/47015 Reviewed-by: Marco Chen Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/variants/garg/gpio.c | 1 + .../google/octopus/variants/garg/include/variant/sku.h | 1 + src/mainboard/google/octopus/variants/garg/variant.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index 67e105649a..d7affc7234 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -71,6 +71,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num) return hdmi_override_table; case SKU_17_LTE: case SKU_18_LTE_TS: + case SKU_39_1A2C_360_LTE_TS_NO_STYLUES: *num = ARRAY_SIZE(lte_override_table); return lte_override_table; default: diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h index 8fc63cca21..96e9c5301d 100644 --- a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h +++ b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h @@ -12,6 +12,7 @@ enum { SKU_20_2A2C_TS = 20, SKU_37_2A2C_360 = 37, SKU_38_2A2C_360_TS_NO_STYLUES = 38, + SKU_39_1A2C_360_LTE_TS_NO_STYLUES = 39, SKU_49_2A2C_TS = 49, SKU_50_HDMI = 50, SKU_51_2A2C = 51, diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index 0a6574d1a6..00e5d326e1 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -37,6 +37,7 @@ void variant_smi_sleep(u8 slp_typ) switch (google_chromeec_get_board_sku()) { case SKU_17_LTE: case SKU_18_LTE_TS: + case SKU_39_1A2C_360_LTE_TS_NO_STYLUES: power_off_lte_module(); return; default: @@ -54,6 +55,7 @@ void variant_update_devtree(struct device *dev) switch (google_chromeec_get_board_sku()) { case SKU_17_LTE: case SKU_18_LTE_TS: + case SKU_39_1A2C_360_LTE_TS_NO_STYLUES: cfg->disable_xhci_lfps_pm = 1; return; default: From 795d73c6d851fde143041483af5dff7c448febe6 Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Tue, 27 Oct 2020 15:36:55 +0800 Subject: [PATCH 079/262] soc/amd/picasso: Update coreboot UPD variable names to include units Use command below to change the variable globally. sed -i "s/\/variable_u/g" `grep variable -rl ./ \ --exclude-dir=build --exclude-dir=crossgcc` BUG=b:171334623 TEST=Build Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3 Signed-off-by: Zheng Bao Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson Reviewed-by: Felix Held --- .../variants/baseboard/devicetree_dalboz.cb | 20 ++++----- .../variants/baseboard/devicetree_trembyle.cb | 20 ++++----- .../zork/variants/berknip/overridetree.cb | 14 +++---- .../zork/variants/dalboz/overridetree.cb | 14 +++---- .../zork/variants/dirinboz/overridetree.cb | 14 +++---- .../zork/variants/ezkinil/overridetree.cb | 14 +++---- .../zork/variants/morphius/overridetree.cb | 24 +++++------ .../zork/variants/trembyle/overridetree.cb | 14 +++---- .../zork/variants/vilboz/overridetree.cb | 14 +++---- .../zork/variants/woomax/overridetree.cb | 14 +++---- src/soc/amd/picasso/chip.h | 42 +++++++++---------- src/soc/amd/picasso/romstage.c | 42 +++++++++---------- src/soc/amd/picasso/root_complex.c | 16 +++---- src/vendorcode/amd/fsp/picasso/FspmUpd.h | 42 +++++++++---------- .../google/dalboz/template/overridetree.cb | 10 ++--- .../google/trembyle/template/overridetree.cb | 14 +++---- 16 files changed, 164 insertions(+), 164 deletions(-) diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 58e25e6ba3..9f5ef0c37b 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -15,22 +15,22 @@ chip soc/amd/picasso # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time - register "prochot_l_deassertion_ramp_time" = "20" #mS + register "prochot_l_deassertion_ramp_time_ms" = "20" # Lower die temperature limit - register "thermctl_limit" = "100" #degrees C + register "thermctl_limit_degreeC" = "100" # FP5 Processor Voltage Supply PSI Currents - register "psi0_current_limit" = "18000" #mA - register "psi0_soc_current_limit" = "12000" #mA - register "vddcr_soc_voltage_margin" = "0" #mV - register "vddcr_vdd_voltage_margin" = "0" #mV + register "psi0_current_limit_mA" = "18000" + register "psi0_soc_current_limit_mA" = "12000" + register "vddcr_soc_voltage_margin_mV" = "0" + register "vddcr_vdd_voltage_margin_mV" = "0" # VRM Limits - register "vrm_maximum_current_limit" = "0" #mA - register "vrm_soc_maximum_current_limit" = "0" #mA - register "vrm_current_limit" = "0" #mA - register "vrm_soc_current_limit" = "0" #mA + register "vrm_maximum_current_limit_mA" = "0" + register "vrm_soc_maximum_current_limit_mA" = "0" + register "vrm_current_limit_mA" = "0" + register "vrm_soc_current_limit_mA" = "0" # Misc SMU settings register "sb_tsi_alert_comparator_mode_en" = "0" diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 3ab70a2945..ffe2b7f3f3 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -15,22 +15,22 @@ chip soc/amd/picasso # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time - register "prochot_l_deassertion_ramp_time" = "20" #mS + register "prochot_l_deassertion_ramp_time_ms" = "20" # Lower die temperature limit - register "thermctl_limit" = "100" #degrees C + register "thermctl_limit_degreeC" = "100" # FP5 Processor Voltage Supply PSI Currents - register "psi0_current_limit" = "18000" #mA - register "psi0_soc_current_limit" = "12000" #mA - register "vddcr_soc_voltage_margin" = "0" #mV - register "vddcr_vdd_voltage_margin" = "0" #mV + register "psi0_current_limit_mA" = "18000" + register "psi0_soc_current_limit_mA" = "12000" + register "vddcr_soc_voltage_margin_mV" = "0" + register "vddcr_vdd_voltage_margin_mV" = "0" # VRM Limits - register "vrm_maximum_current_limit" = "0" #mA - register "vrm_soc_maximum_current_limit" = "0" #mA - register "vrm_current_limit" = "0" #mA - register "vrm_soc_current_limit" = "0" #mA + register "vrm_maximum_current_limit_mA" = "0" + register "vrm_soc_maximum_current_limit_mA" = "0" + register "vrm_current_limit_mA" = "0" + register "vrm_soc_current_limit_mA" = "0" # Misc SMU settings register "sb_tsi_alert_comparator_mode_en" = "0" diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index d97a2b5780..8f6aff2ede 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -9,15 +9,15 @@ chip soc/amd/picasso register "system_config" = "3" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "20000" #mw - register "fast_ppt_limit" = "24000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "12000" #mw + register "slow_ppt_limit_mW" = "20000" + register "fast_ppt_limit_mW" = "24000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "200" + register "sustained_power_limit_mW" = "12000" - register "telemetry_vddcr_vdd_slope" = "65599" #mA + register "telemetry_vddcr_vdd_slope_mA" = "65599" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "29788" #mA + register "telemetry_vddcr_soc_slope_mA" = "29788" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb index 1ddb17bdf4..67fa077f3d 100644 --- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -9,17 +9,17 @@ chip soc/amd/picasso register "system_config" = "1" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "6000" #mw - register "fast_ppt_limit" = "9000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "2500" #second - register "sustained_power_limit" = "4800" #mw + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "2500" + register "sustained_power_limit_mW" = "4800" # End : OPN Performance Configuration - register "telemetry_vddcr_vdd_slope" = "30231" #mA + register "telemetry_vddcr_vdd_slope_mA" = "30231" register "telemetry_vddcr_vdd_offset" = "0-1" - register "telemetry_vddcr_soc_slope" = "22644" #mA + register "telemetry_vddcr_soc_slope_mA" = "22644" register "telemetry_vddcr_soc_offset" = "68" # I2C2 for touchscreen and trackpad diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index a11fa5e4c7..f3be599780 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -9,15 +9,15 @@ chip soc/amd/picasso register "system_config" = "1" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "6000" #mw - register "fast_ppt_limit" = "9000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "2500" #second - register "sustained_power_limit" = "4800" #mw + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "2500" + register "sustained_power_limit_mW" = "4800" - register "telemetry_vddcr_vdd_slope" = "42465" #mA + register "telemetry_vddcr_vdd_slope_mA" = "42465" register "telemetry_vddcr_vdd_offset" = "69" - register "telemetry_vddcr_soc_slope" = "42667" #mA + register "telemetry_vddcr_soc_slope_mA" = "42667" register "telemetry_vddcr_soc_offset" = "167" # End : OPN Performance Configuration diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index 5ef2f0ac77..4fd7e0e063 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -9,15 +9,15 @@ chip soc/amd/picasso register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "20000" #mw - register "fast_ppt_limit" = "24000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "12000" #mw + register "slow_ppt_limit_mW" = "20000" + register "fast_ppt_limit_mW" = "24000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "200" + register "sustained_power_limit_mW" = "12000" - register "telemetry_vddcr_vdd_slope" = "62413" #mA + register "telemetry_vddcr_vdd_slope_mA" = "62413" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_slope_mA" = "28977" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index e04a62e654..4ac5f81798 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -9,24 +9,24 @@ chip soc/amd/picasso register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "20000" #mw - register "fast_ppt_limit" = "24000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "12000" #mw - register "thermctl_limit" = "100" #degrees C + register "slow_ppt_limit_mW" = "20000" + register "fast_ppt_limit_mW" = "24000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "200" + register "sustained_power_limit_mW" = "12000" + register "thermctl_limit_degreeC" = "100" - register "telemetry_vddcr_vdd_slope" = "62641" #mA + register "telemetry_vddcr_vdd_slope_mA" = "62641" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28333" #mA + register "telemetry_vddcr_soc_slope_mA" = "28333" register "telemetry_vddcr_soc_offset" = "0" # Set STAPM confiuration for tablet mode register "dptc_enable" = "1" - register "slow_ppt_limit_tablet_mode" = "20000" #mw - register "fast_ppt_limit_tablet_mode" = "24000" #mw - register "sustained_power_limit_tablet_mode" = "12000" #mw - register "thermctl_limit_tablet_mode" = "70" #degrees C + register "slow_ppt_limit_tablet_mode_mW" = "20000" + register "fast_ppt_limit_tablet_mode_mW" = "24000" + register "sustained_power_limit_tablet_mode_mW" = "12000" + register "thermctl_limit_tablet_mode_degreeC" = "70" # End : OPN Performance Configuration diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb index f06f03d8d6..90020ea89c 100644 --- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -9,15 +9,15 @@ chip soc/amd/picasso register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "25000" #mw - register "fast_ppt_limit" = "30000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "15000" #mw + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "200" + register "sustained_power_limit_mW" = "15000" - register "telemetry_vddcr_vdd_slope" = "71222" #mA + register "telemetry_vddcr_vdd_slope_mA" = "71222" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_slope_mA" = "28977" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index bca556cbee..2f3b4fcc4e 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -10,17 +10,17 @@ chip soc/amd/picasso register "system_config" = "1" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "6000" # mW - register "fast_ppt_limit" = "9000" # mW - register "slow_ppt_time_constant" = "5" # second - register "stapm_time_constant" = "1400" # second - register "sustained_power_limit" = "4800" # mW + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "1400" + register "sustained_power_limit_mW" = "4800" # End : OPN Performance Configuration - register "telemetry_vddcr_vdd_slope" = "32643" #mA + register "telemetry_vddcr_vdd_slope_mA" = "32643" register "telemetry_vddcr_vdd_offset" = "208" - register "telemetry_vddcr_soc_slope" = "22742" #mA + register "telemetry_vddcr_soc_slope_mA" = "22742" register "telemetry_vddcr_soc_offset" = "-83" # USB OC pin mapping diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index e9d66f9a77..0f0e856559 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -10,15 +10,15 @@ chip soc/amd/picasso register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "25000" #mw - register "fast_ppt_limit" = "30000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "15000" #mw + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "200" + register "sustained_power_limit_mW" = "15000" - register "telemetry_vddcr_vdd_slope" = "102586" #mA + register "telemetry_vddcr_vdd_slope_mA" = "102586" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "26967" #mA + register "telemetry_vddcr_soc_slope_mA" = "26967" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 3098a817a7..9d8fb8e70a 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -102,22 +102,22 @@ struct soc_amd_picasso_config { uint8_t system_config; /* STAPM Configuration */ - uint32_t fast_ppt_limit; - uint32_t slow_ppt_limit; - uint32_t slow_ppt_time_constant; - uint32_t stapm_time_constant; - uint32_t sustained_power_limit; + uint32_t fast_ppt_limit_mW; + uint32_t slow_ppt_limit_mW; + uint32_t slow_ppt_time_constant_s; + uint32_t stapm_time_constant_s; + uint32_t sustained_power_limit_mW; /* Enable dptc for tablet mode (0 = disable, 1 = enable) */ uint8_t dptc_enable; /* STAPM Configuration for tablet mode (need enable dptc_enable first) */ - uint32_t fast_ppt_limit_tablet_mode; - uint32_t slow_ppt_limit_tablet_mode; - uint32_t sustained_power_limit_tablet_mode; + uint32_t fast_ppt_limit_tablet_mode_mW; + uint32_t slow_ppt_limit_tablet_mode_mW; + uint32_t sustained_power_limit_tablet_mode_mW; /* PROCHOT_L de-assertion Ramp Time */ - uint32_t prochot_l_deassertion_ramp_time; + uint32_t prochot_l_deassertion_ramp_time_ms; enum { DOWNCORE_AUTO = 0, @@ -128,29 +128,29 @@ struct soc_amd_picasso_config { uint8_t smt_disable; /* 1=disable SMT, 0=enable SMT */ /* Lower die temperature limit */ - uint32_t thermctl_limit; - uint32_t thermctl_limit_tablet_mode; + uint32_t thermctl_limit_degreeC; + uint32_t thermctl_limit_tablet_mode_degreeC; /* FP5 Processor Voltage Supply PSI Currents. 0 indicates use SOC default */ - uint32_t psi0_current_limit; - uint32_t psi0_soc_current_limit; - uint32_t vddcr_soc_voltage_margin; - uint32_t vddcr_vdd_voltage_margin; + uint32_t psi0_current_limit_mA; + uint32_t psi0_soc_current_limit_mA; + uint32_t vddcr_soc_voltage_margin_mV; + uint32_t vddcr_vdd_voltage_margin_mV; /* VRM Limits. 0 indicates use SOC default */ - uint32_t vrm_maximum_current_limit; - uint32_t vrm_soc_maximum_current_limit; - uint32_t vrm_current_limit; - uint32_t vrm_soc_current_limit; + uint32_t vrm_maximum_current_limit_mA; + uint32_t vrm_soc_maximum_current_limit_mA; + uint32_t vrm_current_limit_mA; + uint32_t vrm_soc_current_limit_mA; /* Misc SMU settings */ uint8_t sb_tsi_alert_comparator_mode_en; uint8_t core_dldo_bypass; uint8_t min_soc_vid_offset; uint8_t aclk_dpm0_freq_400MHz; - uint32_t telemetry_vddcr_vdd_slope; + uint32_t telemetry_vddcr_vdd_slope_mA; uint32_t telemetry_vddcr_vdd_offset; - uint32_t telemetry_vddcr_soc_slope; + uint32_t telemetry_vddcr_soc_slope_mA; uint32_t telemetry_vddcr_soc_offset; struct { diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index b96743101c..9be970ddac 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -105,37 +105,37 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->system_config = config->system_config; - if ((config->slow_ppt_limit) && - (config->fast_ppt_limit) && - (config->slow_ppt_time_constant) && - (config->stapm_time_constant)) { - mcfg->slow_ppt_limit = config->slow_ppt_limit; - mcfg->fast_ppt_limit = config->fast_ppt_limit; - mcfg->slow_ppt_time_constant = config->slow_ppt_time_constant; - mcfg->stapm_time_constant = config->stapm_time_constant; + if ((config->slow_ppt_limit_mW) && + (config->fast_ppt_limit_mW) && + (config->slow_ppt_time_constant_s) && + (config->stapm_time_constant_s)) { + mcfg->slow_ppt_limit_mW = config->slow_ppt_limit_mW; + mcfg->fast_ppt_limit_mW = config->fast_ppt_limit_mW; + mcfg->slow_ppt_time_constant_s = config->slow_ppt_time_constant_s; + mcfg->stapm_time_constant_s = config->stapm_time_constant_s; } mcfg->ccx_down_core_mode = config->downcore_mode; mcfg->ccx_disable_smt = config->smt_disable; - mcfg->sustained_power_limit = config->sustained_power_limit; - mcfg->prochot_l_deassertion_ramp_time = config->prochot_l_deassertion_ramp_time; - mcfg->thermctl_limit = config->thermctl_limit; - mcfg->psi0_current_limit = config->psi0_current_limit; - mcfg->psi0_soc_current_limit = config->psi0_soc_current_limit; - mcfg->vddcr_soc_voltage_margin = config->vddcr_soc_voltage_margin; - mcfg->vddcr_vdd_voltage_margin = config->vddcr_vdd_voltage_margin; - mcfg->vrm_maximum_current_limit = config->vrm_maximum_current_limit; - mcfg->vrm_soc_maximum_current_limit = config->vrm_soc_maximum_current_limit; - mcfg->vrm_current_limit = config->vrm_current_limit; - mcfg->vrm_soc_current_limit = config->vrm_soc_current_limit; + mcfg->sustained_power_limit_mW = config->sustained_power_limit_mW; + mcfg->prochot_l_deassertion_ramp_time_ms = config->prochot_l_deassertion_ramp_time_ms; + mcfg->thermctl_limit_degreeC = config->thermctl_limit_degreeC; + mcfg->psi0_current_limit_mA = config->psi0_current_limit_mA; + mcfg->psi0_soc_current_limit_mA = config->psi0_soc_current_limit_mA; + mcfg->vddcr_soc_voltage_margin_mV = config->vddcr_soc_voltage_margin_mV; + mcfg->vddcr_vdd_voltage_margin_mV = config->vddcr_vdd_voltage_margin_mV; + mcfg->vrm_maximum_current_limit_mA = config->vrm_maximum_current_limit_mA; + mcfg->vrm_soc_maximum_current_limit_mA = config->vrm_soc_maximum_current_limit_mA; + mcfg->vrm_current_limit_mA = config->vrm_current_limit_mA; + mcfg->vrm_soc_current_limit_mA = config->vrm_soc_current_limit_mA; mcfg->sb_tsi_alert_comparator_mode_en = config->sb_tsi_alert_comparator_mode_en; mcfg->core_dldo_bypass = config->core_dldo_bypass; mcfg->min_soc_vid_offset = config->min_soc_vid_offset; mcfg->aclk_dpm0_freq_400MHz = config->aclk_dpm0_freq_400MHz; - mcfg->telemetry_vddcr_vdd_slope = config->telemetry_vddcr_vdd_slope; + mcfg->telemetry_vddcr_vdd_slope_mA = config->telemetry_vddcr_vdd_slope_mA; mcfg->telemetry_vddcr_vdd_offset = config->telemetry_vddcr_vdd_offset; - mcfg->telemetry_vddcr_soc_slope = config->telemetry_vddcr_soc_slope; + mcfg->telemetry_vddcr_soc_slope_mA = config->telemetry_vddcr_soc_slope_mA; mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset; mcfg->hd_audio_enable = devtree_hda_dev_enabled(); mcfg->sata_enable = devtree_sata_dev_enabled(); diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 174cddc487..72a0974897 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -200,15 +200,15 @@ static void acipgen_dptci(void) if (!config->dptc_enable) return; - struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit, - config->sustained_power_limit, - config->fast_ppt_limit, - config->slow_ppt_limit); + struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, + config->sustained_power_limit_mW, + config->fast_ppt_limit_mW, + config->slow_ppt_limit_mW); struct dptc_input tablet_mode_input = DPTC_INPUTS( - config->thermctl_limit_tablet_mode, - config->sustained_power_limit_tablet_mode, - config->fast_ppt_limit_tablet_mode, - config->slow_ppt_limit_tablet_mode); + config->thermctl_limit_tablet_mode_degreeC, + config->sustained_power_limit_tablet_mode_mW, + config->fast_ppt_limit_tablet_mode_mW, + config->slow_ppt_limit_tablet_mode_mW); /* Scope (\_SB) */ acpigen_write_scope("\\_SB"); diff --git a/src/vendorcode/amd/fsp/picasso/FspmUpd.h b/src/vendorcode/amd/fsp/picasso/FspmUpd.h index 56e1a5ea1b..960d0b4eb3 100644 --- a/src/vendorcode/amd/fsp/picasso/FspmUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspmUpd.h @@ -18,33 +18,33 @@ typedef struct __packed { /** Offset 0x004C**/ uint32_t serial_port_stride; /** Offset 0x0050**/ uint32_t serial_port_baudrate; /** Offset 0x0054**/ uint32_t serial_port_refclk; - /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope; - /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2; - /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3; - /** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4; - /** Offset 0x0068**/ uint32_t telemetry_vddcr_vdd_slope5; + /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope_mA; + /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2_mA; + /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3_mA; + /** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4_mA; + /** Offset 0x0068**/ uint32_t telemetry_vddcr_vdd_slope5_mA; /** Offset 0x006C**/ uint32_t telemetry_vddcr_vdd_offset; - /** Offset 0x0070**/ uint32_t telemetry_vddcr_soc_slope; + /** Offset 0x0070**/ uint32_t telemetry_vddcr_soc_slope_mA; /** Offset 0x0074**/ uint32_t telemetry_vddcr_soc_offset; /** Offset 0x0078**/ uint8_t aa_mode_en; /** Offset 0x0079**/ uint8_t unused2; /** Offset 0x007A**/ uint8_t unused3; /** Offset 0x007B**/ uint8_t unused4; - /** Offset 0x007C**/ uint32_t fast_ppt_limit; - /** Offset 0x0080**/ uint32_t slow_ppt_limit; - /** Offset 0x0084**/ uint32_t slow_ppt_time_constant; - /** Offset 0x0088**/ uint32_t psi0_current_limit; - /** Offset 0x008C**/ uint32_t psi0_soc_current_limit; - /** Offset 0x0090**/ uint32_t thermctl_limit; - /** Offset 0x0094**/ uint32_t vrm_maximum_current_limit; - /** Offset 0x0098**/ uint32_t vrm_soc_maximum_current_limit; - /** Offset 0x009C**/ uint32_t sustained_power_limit; - /** Offset 0x00A0**/ uint32_t stapm_time_constant; - /** Offset 0x00A4**/ uint32_t prochot_l_deassertion_ramp_time; - /** Offset 0x00A8**/ uint32_t vrm_current_limit; - /** Offset 0x00AC**/ uint32_t vrm_soc_current_limit; - /** Offset 0x00B0**/ uint32_t vddcr_soc_voltage_margin; - /** Offset 0x00B4**/ uint32_t vddcr_vdd_voltage_margin; + /** Offset 0x007C**/ uint32_t fast_ppt_limit_mW; + /** Offset 0x0080**/ uint32_t slow_ppt_limit_mW; + /** Offset 0x0084**/ uint32_t slow_ppt_time_constant_s; + /** Offset 0x0088**/ uint32_t psi0_current_limit_mA; + /** Offset 0x008C**/ uint32_t psi0_soc_current_limit_mA; + /** Offset 0x0090**/ uint32_t thermctl_limit_degreeC; + /** Offset 0x0094**/ uint32_t vrm_maximum_current_limit_mA; + /** Offset 0x0098**/ uint32_t vrm_soc_maximum_current_limit_mA; + /** Offset 0x009C**/ uint32_t sustained_power_limit_mW; + /** Offset 0x00A0**/ uint32_t stapm_time_constant_s; + /** Offset 0x00A4**/ uint32_t prochot_l_deassertion_ramp_time_ms; + /** Offset 0x00A8**/ uint32_t vrm_current_limit_mA; + /** Offset 0x00AC**/ uint32_t vrm_soc_current_limit_mA; + /** Offset 0x00B0**/ uint32_t vddcr_soc_voltage_margin_mV; + /** Offset 0x00B4**/ uint32_t vddcr_vdd_voltage_margin_mV; /** Offset 0x00B8**/ uint32_t smu_feature_control_defines; /** Offset 0x00BC**/ uint32_t smu_feature_control_defines_ext; /** Offset 0x00C0**/ uint8_t sb_tsi_alert_comparator_mode_en; diff --git a/util/mainboard/google/dalboz/template/overridetree.cb b/util/mainboard/google/dalboz/template/overridetree.cb index 7645ba33e3..1cc2364f5e 100644 --- a/util/mainboard/google/dalboz/template/overridetree.cb +++ b/util/mainboard/google/dalboz/template/overridetree.cb @@ -10,11 +10,11 @@ chip soc/amd/picasso register "system_config" = "1" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "6000" #mw - register "fast_ppt_limit" = "9000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "2500" #second - register "sustained_power_limit" = "4800" #mw + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "2500" + register "sustained_power_limit_mW" = "4800" # End : OPN Performance Configuration diff --git a/util/mainboard/google/trembyle/template/overridetree.cb b/util/mainboard/google/trembyle/template/overridetree.cb index d332fce28e..6f545b2402 100644 --- a/util/mainboard/google/trembyle/template/overridetree.cb +++ b/util/mainboard/google/trembyle/template/overridetree.cb @@ -10,15 +10,15 @@ chip soc/amd/picasso register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "25000" #mw - register "fast_ppt_limit" = "30000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "15000" #mw + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "200" + register "sustained_power_limit_mW" = "15000" - register "telemetry_vddcr_vdd_slope" = "71222" #mA + register "telemetry_vddcr_vdd_slope_mA" = "71222" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_slope_mA" = "28977" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration From af2efbb59b0d9b3fa1ac97b8cfa08754aebd9141 Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Thu, 5 Nov 2020 18:26:10 +0800 Subject: [PATCH 080/262] amdfwtool: Use shell command to get depend file list The amdfwtool is not available at the beginning of the building. So it may have error if it is missing. Change-Id: Id4db70986755cef8e98877c4e92841b25ced5452 Signed-off-by: Zheng Bao Reviewed-on: https://review.coreboot.org/c/coreboot/+/47237 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/Makefile.inc | 3 ++- src/soc/amd/stoneyridge/Makefile.inc | 3 ++- src/southbridge/amd/pi/hudson/Makefile.inc | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 5a88d0b684..ffc1463b19 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -242,7 +242,8 @@ endif OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) # Add all the files listed in the config file -DEP_FILES=$(shell $(AMDFWTOOL) --config $(CONFIG_AMDFW_CONFIG_FILE) --depend) +POUND_SIGN=$(call strip_quotes, "\#") +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index c608286382..fb0a45bd65 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -148,7 +148,8 @@ endif OPT_PSP_USE_PSPSECUREOS=$(call strip_quotes, $(PSP_USE_PSPSECUREOS)) # Add all the files listed in the config file -DEP_FILES=$(shell $(AMDFWTOOL) --config $(CONFIG_AMDFW_CONFIG_FILE) --depend) +POUND_SIGN=$(call strip_quotes, "\#") +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index d5528aacef..94c759ee3e 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -121,7 +121,8 @@ OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) # Add all the files listed in the config file -DEP_FILES=$(shell $(AMDFWTOOL) --config $(CONFIG_AMDFW_CONFIG_FILE) --depend) +POUND_SIGN=$(call strip_quotes, "\#") +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ From c6a6e54d056757d77da8a881622383239b814381 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 2 Nov 2020 11:59:16 -0700 Subject: [PATCH 081/262] soc/intel/xeon_sp/cpx: Reorder cpu.c .h includes Clean up the header includes. Change-Id: I9f61d1a82b37bc0ed803967dc64decf18f44adc9 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/47169 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Arthur Heymans Reviewed-by: Jay Talbott --- src/soc/intel/xeon_sp/cpx/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 5bde819ec6..134824a250 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -16,8 +17,8 @@ #include #include #include + #include "chip.h" -#include static const void *microcode_patch; From 18960ce0c96ebb20c5d7664f6d5ca9d729adea4b Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 2 Nov 2020 12:41:12 -0700 Subject: [PATCH 082/262] soc/intel/xeon_sp: Move CPU helper functions Continue Xeon-SP de-duplication. Move CPU helper functions from skx/ and cpx soc_util.c to common util.c. Functions only used by util.c are updated to be static. The following functions are moved: int get_threads_per_package(void); int get_platform_thread_count(void); const IIO_UDS *get_iio_uds(void); unsigned int soc_get_num_cpus(void); void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); void xeonsp_init_cpu_config(void); Change-Id: I118a451b9468459cf2c2194f31da1055e1435ebe Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/47170 Reviewed-by: Arthur Heymans Reviewed-by: Jay Talbott Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/acpi.c | 3 +- src/soc/intel/xeon_sp/cpx/cpu.c | 1 + .../intel/xeon_sp/cpx/include/soc/soc_util.h | 10 -- src/soc/intel/xeon_sp/cpx/soc_util.c | 133 +---------------- src/soc/intel/xeon_sp/include/soc/util.h | 5 + src/soc/intel/xeon_sp/nb_acpi.c | 1 + .../intel/xeon_sp/skx/include/soc/soc_util.h | 9 -- src/soc/intel/xeon_sp/skx/soc_util.c | 126 ---------------- src/soc/intel/xeon_sp/util.c | 137 ++++++++++++++++++ 9 files changed, 147 insertions(+), 278 deletions(-) diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index acf030b450..d33d1d0cea 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -11,8 +11,9 @@ #include #include #include -#include #include +#include +#include #include acpi_cstate_t *soc_get_cstate_map(size_t *entries) diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 134824a250..d1bcbd7977 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "chip.h" diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 5f4a6f9e2f..8c454bb29e 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -13,16 +13,6 @@ struct iiostack_resource { uint8_t get_iiostack_info(struct iiostack_resource *info); -void xeonsp_init_cpu_config(void); -const IIO_UDS *get_iio_uds(void); -void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); -void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, - uint8_t *package, uint8_t *core, uint8_t *thread); -/* Return socket count, as obtained from FSP HOB */ -unsigned int soc_get_num_cpus(void); - -int get_platform_thread_count(void); -int get_threads_per_package(void); const struct SystemMemoryMapHob *get_system_memory_map(void); void set_bios_init_completion(void); diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index de6d8525c2..149f2c01eb 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -9,22 +8,11 @@ #include #include #include +#include #include #include #include -int get_threads_per_package(void) -{ - unsigned int core_count, thread_count; - cpu_read_topology(&core_count, &thread_count); - return thread_count; -} - -int get_platform_thread_count(void) -{ - return soc_get_num_cpus() * get_threads_per_package(); -} - const struct SystemMemoryMapHob *get_system_memory_map(void) { size_t hob_size; @@ -41,125 +29,6 @@ const struct SystemMemoryMapHob *get_system_memory_map(void) return *memmap_addr; } -void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, - uint8_t *package, uint8_t *core, uint8_t *thread) -{ - if (package != NULL) - *package = (apicid >> (thread_bits + core_bits)); - if (core != NULL) - *core = (uint32_t)((apicid >> thread_bits) & ~((~0) << core_bits)); - if (thread != NULL) - *thread = (uint32_t)(apicid & ~((~0) << thread_bits)); -} - -void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits) -{ - register int ecx; - struct cpuid_result cpuid_regs; - - /* get max index of CPUID */ - cpuid_regs = cpuid(0); - assert(cpuid_regs.eax >= 0xb); /* cpuid_regs.eax is max input value for cpuid */ - - *thread_bits = *core_bits = 0; - ecx = 0; - while (1) { - cpuid_regs = cpuid_ext(0xb, ecx); - if (ecx == 0) { - *thread_bits = (cpuid_regs.eax & 0x1f); - } else { - *core_bits = (cpuid_regs.eax & 0x1f) - *thread_bits; - break; - } - ecx++; - } -} - -const IIO_UDS *get_iio_uds(void) -{ - size_t hob_size; - const IIO_UDS *hob; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - - hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - return hob; -} - -unsigned int soc_get_num_cpus(void) -{ - /* The FSP IIO UDS HOB has field numCpus, it is actually socket count */ - return get_iio_uds()->SystemStatus.numCpus; -} - -void xeonsp_init_cpu_config(void) -{ - struct device *dev; - int apic_ids[CONFIG_MAX_CPUS] = {0}, apic_ids_by_thread[CONFIG_MAX_CPUS] = {0}; - int num_apics = 0; - uint32_t core_bits, thread_bits; - unsigned int core_count, thread_count; - unsigned int num_sockets; - - /* - * sort APIC ids in asending order to identify apicid ranges for - * each numa domain - */ - for (dev = all_devices; dev; dev = dev->next) { - if ((dev->path.type != DEVICE_PATH_APIC) || - (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!dev->enabled) - continue; - if (num_apics >= ARRAY_SIZE(apic_ids)) - break; - apic_ids[num_apics++] = dev->path.apic.apic_id; - } - if (num_apics > 1) - bubblesort(apic_ids, num_apics, NUM_ASCENDING); - - num_sockets = soc_get_num_cpus(); - cpu_read_topology(&core_count, &thread_count); - assert(num_apics == (num_sockets * thread_count)); - - /* sort them by thread i.e., all cores with thread 0 and then thread 1 */ - int index = 0; - for (int id = 0; id < num_apics; ++id) { - int apic_id = apic_ids[id]; - if (apic_id & 0x1) { /* 2nd thread */ - apic_ids_by_thread[index + (num_apics/2) - 1] = apic_id; - } else { /* 1st thread */ - apic_ids_by_thread[index++] = apic_id; - } - } - - /* update apic_id, node_id in sorted order */ - num_apics = 0; - get_core_thread_bits(&core_bits, &thread_bits); - for (dev = all_devices; dev; dev = dev->next) { - uint8_t package; - - if ((dev->path.type != DEVICE_PATH_APIC) || - (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!dev->enabled) - continue; - if (num_apics >= ARRAY_SIZE(apic_ids)) - break; - dev->path.apic.apic_id = apic_ids_by_thread[num_apics]; - get_cpu_info_from_apicid(dev->path.apic.apic_id, core_bits, thread_bits, - &package, NULL, NULL); - dev->path.apic.node_id = package; - printk(BIOS_DEBUG, "CPU %d apic_id: 0x%x (%d), node_id: 0x%x\n", - num_apics, dev->path.apic.apic_id, - dev->path.apic.apic_id, dev->path.apic.node_id); - - ++num_apics; - } -} - uint8_t get_iiostack_info(struct iiostack_resource *info) { size_t hob_size; diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 51e2b69b00..73fc63da4c 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -10,5 +10,10 @@ void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus void unlock_pam_regions(void); void get_stack_busnos(uint32_t *bus); msr_t read_msr_ppin(void); +int get_threads_per_package(void); +int get_platform_thread_count(void); +const IIO_UDS *get_iio_uds(void); +unsigned int soc_get_num_cpus(void); +void xeonsp_init_cpu_config(void); #endif diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index cf397f7897..4a29c0868f 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "chip.h" diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index cce542a1d5..fd0d4e2fbb 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -13,20 +13,11 @@ struct iiostack_resource { uint8_t get_iiostack_info(struct iiostack_resource *info); -void xeonsp_init_cpu_config(void); - void config_reset_cpl3_csrs(void); -void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); -void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, - uint8_t *package, uint8_t *core, uint8_t *thread); - -int get_platform_thread_count(void); -int get_threads_per_package(void); const struct SystemMemoryMapHob *get_system_memory_map(void); void set_bios_init_completion(void); -unsigned int soc_get_num_cpus(void); int soc_get_stack_for_port(int port); #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 3af6483dfe..5a2b3c6ca5 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include #include #include #include @@ -230,64 +229,6 @@ void set_bios_init_completion(void) set_bios_init_completion_for_package(sbsp_socket_id); } -void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits) -{ - register int ecx; - struct cpuid_result cpuid_regs; - - /* get max index of CPUID */ - cpuid_regs = cpuid(0); - assert(cpuid_regs.eax >= 0xb); /* cpuid_regs.eax is max input value for cpuid */ - - *thread_bits = *core_bits = 0; - ecx = 0; - while (1) { - cpuid_regs = cpuid_ext(0xb, ecx); - if (ecx == 0) { - *thread_bits = (cpuid_regs.eax & 0x1f); - } else { - *core_bits = (cpuid_regs.eax & 0x1f) - *thread_bits; - break; - } - ecx++; - } -} - -void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, - uint8_t *package, uint8_t *core, uint8_t *thread) -{ - if (package != NULL) - *package = (apicid >> (thread_bits + core_bits)); - if (core != NULL) - *core = (uint32_t)((apicid >> thread_bits) & ~((~0) << core_bits)); - if (thread != NULL) - *thread = (uint32_t)(apicid & ~((~0) << thread_bits)); -} - -unsigned int soc_get_num_cpus(void) -{ - size_t hob_size; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob; - - /* these fields are incorrect - need debugging */ - hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - return hob->SystemStatus.numCpus; -} - -int get_threads_per_package(void) -{ - unsigned int core_count, thread_count; - cpu_read_topology(&core_count, &thread_count); - return thread_count; -} - -int get_platform_thread_count(void) -{ - return soc_get_num_cpus() * get_threads_per_package(); -} - uint8_t get_iiostack_info(struct iiostack_resource *info) { size_t hob_size; @@ -327,73 +268,6 @@ const struct SystemMemoryMapHob *get_system_memory_map(void) return memmap_addr; } -void xeonsp_init_cpu_config(void) -{ - struct device *dev; - int apic_ids[CONFIG_MAX_CPUS] = {0}, apic_ids_by_thread[CONFIG_MAX_CPUS] = {0}; - int num_apics = 0; - uint32_t core_bits, thread_bits; - unsigned int core_count, thread_count; - unsigned int num_cpus; - - /* sort APIC ids in asending order to identify apicid ranges for - each numa domain - */ - for (dev = all_devices; dev; dev = dev->next) { - if ((dev->path.type != DEVICE_PATH_APIC) || - (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!dev->enabled) - continue; - if (num_apics >= ARRAY_SIZE(apic_ids)) - break; - apic_ids[num_apics++] = dev->path.apic.apic_id; - } - if (num_apics > 1) - bubblesort(apic_ids, num_apics, NUM_ASCENDING); - - num_cpus = soc_get_num_cpus(); - cpu_read_topology(&core_count, &thread_count); - assert(num_apics == (num_cpus * thread_count)); - - /* sort them by thread i.e., all cores with thread 0 and then thread 1 */ - int index = 0; - for (int id = 0; id < num_apics; ++id) { - int apic_id = apic_ids[id]; - if (apic_id & 0x1) { /* 2nd thread */ - apic_ids_by_thread[index + (num_apics/2) - 1] = apic_id; - } else { /* 1st thread */ - apic_ids_by_thread[index++] = apic_id; - } - } - - /* update apic_id, node_id in sorted order */ - num_apics = 0; - get_core_thread_bits(&core_bits, &thread_bits); - for (dev = all_devices; dev; dev = dev->next) { - uint8_t package; - - if ((dev->path.type != DEVICE_PATH_APIC) || - (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!dev->enabled) - continue; - if (num_apics >= ARRAY_SIZE(apic_ids)) - break; - dev->path.apic.apic_id = apic_ids_by_thread[num_apics]; - get_cpu_info_from_apicid(dev->path.apic.apic_id, core_bits, thread_bits, - &package, NULL, NULL); - dev->path.apic.node_id = package; - printk(BIOS_DEBUG, "CPU %d apic_id: 0x%x (%d), node_id: 0x%x\n", - num_apics, dev->path.apic.apic_id, - dev->path.apic.apic_id, dev->path.apic.node_id); - - ++num_apics; - } -} - /* * EX: SKX-SP * Ports Stack Stack(HOB) IioConfigIou diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 66b9ef11c1..feacca497e 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -1,7 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include +#include #include +#include #include #include #include @@ -85,3 +89,136 @@ msr_t read_msr_ppin(void) wrmsr(MSR_PPIN_CTL, msr); return ppin; } + +int get_threads_per_package(void) +{ + unsigned int core_count, thread_count; + cpu_read_topology(&core_count, &thread_count); + return thread_count; +} + +int get_platform_thread_count(void) +{ + return soc_get_num_cpus() * get_threads_per_package(); +} + +const IIO_UDS *get_iio_uds(void) +{ + size_t hob_size; + const IIO_UDS *hob; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + + hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + return hob; +} + +unsigned int soc_get_num_cpus(void) +{ + /* The FSP IIO UDS HOB has field numCpus, it is actually socket count */ + return get_iio_uds()->SystemStatus.numCpus; +} + +#if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */ +static void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits) +{ + register int ecx; + struct cpuid_result cpuid_regs; + + /* get max index of CPUID */ + cpuid_regs = cpuid(0); + assert(cpuid_regs.eax >= 0xb); /* cpuid_regs.eax is max input value for cpuid */ + + *thread_bits = *core_bits = 0; + ecx = 0; + while (1) { + cpuid_regs = cpuid_ext(0xb, ecx); + if (ecx == 0) { + *thread_bits = (cpuid_regs.eax & 0x1f); + } else { + *core_bits = (cpuid_regs.eax & 0x1f) - *thread_bits; + break; + } + ecx++; + } +} + +static void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, + uint8_t *package, uint8_t *core, uint8_t *thread) +{ + if (package != NULL) + *package = (apicid >> (thread_bits + core_bits)); + if (core != NULL) + *core = (uint32_t)((apicid >> thread_bits) & ~((~0) << core_bits)); + if (thread != NULL) + *thread = (uint32_t)(apicid & ~((~0) << thread_bits)); +} + +void xeonsp_init_cpu_config(void) +{ + struct device *dev; + int apic_ids[CONFIG_MAX_CPUS] = {0}, apic_ids_by_thread[CONFIG_MAX_CPUS] = {0}; + int num_apics = 0; + uint32_t core_bits, thread_bits; + unsigned int core_count, thread_count; + unsigned int num_sockets; + + /* + * sort APIC ids in asending order to identify apicid ranges for + * each numa domain + */ + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type != DEVICE_PATH_APIC) || + (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!dev->enabled) + continue; + if (num_apics >= ARRAY_SIZE(apic_ids)) + break; + apic_ids[num_apics++] = dev->path.apic.apic_id; + } + if (num_apics > 1) + bubblesort(apic_ids, num_apics, NUM_ASCENDING); + + num_sockets = soc_get_num_cpus(); + cpu_read_topology(&core_count, &thread_count); + assert(num_apics == (num_sockets * thread_count)); + + /* sort them by thread i.e., all cores with thread 0 and then thread 1 */ + int index = 0; + for (int id = 0; id < num_apics; ++id) { + int apic_id = apic_ids[id]; + if (apic_id & 0x1) { /* 2nd thread */ + apic_ids_by_thread[index + (num_apics/2) - 1] = apic_id; + } else { /* 1st thread */ + apic_ids_by_thread[index++] = apic_id; + } + } + + /* update apic_id, node_id in sorted order */ + num_apics = 0; + get_core_thread_bits(&core_bits, &thread_bits); + for (dev = all_devices; dev; dev = dev->next) { + uint8_t package; + + if ((dev->path.type != DEVICE_PATH_APIC) || + (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!dev->enabled) + continue; + if (num_apics >= ARRAY_SIZE(apic_ids)) + break; + dev->path.apic.apic_id = apic_ids_by_thread[num_apics]; + get_cpu_info_from_apicid(dev->path.apic.apic_id, core_bits, thread_bits, + &package, NULL, NULL); + dev->path.apic.node_id = package; + printk(BIOS_DEBUG, "CPU %d apic_id: 0x%x (%d), node_id: 0x%x\n", + num_apics, dev->path.apic.apic_id, + dev->path.apic.apic_id, dev->path.apic.node_id); + + ++num_apics; + } +} +#endif From 83729bd430425ef9b161ebb9260ad047d3920d7c Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Thu, 5 Nov 2020 17:30:26 -0700 Subject: [PATCH 083/262] soc/intel/xeon_sp/skx: Fix MADT CPU indexes The CPU index wasn't getting updated. Confirm MADT sets IOAPIC and CPU ID numbers. Change-Id: I72430cc48f4609ac408e723172ba1ed263cca8e3 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/47277 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Arthur Heymans --- src/soc/intel/xeon_sp/skx/soc_acpi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index b3926193da..95563f5837 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -182,7 +182,7 @@ void soc_power_states_generation(int core, int cores_per_package) unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) { struct device *cpu; - int num_cpus = 0; + uint8_t num_cpus = 0; for (cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || @@ -193,6 +193,7 @@ unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) continue; current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, num_cpus, cpu->path.apic.apic_id); + num_cpus++; } return current; From 8839b7f1099f358e967f468b98dd225c4e330444 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Wed, 28 Oct 2020 11:38:57 -0600 Subject: [PATCH 084/262] security/vboot: Add Kconfig symbol to set hashing block size Generally, this size probably doesn't matter very much, but in the case of picasso's psp_verstage, the hash is being calculated by hardware using relatively expensive system calls. By increasing the block size, we can save roughly 140ms of boot and resume time. TEST=Build & boot see that boot time has decreased. BRANCH=Zork BUG=b:169217270 - Zork: SHA calculation in vboot takes too long Signed-off-by: Martin Roth Change-Id: I68eecbbdfadcbf14288dc6e849397724fb66e0b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46901 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Kangheui Won --- src/security/vboot/Kconfig | 11 +++++++++++ src/security/vboot/vboot_logic.c | 4 +--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 094cbb9642..e7744786f6 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -369,6 +369,17 @@ config VBOOT_KEYBLOCK_PREAMBLE_FLAGS hex "Keyblock preamble flags" default 0x0 +config VBOOT_HASH_BLOCK_SIZE + hex + default 0x400 + help + Set the default hash size. Generally 1k is reasonable, but in some + cases it may improve hashing speed to increase the size. + + Note that this buffer is allocated in the stack. Although the + build should fail if the stack size is exceeded, it's something to + be aware of when changing the size. + endmenu # Keys endif # VBOOT endmenu # Verified Boot (vboot) diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index dbaa883080..54c82244b6 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -19,8 +19,6 @@ /* The max hash size to expect is for SHA512. */ #define VBOOT_MAX_HASH_SIZE VB2_SHA512_DIGEST_SIZE -#define TODO_BLOCK_SIZE 1024 - /* exports */ vb2_error_t vb2ex_read_resource(struct vb2_context *ctx, @@ -144,7 +142,7 @@ static vb2_error_t hash_body(struct vb2_context *ctx, { uint64_t load_ts; uint32_t remaining; - uint8_t block[TODO_BLOCK_SIZE]; + uint8_t block[CONFIG_VBOOT_HASH_BLOCK_SIZE]; uint8_t hash_digest[VBOOT_MAX_HASH_SIZE]; const size_t hash_digest_sz = sizeof(hash_digest); size_t block_size = sizeof(block); From 5602945e9fbe24a43968fc59b12767dc2c3041c3 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Fri, 30 Oct 2020 21:01:10 +0800 Subject: [PATCH 085/262] mb/google/variant/elemi: Select USE_CAR_NEM_ENHANCED_V2 for elemi BUG=b:170604353 TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen Change-Id: I1a1ab6f3d57d5023523b85bfb00d48d8b70a6c1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/47018 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/volteer/Kconfig.name | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index d8f1b4470c..8f966ee679 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -80,6 +80,7 @@ config BOARD_GOOGLE_BOLDAR config BOARD_GOOGLE_ELEMI bool "-> Elemi" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select USE_CAR_NEM_ENHANCED_V2 config BOARD_GOOGLE_VOEMA bool "-> Voema" From 4efd7d99268e94bc8bde13a22d4df3df27775672 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Fri, 30 Oct 2020 21:08:53 +0800 Subject: [PATCH 086/262] mb/google/variant/elemi: config CSE LITE Config elemi to use CSE LITE BUG=b:170604353 TEST=emerge-volteer coreboot Change-Id: I31c7a743645d6a34ee34e750ba92c108b306ee09 Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/47019 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/Kconfig.name | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 8f966ee679..6c9248e99d 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -80,6 +80,7 @@ config BOARD_GOOGLE_BOLDAR config BOARD_GOOGLE_ELEMI bool "-> Elemi" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU select USE_CAR_NEM_ENHANCED_V2 config BOARD_GOOGLE_VOEMA From 1597a213262d812503300dfec083f524dc113d67 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Sat, 31 Oct 2020 00:51:06 +0800 Subject: [PATCH 087/262] mb/google/volteer/var/elemi: Update gpio and devicetree Update gpio and devicetree for elemi. BUG=b:170604353 TEST=emerge-volteer coreboot and boot into kernel Signed-off-by: Wisley Chen Change-Id: I5b8880d485ed73aa4e65c1249c58f02c8f0c6501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47039 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../volteer/variants/elemi/Makefile.inc | 4 + .../google/volteer/variants/elemi/gpio.c | 224 ++++++++++++++++++ .../volteer/variants/elemi/overridetree.cb | 130 +++++++++- 3 files changed, 357 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/google/volteer/variants/elemi/gpio.c diff --git a/src/mainboard/google/volteer/variants/elemi/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/Makefile.inc index 9064208bff..b0bfc567ff 100644 --- a/src/mainboard/google/volteer/variants/elemi/Makefile.inc +++ b/src/mainboard/google/volteer/variants/elemi/Makefile.inc @@ -1,3 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/elemi/gpio.c b/src/mainboard/google/volteer/variants/elemi/gpio.c new file mode 100644 index 0000000000..6868aca0eb --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/gpio.c @@ -0,0 +1,224 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + /* B3 : CPU_GP2 ==> PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B4 : CPU_GP3==> EN_PP3300_EMMC */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBCLK ==> EMMC_CLKREQ_ODL*/ + PAD_CFG_GPO(GPP_C1, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, DN_20K), + /* C3 : EMMC_PE_WAKE_ODL*/ + PAD_CFG_GPI(GPP_C3, NONE, DEEP), + /* C4 : EMMC_PERST_L*/ + PAD_CFG_GPO(GPP_C4, 1, DEEP), + + /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP_0 */ + PAD_NC(GPP_C5, DN_20K), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */ + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MOSI_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 0, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */ + PAD_CFG_GPI(GPP_E6, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + + /* F7 : GPPF7_STRAP ==> GPP_F7_STRAP */ + PAD_NC(GPP_F7, DN_20K), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> NC */ + PAD_NC(GPP_F12, NONE), + + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, DN_20K), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, DN_20K), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, DN_20K), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H10 : SRCCLKREQ4# */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 31e1927a91..5ea48ad038 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -1,5 +1,49 @@ chip soc/intel/tigerlake + register "TcssAuxOri" = "1" + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on device ref north_xhci on chip drivers/usb/acpi @@ -76,6 +120,90 @@ chip soc/intel/tigerlake end end end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end # PMC end - end From 03d06d3bcd368a8e635e3279d4f17336f09adef8 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Wed, 28 Oct 2020 13:51:42 -0600 Subject: [PATCH 088/262] soc/amd/picasso: Up stack size to 40k for vboot hash buffer Increasing the vboot hash buffer size greatly speeds up the SHA calculations. Going from a standard 4k buffer to a 36k buffer takes ~150ms of the boot and resume time. TEST=Build & boot see that boot time has decreased. BRANCH=Zork BUG=b:169217270 - Zork: SHA calculation in vboot takes too long Signed-off-by: Martin Roth Change-Id: Ibca868ad7be639c2a0ca1c4ba6d71123d8b83c92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46902 Reviewed-by: Felix Held Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/memlayout_psp_verstage.ld | 6 +++--- src/soc/amd/picasso/psp_verstage/Makefile.inc | 3 +++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/picasso/memlayout_psp_verstage.ld b/src/soc/amd/picasso/memlayout_psp_verstage.ld index e7a6c84000..ca95cf81bd 100644 --- a/src/soc/amd/picasso/memlayout_psp_verstage.ld +++ b/src/soc/amd/picasso/memlayout_psp_verstage.ld @@ -19,15 +19,15 @@ * should be sufficient. This is just for the function mapping the * actual stack. */ -#define PSP_VERSTAGE_TEMP_STACK_START 0x39000 +#define PSP_VERSTAGE_TEMP_STACK_START 0x32000 #define PSP_VERSTAGE_TEMP_STACK_SIZE 4K /* * The top of the stack must be 4k aligned, so set the bottom as 4k aligned * and make the size a multiple of 4k */ -#define PSP_VERSTAGE_STACK_START 0x3B000 -#define PSP_VERSTAGE_STACK_SIZE 8K +#define PSP_VERSTAGE_STACK_START 0x33000 +#define PSP_VERSTAGE_STACK_SIZE 40K ENTRY(_psp_vs_start) SECTIONS diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.inc b/src/soc/amd/picasso/psp_verstage/Makefile.inc index 4f1642bdf7..0986fd8750 100644 --- a/src/soc/amd/picasso/psp_verstage/Makefile.inc +++ b/src/soc/amd/picasso/psp_verstage/Makefile.inc @@ -5,6 +5,9 @@ verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/picasso/include verstage-generic-ccopts += -D__USER_SPACE__ CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/2lib/include/ +# This size should match the size in the linker script. +CFLAGS_arm += -Wstack-usage=40960 + verstage-y += delay.c verstage-y += fch.c verstage-y += pmutil.c From 5632c6bc020b02868e21714ea990d550e44e91d3 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Wed, 28 Oct 2020 11:52:30 -0600 Subject: [PATCH 089/262] soc/amd/picasso: Set vboot hashing block size to 36k On picasso's psp_verstage, the vboot hash is being calculated by hardware using relatively expensive system calls. By increasing the block size, we can save roughly 150ms of boot and S3 resume time. TEST=Build & boot see that boot time has decreased. BRANCH=Zork BUG=b:169217270 - Zork: SHA calculation in vboot takes too long Signed-off-by: Martin Roth Change-Id: I6642073357327811b415dcbcad6930ac6d2598f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46903 Reviewed-by: Aaron Durbin Reviewed-by: Kangheui Won Reviewed-by: Felix Held Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Kconfig | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index bae2d2868a..5ae0a2a58f 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -535,6 +535,22 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK Runs verstage on the PSP. Only available on certain Chrome OS branded parts from AMD. +config VBOOT_HASH_BLOCK_SIZE + hex + default 0x9000 + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + help + Because the bulk of the time in psp_verstage to hash the RO cbfs is + spent in the overhead of doing svc calls, increasing the hash block + size significantly cuts the verstage hashing time as seen below. + + 4k takes 180ms + 16k takes 44ms + 32k takes 33.7ms + 36k takes 32.5ms + There's actually still room for an even bigger stack, but we've + reached a point of diminishing returns. + config CMOS_RECOVERY_BYTE hex default 0x51 From ea4db9b8fb2e29a1640afbf8b59b974d61c5b6a4 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 4 Nov 2020 00:40:53 -0600 Subject: [PATCH 090/262] mb/purism/librem_mini: Set unused GPIO pads to PAD_NC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set numerous pads to PAD_NC as per board schematics (they are either NC, or connected to test pads), and adjust comments as needed. Change-Id: I4c2ab936256d0031d7a127fbeac42c8951a0b39f Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47191 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- .../librem_cnl/variants/librem_mini/gpio.c | 560 +++++++++--------- 1 file changed, 280 insertions(+), 280 deletions(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index 4c735c5168..b35ee4c64d 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -28,8 +28,8 @@ static const struct pad_config gpio_table[] = { /* GPP_A6 - SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - /* GPP_A7 - GPIO */ - PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* GPP_A7 - NC */ + PAD_NC(GPP_A7, NONE), /* GPP_A8 - CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), @@ -40,43 +40,43 @@ static const struct pad_config gpio_table[] = { /* GPP_A10 - CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), - /* GPP_A11 - GPIO */ - PAD_CFG_GPO(GPP_A11, 1, PLTRST), + /* GPP_A11 - NC */ + PAD_NC(GPP_A11, UP_20K), - /* GPP_A12 - GPIO */ - PAD_CFG_GPO(GPP_A12, 1, PLTRST), + /* GPP_A12 - NC */ + PAD_NC(GPP_A12, UP_20K), - /* GPP_A13 - GPIO */ - PAD_CFG_GPO(GPP_A13, 1, PLTRST), + /* GPP_A13 - NC */ + PAD_NC(GPP_A13, NONE), /* GPP_A14 - SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - /* GPP_A15 - GPIO */ - PAD_CFG_GPO(GPP_A15, 1, PLTRST), + /* GPP_A15 - NC */ + PAD_NC(GPP_A15, NONE), - /* GPP_A16 - GPIO */ - PAD_CFG_TERM_GPO(GPP_A16, 1, UP_20K, PLTRST), + /* GPP_A16 - NC */ + PAD_NC(GPP_A16, UP_20K), - /* GPP_A17 - GPIO */ - PAD_CFG_GPO(GPP_A17, 1, PLTRST), + /* GPP_A17 - NC */ + PAD_NC(GPP_A17, UP_20K), - /* GPP_A18 - GPIO */ + /* GPP_A18 - NC */ PAD_NC(GPP_A18, UP_20K), - /* GPP_A19 - GPIO */ + /* GPP_A19 - NC */ PAD_NC(GPP_A19, UP_20K), - /* GPP_A20 - GPIO */ + /* GPP_A20 - NC */ PAD_NC(GPP_A20, UP_20K), - /* GPP_A21 - GPIO */ + /* GPP_A21 - NC */ PAD_NC(GPP_A21, UP_20K), - /* GPP_A22 - GPIO */ + /* GPP_A22 - NC */ PAD_NC(GPP_A22, UP_20K), - /* GPP_A23 - GPIO */ + /* GPP_A23 - NC */ PAD_NC(GPP_A23, UP_20K), /* ------- GPIO Group GPP_B ------- */ @@ -87,35 +87,35 @@ static const struct pad_config gpio_table[] = { /* GPP_B1 - Reserved */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), - /* GPP_B2 - VRALERT# */ - PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), + /* GPP_B2 - NC */ + PAD_NC(GPP_B2, UP_20K), - /* GPP_B3 - GPIO */ - PAD_CFG_GPO(GPP_B3, 1, PLTRST), + /* GPP_B3 - NC */ + PAD_NC(GPP_B3, NONE), - /* GPP_B4 - GPIO */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* GPP_B4 - NC */ + PAD_NC(GPP_B4, UP_20K), - /* GPP_B5 - GPIO */ + /* GPP_B5 - NC */ PAD_NC(GPP_B5, NONE), - /* GPP_B6 - GPIO */ + /* GPP_B6 - NC */ PAD_NC(GPP_B6, NONE), - /* GPP_B7 - GPIO */ + /* GPP_B7 - NC */ PAD_NC(GPP_B7, NONE), - /* GPP_B8 - GPIO */ + /* GPP_B8 - NC */ PAD_NC(GPP_B8, NONE), - /* GPP_B9 - GPIO */ + /* GPP_B9 - NC */ PAD_NC(GPP_B9, NONE), - /* GPP_B10 - GPIO */ + /* GPP_B10 - NC */ PAD_NC(GPP_B10, NONE), - /* GPP_B11 - GPIO */ - PAD_CFG_GPO(GPP_B11, 1, PLTRST), + /* GPP_B11 - NC */ + PAD_NC(GPP_B11, NONE), /* GPP_B12 - SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), @@ -126,280 +126,280 @@ static const struct pad_config gpio_table[] = { /* GPP_B14 - GPIO */ PAD_CFG_GPO(GPP_B14, 1, PLTRST), - /* GPP_B15 - GPIO */ - PAD_CFG_TERM_GPO(GPP_B15, 1, UP_20K, PLTRST), + /* GPP_B15 - NC */ + PAD_NC(GPP_B15, NONE), - /* GPP_B16 - GSPI0_CLK */ - PAD_CFG_NF(GPP_B16, NONE, PLTRST, NF1), + /* GPP_B16 - NC */ + PAD_NC(GPP_B16, NONE), - /* GPP_B17 - GSPI0_MISO */ - PAD_CFG_NF(GPP_B17, NONE, PLTRST, NF1), + /* GPP_B17 - NC */ + PAD_NC(GPP_B17, NONE), - /* GPP_B18 - GSPI0_MOSI */ - PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1), + /* GPP_B18 - NC */ + PAD_NC(GPP_B18, NONE), - /* GPP_B19 - GSPI1_CS0# */ - PAD_CFG_NF(GPP_B19, NONE, PLTRST, NF1), + /* GPP_B19 - NC */ + PAD_NC(GPP_B19, NONE), - /* GPP_B20 - GSPI1_CLK */ - PAD_CFG_NF(GPP_B20, NONE, PLTRST, NF1), + /* GPP_B20 - NC */ + PAD_NC(GPP_B20, NONE), - /* GPP_B21 - GSPI1_MISO */ - PAD_CFG_NF(GPP_B21, NONE, PLTRST, NF1), + /* GPP_B21 - NC */ + PAD_NC(GPP_B21, NONE), - /* GPP_B22 - GSPI1_MOSI */ - PAD_CFG_NF(GPP_B22, NONE, PLTRST, NF1), + /* GPP_B22 - NC */ + PAD_NC(GPP_B22, UP_20K), - /* GPP_B23 - GPIO */ - PAD_CFG_GPO(GPP_B23, 1, DEEP), + /* GPP_B23 - NC */ + PAD_NC(GPP_B23, UP_20K), /* ------- GPIO Group GPP_G ------- */ - /* GPP_G0 - GPIO */ - PAD_CFG_TERM_GPO(GPP_G0, 0, DN_20K, PWROK), + /* GPP_G0 - NC */ + PAD_NC(GPP_G0, UP_20K), - /* GPP_G1 - GPIO */ + /* GPP_G1 - NC */ PAD_NC(GPP_G1, NONE), - /* GPP_G2 - GPIO */ - PAD_NC(GPP_G2, NONE), + /* GPP_G2 - NC */ + PAD_NC(GPP_G2, UP_20K), - /* GPP_G3 - GPIO */ - PAD_NC(GPP_G3, NONE), + /* GPP_G3 - NC */ + PAD_NC(GPP_G3, UP_20K), - /* GPP_G4 - GPIO */ - PAD_NC(GPP_G4, NONE), + /* GPP_G4 - NC */ + PAD_NC(GPP_G4, UP_20K), - /* GPP_G5 - GPIO */ + /* GPP_G5 - NC */ PAD_NC(GPP_G5, UP_20K), - /* GPP_G6 - GPIO */ - PAD_NC(GPP_G6, NONE), + /* GPP_G6 - NC */ + PAD_NC(GPP_G6, UP_20K), - /* GPP_G7 - GPIO */ + /* GPP_G7 - NC */ PAD_NC(GPP_G7, DN_20K), /* ------- GPIO Group GPP_D ------- */ - /* GPP_D0 - GPIO */ - PAD_NC(GPP_D0, NONE), + /* GPP_D0 - NC */ + PAD_NC(GPP_D0, UP_20K), - /* GPP_D1 - GPIO */ - PAD_NC(GPP_D1, NONE), + /* GPP_D1 - NC */ + PAD_NC(GPP_D1, UP_20K), - /* GPP_D2 - GPIO */ - PAD_NC(GPP_D2, NONE), + /* GPP_D2 - NC */ + PAD_NC(GPP_D2, UP_20K), - /* GPP_D3 - GPIO */ - PAD_NC(GPP_D3, NONE), + /* GPP_D3 - NC */ + PAD_NC(GPP_D3, UP_20K), - /* GPP_D4 - GPIO */ - PAD_NC(GPP_D4, NONE), + /* GPP_D4 - NC */ + PAD_NC(GPP_D4, UP_20K), - /* GPP_D5 - ISH_I2C0_SDA */ - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* GPP_D5 - NC */ + PAD_NC(GPP_D5, NONE), - /* GPP_D6 - ISH_I2C0_SCL */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* GPP_D6 - NC */ + PAD_NC(GPP_D6, NONE), - /* GPP_D7 - GPIO */ - PAD_CFG_GPO(GPP_D7, 1, PLTRST), + /* GPP_D7 - NC */ + PAD_NC(GPP_D7, UP_20K), - /* GPP_D8 - GPIO */ - PAD_CFG_GPO(GPP_D8, 1, PLTRST), + /* GPP_D8 - NC */ + PAD_NC(GPP_D8, NONE), - /* GPP_D9 - GPIO */ - PAD_CFG_GPO(GPP_D9, 1, PLTRST), + /* GPP_D9 - NC */ + PAD_NC(GPP_D9, NONE), - /* GPP_D10 - GPIO */ - PAD_CFG_GPO(GPP_D10, 1, PLTRST), + /* GPP_D10 - NC */ + PAD_NC(GPP_D10, NONE), - /* GPP_D11 - GPIO */ - PAD_CFG_TERM_GPO(GPP_D11, 1, UP_20K, DEEP), + /* GPP_D11 - NC */ + PAD_NC(GPP_D11, UP_20K), - /* GPP_D12 - GPIO */ - PAD_CFG_GPI_APIC(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, NONE), + /* GPP_D12 - NC */ + PAD_NC(GPP_D12, UP_20K), - /* GPP_D13 - GPIO */ - PAD_NC(GPP_D13, NONE), + /* GPP_D13 - NC */ + PAD_NC(GPP_D13, DN_20K), - /* GPP_D14 - GPIO */ - PAD_CFG_GPO(GPP_D14, 1, PLTRST), + /* GPP_D14 - NC */ + PAD_NC(GPP_D14, DN_20K), - /* GPP_D15 - GPIO */ - PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /* GPP_D15 - NC */ + PAD_NC(GPP_D15, UP_20K), - /* GPP_D16 - GPIO */ - PAD_CFG_GPO(GPP_D16, 0, RSMRST), + /* GPP_D16 - NC */ + PAD_NC(GPP_D16, UP_20K), - /* GPP_D17 - DMIC_CLK1 */ - PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* GPP_D17 - NC */ + PAD_NC(GPP_D17, NONE), - /* GPP_D18 - DMIC_DATA1 */ - PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* GPP_D18 - NC */ + PAD_NC(GPP_D18, NONE), - /* GPP_D19 - DMIC_CLK0 */ - PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* GPP_D19 - NC */ + PAD_NC(GPP_D19, NONE), - /* GPP_D20 - DMIC_DATA0 */ - PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* GPP_D20 - NC */ + PAD_NC(GPP_D20, NONE), - /* GPP_D21 - GPIO */ - PAD_NC(GPP_D21, NONE), + /* GPP_D21 - NC */ + PAD_NC(GPP_D21, UP_20K), - /* GPP_D22 - GPIO */ - PAD_NC(GPP_D22, NONE), + /* GPP_D22 - NC */ + PAD_NC(GPP_D22, UP_20K), - /* GPP_D23 - GPIO */ - PAD_NC(GPP_D23, NONE), + /* GPP_D23 - NC */ + PAD_NC(GPP_D23, UP_20K), /* ------- GPIO Group GPP_F ------- */ - /* GPP_F0 - GPIO */ - PAD_NC(GPP_F0, NONE), + /* GPP_F0 - NC */ + PAD_NC(GPP_F0, UP_20K), - /* GPP_F1 - GPIO */ - PAD_CFG_GPO(GPP_F1, 0, RSMRST), + /* GPP_F1 - NC */ + PAD_NC(GPP_F1, UP_20K), - /* GPP_F2 - GPIO */ - PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), + /* GPP_F2 - NC */ + PAD_NC(GPP_F2, UP_20K), - /* GPP_F3 - GPIO */ + /* GPP_F3 - NC */ PAD_NC(GPP_F3, UP_20K), - /* GPP_F4 - CNV_BRI_DT */ - PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1), + /* GPP_F4 - NC */ + PAD_NC(GPP_F4, UP_20K), - /* GPP_F5 - CNV_BRI_RSP */ - PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), + /* GPP_F5 - NC */ + PAD_NC(GPP_F5, UP_20K), - /* GPP_F6 - CNV_RGI_DT */ - PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1), + /* GPP_F6 - NC */ + PAD_NC(GPP_F6, NONE), - /* GPP_F7 - CNV_RGI_RSP */ - PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), + /* GPP_F7 - NC */ + PAD_NC(GPP_F7, NONE), - /* GPP_F8 - GPIO */ - PAD_NC(GPP_F8, NONE), + /* GPP_F8 - NC */ + PAD_NC(GPP_F8, UP_20K), - /* GPP_F9 - GPIO */ - PAD_NC(GPP_F9, NONE), + /* GPP_F9 - NC */ + PAD_NC(GPP_F9, UP_20K), - /* GPP_F10 - GPIO */ - PAD_CFG_GPO(GPP_F10, 1, PLTRST), + /* GPP_F10 - NC */ + PAD_NC(GPP_F10, UP_20K), - /* GPP_F11 - GPIO */ - PAD_NC(GPP_F11, NONE), + /* GPP_F11 - NC */ + PAD_NC(GPP_F11, UP_20K), - /* GPP_F12 - GPIO */ - PAD_NC(GPP_F12, NONE), + /* GPP_F12 - NC */ + PAD_NC(GPP_F12, UP_20K), - /* GPP_F13 - GPIO */ - PAD_NC(GPP_F13, NONE), + /* GPP_F13 - NC */ + PAD_NC(GPP_F13, UP_20K), - /* GPP_F14 - GPIO */ - PAD_NC(GPP_F14, NONE), + /* GPP_F14 - NC */ + PAD_NC(GPP_F14, UP_20K), - /* GPP_F15 - GPIO */ - PAD_NC(GPP_F15, NONE), + /* GPP_F15 - NC */ + PAD_NC(GPP_F15, UP_20K), - /* GPP_F16 - GPIO */ - PAD_NC(GPP_F16, NONE), + /* GPP_F16 - NC */ + PAD_NC(GPP_F16, UP_20K), - /* GPP_F17 - GPIO */ - PAD_NC(GPP_F17, NONE), + /* GPP_F17 - NC */ + PAD_NC(GPP_F17, UP_20K), - /* GPP_F18 - GPIO */ - PAD_NC(GPP_F18, NONE), + /* GPP_F18 - NC */ + PAD_NC(GPP_F18, UP_20K), - /* GPP_F19 - GPIO */ - PAD_NC(GPP_F19, NONE), + /* GPP_F19 - NC */ + PAD_NC(GPP_F19, UP_20K), - /* GPP_F20 - GPIO */ - PAD_NC(GPP_F20, NONE), + /* GPP_F20 - NC */ + PAD_NC(GPP_F20, UP_20K), - /* GPP_F21 - GPIO */ - PAD_NC(GPP_F21, NONE), + /* GPP_F21 - NC */ + PAD_NC(GPP_F21, UP_20K), - /* GPP_F22 - GPIO */ - PAD_NC(GPP_F22, NONE), + /* GPP_F22 - NC */ + PAD_NC(GPP_F22, UP_20K), - /* GPP_F23 - A4WP_PRESENT */ - PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1), + /* GPP_F23 - NC */ + PAD_NC(GPP_F23, UP_20K), /* ------- GPIO Group GPP_H ------- */ - /* GPP_H0 - GPIO */ + /* GPP_H0 - NC */ PAD_NC(GPP_H0, UP_20K), - /* GPP_H1 - CNV_RF_RESET# */ - PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3), + /* GPP_H1 - NC# */ + PAD_NC(GPP_H1, NONE), - /* GPP_H2 - MODEM_CLKREQ */ - PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3), + /* GPP_H2 - NC */ + PAD_NC(GPP_H2, NONE), - /* GPP_H3 - GPIO */ + /* GPP_H3 - NC */ PAD_NC(GPP_H3, UP_20K), - /* GPP_H4 - GPIO */ - PAD_NC(GPP_H4, NONE), + /* GPP_H4 - NC */ + PAD_NC(GPP_H4, UP_20K), - /* GPP_H5 - GPIO */ - PAD_NC(GPP_H5, NONE), + /* GPP_H5 - NC */ + PAD_NC(GPP_H5, UP_20K), - /* GPP_H6 - I2C3_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* GPP_H6 - NC */ + PAD_NC(GPP_H6, UP_20K), - /* GPP_H7 - I2C3_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* GPP_H7 - NC */ + PAD_NC(GPP_H7, UP_20K), - /* GPP_H8 - I2C4_SDA */ - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* GPP_H8 - NC */ + PAD_NC(GPP_H8, UP_20K), - /* GPP_H9 - I2C4_SCL */ - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* GPP_H9 - NC */ + PAD_NC(GPP_H9, UP_20K), - /* GPP_H10 - I2C5_SDA */ - PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1), + /* GPP_H10 - NC */ + PAD_NC(GPP_H10, NONE), - /* GPP_H11 - I2C5_SCL */ - PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF1), + /* GPP_H11 - NC */ + PAD_NC(GPP_H11, NONE), - /* GPP_H12 - GPIO */ - PAD_CFG_GPO(GPP_H12, 1, PLTRST), + /* GPP_H12 - NC */ + PAD_NC(GPP_H12, UP_20K), - /* GPP_H13 - GPIO */ - PAD_CFG_GPO(GPP_H13, 1, PLTRST), + /* GPP_H13 - NC */ + PAD_NC(GPP_H13, UP_20K), - /* GPP_H14 - GPIO */ - PAD_CFG_GPO(GPP_H14, 1, PLTRST), + /* GPP_H14 - NC */ + PAD_NC(GPP_H14, UP_20K), - /* GPP_H15 - GPIO */ - PAD_CFG_GPO(GPP_H15, 1, PLTRST), + /* GPP_H15 - NC */ + PAD_NC(GPP_H15, UP_20K), - /* GPP_H16 - GPIO */ - PAD_NC(GPP_H16, NONE), + /* GPP_H16 - NC */ + PAD_NC(GPP_H16, UP_20K), - /* GPP_H17 - GPIO */ - PAD_CFG_GPO(GPP_H17, 0, DEEP), + /* GPP_H17 - NC */ + PAD_NC(GPP_H17, UP_20K), - /* GPP_H18 - CPU_C10_GATE# */ - PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* GPP_H18 - NC */ + PAD_NC(GPP_H18, UP_20K), - /* GPP_H19 - GPIO */ - PAD_CFG_GPO(GPP_H19, 1, PLTRST), + /* GPP_H19 - NC */ + PAD_NC(GPP_H19, UP_20K), - /* GPP_H20 - GPIO */ - PAD_NC(GPP_H20, NONE), + /* GPP_H20 - NC */ + PAD_NC(GPP_H20, UP_20K), - /* GPP_H21 - GPIO */ - PAD_CFG_GPO(GPP_H21, 0, DEEP), + /* GPP_H21 - NC */ + PAD_NC(GPP_H21, NONE), - /* GPP_H22 - GPIO */ - PAD_CFG_GPO(GPP_H22, 1, PLTRST), + /* GPP_H22 - NC */ + PAD_NC(GPP_H22, UP_20K), - /* GPP_H23 - GPIO */ - PAD_CFG_GPO(GPP_H23, 0, DEEP), + /* GPP_H23 - NC */ + PAD_NC(GPP_H23, NONE), /* ------- GPIO Group GPD ------- */ @@ -409,8 +409,8 @@ static const struct pad_config gpio_table[] = { /* GPD1 - ACPRESENT */ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), - /* GPD2 - LAN_WAKE# */ - PAD_CFG_NF(GPD2, NATIVE, DEEP, NF1), + /* GPD2 - NC */ + PAD_NC(GPD2, NONE), /* GPD3 - PRWBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), @@ -421,23 +421,23 @@ static const struct pad_config gpio_table[] = { /* GPD5 - SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), - /* GPD6 - SLP_A# */ - PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD6 - NC */ + PAD_NC(GPD6, UP_20K), - /* GPD7 - GPIO */ - PAD_CFG_GPO(GPD7, 0, DEEP), + /* GPD7 - NC */ + PAD_NC(GPD7, NONE), /* GPD8 - SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), - /* GPD9 - SLP_WLAN# */ - PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD9 - NC */ + PAD_NC(GPD9, UP_20K), - /* GPD10 - SLP_S5# */ - PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD10 - NC */ + PAD_NC(GPD10, UP_20K), - /* GPD11 - LANPHYPC */ - PAD_CFG_NF(GPD11, NONE, DEEP, NF1), + /* GPD11 - NC */ + PAD_NC(GPD11, UP_20K), /* ------- GPIO Group GPP_C ------- */ @@ -447,97 +447,97 @@ static const struct pad_config gpio_table[] = { /* GPP_C1 - SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - /* GPP_C2 - GPIO */ - PAD_CFG_GPO(GPP_C2, 1, DEEP), + /* GPP_C2 - NC */ + PAD_NC(GPP_C2, NONE), - /* GPP_C3 - SML0CLK */ - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* GPP_C3 - NC */ + PAD_NC(GPP_C3, NONE), - /* GPP_C4 - SML0DATA */ - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* GPP_C4 - NC */ + PAD_NC(GPP_C4, NONE), - /* GPP_C5 - GPIO */ - PAD_CFG_GPO(GPP_C5, 1, PLTRST), + /* GPP_C5 - NC */ + PAD_NC(GPP_C5, UP_20K), - /* GPP_C6 - GPIO */ + /* GPP_C6 - NC */ PAD_NC(GPP_C6, NONE), - /* GPP_C7 - GPIO */ + /* GPP_C7 - NC */ PAD_NC(GPP_C7, NONE), - /* GPP_C8 - GPIO */ - PAD_CFG_GPO(GPP_C8, 1, PLTRST), + /* GPP_C8 - NC */ + PAD_NC(GPP_C8, NONE), - /* GPP_C9 - GPIO */ - PAD_CFG_GPO(GPP_C9, 1, PLTRST), + /* GPP_C9 - NC */ + PAD_NC(GPP_C9, NONE), - /* GPP_C10 - GPIO */ - PAD_CFG_GPO(GPP_C10, 0, PLTRST), + /* GPP_C10 - NC */ + PAD_NC(GPP_C10, UP_20K), - /* GPP_C11 - GPIO */ - PAD_CFG_GPI_APIC(GPP_C11, NONE, DEEP, LEVEL, NONE), + /* GPP_C11 - NC */ + PAD_NC(GPP_C11, UP_20K), - /* GPP_C12 - UART1_RXD */ - PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), + /* GPP_C12 - NC */ + PAD_NC(GPP_C12, UP_20K), - /* GPP_C13 - UART1_TXD */ - PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* GPP_C13 - NC */ + PAD_NC(GPP_C13, UP_20K), - /* GPP_C14 - UART1_RTS# */ - PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + /* GPP_C14 - NC */ + PAD_NC(GPP_C14, UP_20K), - /* GPP_C15 - UART1_CTS# */ - PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1), + /* GPP_C15 - NC */ + PAD_NC(GPP_C15, UP_20K), - /* GPP_C16 - I2C0_SDA */ - PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), + /* GPP_C16 - NC */ + PAD_NC(GPP_C16, NONE), - /* GPP_C17 - I2C0_SCL */ - PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), + /* GPP_C17 - NC */ + PAD_NC(GPP_C17, NONE), - /* GPP_C18 - I2C1_SDA */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* GPP_C18 - NC */ + PAD_NC(GPP_C18, UP_20K), - /* GPP_C19 - I2C1_SCL */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* GPP_C19 - NC */ + PAD_NC(GPP_C19, UP_20K), - /* GPP_C20 - GPIO */ + /* GPP_C20 - NC */ PAD_NC(GPP_C20, NONE), - /* GPP_C21 - GPIO */ + /* GPP_C21 - NC */ PAD_NC(GPP_C21, NONE), /* GPP_C22 - GPIO */ PAD_CFG_GPO(GPP_C22, 1, PLTRST), - /* GPP_C23 - GPIO */ - PAD_CFG_GPI_APIC(GPP_C23, DN_20K, DEEP, LEVEL, NONE), + /* GPP_C23 - NC */ + PAD_NC(GPP_C23, UP_20K), /* ------- GPIO Group GPP_E ------- */ - /* GPP_E0 - GPIO */ - PAD_NC(GPP_E0, NONE), + /* GPP_E0 - NC */ + PAD_NC(GPP_E0, UP_20K), - /* GPP_E1 - GPIO */ - PAD_NC(GPP_E1, NONE), + /* GPP_E1 - NC */ + PAD_NC(GPP_E1, UP_20K), /* GPP_E2 - SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), - /* GPP_E3 - GPIO */ - PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), + /* GPP_E3 - NC */ + PAD_NC(GPP_E3, UP_20K), /* GPP_E4 - GPIO */ PAD_CFG_GPO(GPP_E4, 1, PLTRST), - /* GPP_E5 - GPIO */ - PAD_NC(GPP_E5, NONE), + /* GPP_E5 - NC */ + PAD_NC(GPP_E5, UP_20K), - /* GPP_E6 - GPIO */ - PAD_NC(GPP_E6, NONE), + /* GPP_E6 - NC */ + PAD_NC(GPP_E6, UP_20K), - /* GPP_E7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, EDGE_SINGLE, ACPI), + /* GPP_E7 - NC */ + PAD_NC(GPP_E7, NONE), /* GPP_E8 - SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), @@ -560,14 +560,14 @@ static const struct pad_config gpio_table[] = { /* GPP_E14 - DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - /* GPP_E15 - GPIO */ - PAD_CFG_GPO(GPP_E15, 1, PLTRST), + /* GPP_E15 - NC */ + PAD_NC(GPP_E15, NONE), /* GPP_E16 - GPIO */ PAD_CFG_GPI_SCI(GPP_E16, UP_20K, PLTRST, LEVEL, INVERT), - /* GPP_E17 - EDP_HPD */ - PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + /* GPP_E17 - NC */ + PAD_NC(GPP_E17, NONE), /* GPP_E18 - DPPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), @@ -575,17 +575,17 @@ static const struct pad_config gpio_table[] = { /* GPP_E19 - DPPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), - /* GPP_E20 - DPPC_CTRLCLK */ - PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* GPP_E20 - NC */ + PAD_NC(GPP_E20, NONE), - /* GPP_E21 - DPPC_CTRLDATA */ - PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* GPP_E21 - NC */ + PAD_NC(GPP_E21, NONE), - /* GPP_E22 - DPPD_CTRLCLK */ - PAD_CFG_NF(GPP_E22, NONE, PLTRST, NF1), + /* GPP_E22 - NC */ + PAD_NC(GPP_E22, UP_20K), - /* GPP_E23 - DPPD_CTRLDATA */ - PAD_CFG_NF(GPP_E23, NONE, PLTRST, NF1), + /* GPP_E23 - NC */ + PAD_NC(GPP_E23, NONE), }; const struct pad_config *variant_gpio_table(size_t *num) From d8c189b669a8b98448f287fa0872d440b8892dd1 Mon Sep 17 00:00:00 2001 From: Lucas Chen Date: Fri, 30 Oct 2020 14:11:26 +0800 Subject: [PATCH 091/262] zork/var/ezkinil: Adjust USB2 phy si fine tune on DVT Board Adjust USB2 phy si setting fine tune on DVT for Ezkinil. BRANCH=zork BUG=b:156315391 TEST=Measuring scope timing and test usb detection Signed-off-by: Lucas Chen Change-Id: Id537b6e9a17f47481b6aedcea0c6a8474d993b6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47011 Tested-by: build bot (Jenkins) Reviewed-by: Rob Barnes Reviewed-by: Aaron Durbin --- .../zork/variants/ezkinil/overridetree.cb | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index 4fd7e0e063..2537ee8fc4 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -29,6 +29,31 @@ chip soc/amd/picasso .ports.xhci0_port3 = 1, }" + #USB 2.0 strength + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x05, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x9, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x05, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x9, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, From 53c173e9efa806d4124b28a25185eb596f936023 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 5 Nov 2020 17:24:18 +0100 Subject: [PATCH 092/262] soc/amd/picasso/cpu: add Raven1 CPUID to CPU table The RV1 CPUID is already in the cpu.h file, but was still missing from the CPU table in cpu.c. Change-Id: Iad78cbe933b40e946d421e4c93e523f9e31f1089 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47249 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 4d6e98d221..5979fc6a82 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -128,6 +128,7 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, RAVEN1_B0_CPUID}, { X86_VENDOR_AMD, PICASSO_B0_CPUID }, { X86_VENDOR_AMD, PICASSO_B1_CPUID }, { X86_VENDOR_AMD, RAVEN2_A0_CPUID }, From ac2da047acb50ce8a776e8d2218c2b304af8be02 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 5 Nov 2020 17:37:21 +0100 Subject: [PATCH 093/262] soc/amd/picasso: add Raven1 GPU PCI ID Change-Id: Id4460eb596b080dec1a63a20869182170c3388af Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47250 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/include/soc/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index e79dd87faf..cbc3929a78 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -12,6 +12,8 @@ void check_mca(void); #define RAVEN2_A0_CPUID 0x00820f00 #define RAVEN2_A1_CPUID 0x00820f01 +#define RAVEN1_VBIOS_VID_DID 0x100215dd +#define RAVEN1_VBIOS_REV 0x81 #define PICASSO_VBIOS_VID_DID 0x100215d8 #define PICASSO_VBIOS_REV 0xc1 #define RAVEN2_VBIOS_VID_DID 0x100215dd /* VID/DID in RV2 VBIOS header */ From 7bfef7d50ce6e7c6e562189249a180e4e9861749 Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Thu, 5 Nov 2020 13:49:59 -0800 Subject: [PATCH 094/262] sc7180: Correct mmu configuration for AOP SRAM regions NOC errors detected at runtime in AOP SRAM region strongly suggested speculative memory accesses were occurring in memory regions that either don't exist or are device memory rather than SRAM. Signed-off-by: T Michael Turney Change-Id: I6611dc614c80063c7df057b59337417c8f56fd9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/47261 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/qualcomm/sc7180/include/soc/symbols.h | 3 ++- src/soc/qualcomm/sc7180/memlayout.ld | 3 ++- src/soc/qualcomm/sc7180/mmu.c | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index 207bc4377e..1281d6370d 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -14,7 +14,8 @@ DECLARE_REGION(dram_modem_extra) DECLARE_REGION(dcb) DECLARE_REGION(pmic) DECLARE_REGION(limits_cfg) -DECLARE_REGION(aop) +DECLARE_REGION(aop_code_ram) +DECLARE_REGION(aop_data_ram) DECLARE_REGION(modem_id) #endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index 65e50d106e..482620a579 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -18,7 +18,8 @@ SECTIONS { AOPSRAM_START(0x0B000000) - REGION(aop, 0x0B000000, 0x100000, 4096) + REGION(aop_code_ram, 0x0B000000, 0x80000, 4096) + REGION(aop_data_ram, 0x0B0E0000, 0x20000, 4096) AOPSRAM_END(0x0B100000) SSRAM_START(0x14680000) diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c index b33baca0f1..8447c01b72 100644 --- a/src/soc/qualcomm/sc7180/mmu.c +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -22,5 +22,6 @@ void sc7180_mmu_init(void) void soc_mmu_dram_config_post_dram_init(void) { - mmu_config_range((void *)_aop, REGION_SIZE(aop), CACHED_RAM); + mmu_config_range((void *)_aop_code_ram, REGION_SIZE(aop_code_ram), CACHED_RAM); + mmu_config_range((void *)_aop_data_ram, REGION_SIZE(aop_data_ram), CACHED_RAM); } From 9e0dd96e7e457943629ef54b34fb14fd207069e2 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Wed, 21 Oct 2020 15:20:50 -0700 Subject: [PATCH 095/262] vc/intel/FSP2_0/CPX-SP: update to ww45 release and add watermark option Intel CPX-SP FSP ww45 release annotates default values for FSP-M UPD variables. FSPM MemRefreshWatermark option support is present in FB's CPX-SP FSP binary, but not in Intel's CPX-SP FSP binary. In FB's CPX-SP FSP binary, this option takes the space of UnusedUpdSpace0[0]. For DeltaLake mainboard, if corresponding VPD variable is set, use it to control the behavior. Such control is effective when FB's CPX-SP FSP binary is used. Signed-off-by: Jonathan Zhang Change-Id: I57ad01f33b92bf61a6a2725dd1cdbbc99c02405d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46640 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones Reviewed-by: Christian Walter --- src/mainboard/ocp/deltalake/romstage.c | 16 + src/mainboard/ocp/deltalake/vpd.h | 4 + .../intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h | 329 +++++++++--------- 3 files changed, 191 insertions(+), 158 deletions(-) diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 71a26c8789..f0cdd3dbb7 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -59,6 +59,22 @@ static void mainboard_config_upd(FSPM_UPD *mupd) "DciEn to %d\n", FSP_DCI, FSP_DCI_DEFAULT); mupd->FspmConfig.PchDciEn = FSP_DCI_DEFAULT; } + + /* + * UnusedUpdSpace0[0] is reserved for Memory Refresh Watermark. + * Following code is effective when MemRefreshWaterMark patch is added to FSP + * and when corresponding VPD variable is set. + */ + if (vpd_gets(FSPM_MEMREFRESHWATERMARK, val_str, VPD_LEN, VPD_RW_THEN_RO)) { + val = (uint8_t)atol(val_str); + if (val > 2) { + printk(BIOS_DEBUG, "Invalid MemRefreshWatermark value from VPD: " + "%d\n", val); + val = FSPM_MEMREFRESHWATERMARK_DEFAULT; + } + printk(BIOS_DEBUG, "Setting MemRefreshWatermark %d from VPD\n", val); + mupd->FspmConfig.UnusedUpdSpace0[0] = val; + } } /* Update bifurcation settings according to different Configs */ diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index 43070c2a16..71a3b09202 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -36,4 +36,8 @@ #define COREBOOT_LOG_LEVEL "coreboot_log_level" #define COREBOOT_LOG_LEVEL_DEFAULT 4 +/* FSPM MemRefreshWatermark: 0:Auto, 1: high(default), 2: low */ +#define FSPM_MEMREFRESHWATERMARK "fspm_mem_refresh_watermark" +#define FSPM_MEMREFRESHWATERMARK_DEFAULT 1 + #endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 37ff1bd620..b4d4cada49 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -151,223 +151,231 @@ typedef struct { UINT8 CustomerRevision[32]; /** Offset 0x0060 - Bus Ratio - Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO + Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO. + Default 0x1 **/ UINT8 BusRatio[8]; /** Offset 0x0068 - D2K Credit Config - Set the D2K Credit Config + Set the D2K Credit Config. 1: Min,2: Med (Default), 3: Max. 1:Min, 2:Med, 3:Max **/ UINT8 D2KCreditConfig; /** Offset 0x0069 - Snoop Throttle Config - Set the Snoop Throttle Config - 0:DIS, 1:Min, 2:Med, 3:Max + Set the Snoop Throttle Config. 0: Disable(Default), 1: Min, 2: Med, 3: Max + 0:Disable, 1:Min, 2:Med, 3:Max **/ UINT8 SnoopThrottleConfig; /** Offset 0x006A - Snoop Throttle Config - Set the Snoop All Core Config - 0:DIS, 1:EN, 2:Auto + Set the Snoop All Core Config. 0: Disable(Default), 1: Enable, 2: Auto + 0:Disable, 1:Enable, 2:Auto **/ UINT8 SnoopAllCores; -/** Offset 0x006B - Legacy VGA Soc - Socket that claims the legacy VGA range +/** Offset 0x006B - Legacy VGA Socket + Socket that claims the legacy VGA range. Default: Socket 0 **/ UINT8 LegacyVgaSoc; /** Offset 0x006C - Legacy VGA Stack - Stack that claims the legacy VGA range + Stack that claims the legacy VGA range. Default: Stack 0 **/ UINT8 LegacyVgaStack; /** Offset 0x006D - Pcie P2P Performance Mode - Determine if to enable PCIe P2P Performance Mode + Enable: Enable PCIe P2P Performance Mode, Disable(Default): Disable PCIe + P2P Performance Mode $EN_DIS **/ UINT8 P2pRelaxedOrdering; /** Offset 0x006E - Debug Print Level - Set Debug Print Level + Debug Print Level Bitmask. 0: Disable, 1: Fatal, 2: Warning, 4: Summary, 8: Detail, + 0xF: All(Default) 1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All **/ UINT8 DebugPrintLevel; /** Offset 0x006F - SNC - Enable or Disable SNC + Enable(Default) or Disable SNC $EN_DIS **/ UINT8 SncEn; /** Offset 0x0070 - UMA Clustering - Set UMA Clusters + Set number of enabled UMA Clusters. 0: Disable(Default), 2: Two Clusters, + 4: Four Clusters 0:Disable, 2:Two Clusters, 4:Four Clusters **/ UINT8 UmaClustering; /** Offset 0x0071 - IODC Mode - IODC Setup Option + IODC Mode. 0: Disable, 1: Auto(Default), 2: Push, 3: AllocFlow 4: NonAlloc, 5: WCILF 0:Disable, 1:Auto, 2:Push, 3:AllocFlow 4:NonAlloc, 5:WCILF **/ UINT8 IoDcMode; /** Offset 0x0072 - Degrade Precedence - Setup Degrade Precedence + Degrade Precedence. 0: Topology(Default), 1: Feature 0:Topology, 1:Feature **/ UINT8 DegradePrecedence; /** Offset 0x0073 - Degrade 4 Socket Preference - Setup Degrade 4 Socket Preference + Degrade 4 Socket Preference. 0: Fully Connect(Default), 1: Dual Link Ring 0:Fully Connect, 1:Dual Link Ring **/ UINT8 Degrade4SPreference; /** Offset 0x0074 - Directory Mode - Enable or Disable Directory Mode + Enable(Default) or Disable Directory Mode $EN_DIS **/ UINT8 DirectoryModeEn; /** Offset 0x0075 - XPT Prefetch Enable - Enable or Disable XPT Prefetch + XPT Prefetch. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 XptPrefetchEn; /** Offset 0x0076 - KTI Prefetch Enable - Enable or Disable KTI Prefetch + Enable(Default) or Disable KTI Prefetch $EN_DIS **/ UINT8 KtiPrefetchEn; /** Offset 0x0077 - XPT Remote Prefetch Enable - Enable or Disable XPT Remote Prefetch Enable + Enable or Disable(Default) XPT Remote Prefetch $EN_DIS **/ UINT8 XptRemotePrefetchEn; /** Offset 0x0078 - KTI FPGA - Enable or Disable KTI FPGA - $EN_DIS + Enable or Disable KTI FPGA, Default: 0x1 (Enable) **/ UINT8 KtiFpgaEnable[8]; /** Offset 0x0080 - DDRT QoS Mode - Setup DDRT QoS + DDRT QoS. 0: Mode 0(Default), 1: Mode 1, 2: Mode 2 **/ UINT8 DdrtQosMode; /** Offset 0x0081 - KTI Link Speed Mode - Choose KTI Link Speed Mode + KTI Link Speed Mode. 0: Slow, 1: Full(Default) **/ UINT8 KtiLinkSpeedMode; /** Offset 0x0082 - KTI Link Speed - Setup KTI Link Speed + KTI Link Speed. 0: 128GT, 1: 144GT, 2: 160GT, 3: Max KTI Link Speed(Default), + 4: Frequency Per Link **/ UINT8 KtiLinkSpeed; /** Offset 0x0083 - KTI Link L0p - Enable or Disable KTI Link L0p + KTI Link L0p. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 KtiLinkL0pEn; /** Offset 0x0084 - KTI Link L1 - Enable or Disable KTI Link L1 + KTI Link L1. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 KtiLinkL1En; /** Offset 0x0085 - KTI Failover - Enable or Disable KTI Failover + KTI Failover. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 KtiFailoverEn; /** Offset 0x0086 - KTI LB Enable - Enable or Disable KTI LB + Enable or Disable(Default) KTI LB $EN_DIS **/ UINT8 KtiLbEn; /** Offset 0x0087 - KTI CRC Mode - Select KTI CRC Mode + KTI CRC Mode. 0: 16bit, 1: 32bit, 2: Auto(Default) 0:16bit, 1:32bit, 2:Auto **/ UINT8 KtiCrcMode; /** Offset 0x0088 - KTI CPU Socket Hotplug - Enable or Disable KTI CPU Socket Hotplug + Enable or Disable(Default) KTI CPU Socket Hotplug $EN_DIS **/ UINT8 KtiCpuSktHotPlugEn; /** Offset 0x0089 - KTI CPU Socket HotPlug Topology - Select KTI CPU Socket HotPlug Topology + KTI CPU Socket HotPlug Topology. 0: 4 Socket(Default), 1: 8 Socket 0:4Socket, 1:8Socket **/ UINT8 KtiCpuSktHotPlugTopology; /** Offset 0x008A - KTI SKU Mismatch Check - Enable or Disable KTI SKU Mismatch Check + Enable(Default) or Disable KTI SKU Mismatch Check $EN_DIS **/ UINT8 KtiSkuMismatchCheck; /** Offset 0x008B - IRQ Threshold - Select IRQ Threshold + IRQ Threshold. 0: Disable, 1: Auto(Default), 2: Low, 3: Medium, 4: High 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High **/ UINT8 IrqThreshold; -/** Offset 0x008C - IRQ Threshold - Enable or Disable +/** Offset 0x008C - TOR threshold - Loctorem threshold normal + TOR threshold - Loctorem threshold normal. 0: Disable, 1: Auto(Default), + 2: Low, 3: Medium, 4: High 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High **/ UINT8 TorThresLoctoremNorm; /** Offset 0x008D - TOR threshold - Loctorem threshold empty - Select TOR threshold - Loctorem threshold empty + TOR threshold - Loctorem threshold empty. 0: Disable, 1: Auto(Default), + 2: Low, 3: Medium, 4: High 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High **/ UINT8 TorThresLoctoremEmpty; /** Offset 0x008E - MBA BW Calibration - MBA BW Calibration setting + MBA BW Calibration setting. 0: Linear, 1: Biased, 2: Legacy, 3: Auto(Default) 0:Linear, 1:Biased, 2:Legacy, 3:Auto **/ UINT8 MbeBwCal; /** Offset 0x008F - TSC Sync in Sockets - Enable or Disable TSC Sync in Sockets + TSC Sync in Sockets. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 TscSyncEn; /** Offset 0x0090 - HA A to S directory optimization - Enable or Disable HA A to S directory optimization + HA A to S directory optimization. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 StaleAtoSOptEn; /** Offset 0x0091 - LLC Deadline Allocation - Enable or Disable LLC Deadline Allocation + Enable(Default) or Disable LLC Deadline Allocation $EN_DIS **/ UINT8 LLCDeadLineAlloc; /** Offset 0x0092 - Split Lock - Enable or Disable Split Lock + Split Lock. 0: Disable(Default), 1: Enable, 2: Auto **/ UINT8 SplitLock; /** Offset 0x0093 - MMCFG Base Address - Setup MMCFG Base Address - 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto + MMCFG Base Address. 0: 1GB, 1: 1.5GB, 2: 1.75GB, 3: 2GB, 4: 2.25GB, 5: 3GB, 6: + Auto(Default) + 0:1GB, 1:1.5GB, 2:1.75GB, 3:2GB, 4:2.25GB, 5:3GB, 6:Auto **/ UINT8 mmCfgBase; /** Offset 0x0094 - MMCFG Size - Select MMCFG Size - 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto + Select MMCFG Size. 0: 64MB, 1: 128MB, 2: 256MB, 3: 512MB, 4: 1GB, 5: 2GB, 6: + Auto(Default) + 0:64MB, 1:128MB, 2:256MB, 3:512MB, 4:1GB, 5:2GB, 6: Auto **/ UINT8 mmCfgSize; @@ -375,37 +383,44 @@ typedef struct { **/ UINT8 UnusedUpdSpace0[3]; +/* + * UnusedUpdSpace0[0] is reserved for following UPD variable: + * Offset 0x0095 - Usage type for Memory Refresh Watermark + * Select Memory Refresh Watermark, 0: Auto, 1: High(default), 2: Low + UINT8 MemRefreshWaterMark; + */ + /** Offset 0x0098 - MMIO High Base Address - MMIO High Base Address, a hex number for Bit[51:32] + MMIO High Base Address, a hex number for Bit[51:32]. Default: 0x6 (Gives 0x200) **/ UINT32 mmiohBase; /** Offset 0x009C - CPU Physical Address Limit - CPU Physical Address Limit + Enable(Default) or Disable CPU Physical Address Limit 0:Disable, 1:Enable **/ UINT8 CpuPaLimit; /** Offset 0x009D - High Gap - Enable or Disable High Gap + Enable or Disable(Default) High Gap $EN_DIS **/ UINT8 highGap; /** Offset 0x009E - MMIO High Size MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space - per CPU. Range 1-1024 + per CPU. Range 1-1024, Default: 3 **/ UINT16 mmiohSize; -/** Offset 0x00A0 - } TYPE:{Combo - Enable or Disable +/** Offset 0x00A0 - ISOC + Enable(Default) or Disable ISOC $EN_DIS **/ UINT8 isocEn; /** Offset 0x00A1 - DCA - Enable or Disable DCA + Enable or Disable(Default) DCA $EN_DIS **/ UINT8 dcaEn; @@ -414,289 +429,287 @@ typedef struct { **/ UINT8 UnusedUpdSpace1[2]; -/** Offset 0x00A4 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00A4 - BoardTypeBitmask + Board Type Bitmask. Default: 0x1 **/ UINT32 BoardTypeBitmask; -/** Offset 0x00A8 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00A8 - AllLanesPtr + Pointer to array of ALL_LANES_EPARAM_LINK_INFO **/ UINT32 AllLanesPtr; -/** Offset 0x00AC - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00AC - PerLanePtr + Pointer to array of PER_LANE_EPARAM_LINK_INFO **/ UINT32 PerLanePtr; -/** Offset 0x00B0 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00B0 - AllLanesSizeOfTable + Number of elements in AllLanesPtr array. **/ UINT32 AllLanesSizeOfTable; -/** Offset 0x00B4 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00B4 - PerLaneSizeOfTable + Number of elements in PerLanePtr array. **/ UINT32 PerLaneSizeOfTable; -/** Offset 0x00B8 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00B8 - WaitTimeForPSBP + Number of milliseconds to wait for remote CPUs to initialize. Default: 30 sec **/ UINT32 WaitTimeForPSBP; -/** Offset 0x00BC - } TYPE:{Combo - Enable or Disable +/** Offset 0x00BC - IsKtiNvramDataReady + IsKtiNvramDataReady. Default: Disable $EN_DIS **/ UINT8 IsKtiNvramDataReady; -/** Offset 0x00BD - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00BD - BoardId + Board ID **/ UINT8 BoardId; -/** Offset 0x00BE - } TYPE:{Combo - Enable or Disable +/** Offset 0x00BE - WaSerializationEn + Enable(Default) or Disable BIOS serialization WA $EN_DIS **/ UINT8 WaSerializationEn; -/** Offset 0x00BF - } TYPE:{Combo - Enable or Disable +/** Offset 0x00BF - KtiInEnableMktme + Enable(Default) or Disable MkTme status decides D2Kti feature state $EN_DIS **/ UINT8 KtiInEnableMktme; -/** Offset 0x00C0 - Usage type for Processor VmxEnable Function - Processor VmxEnable Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C0 - Processor VmxEnable Function + Enable(Default) or Disable Processor VmxEnable Function $EN_DIS **/ UINT8 VmxEnable; -/** Offset 0x00C1 - Usage type for Processor X2apic Function - Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C1 - Processor X2apic Function + Enable(Default) or Disable Processor X2apic Function + $EN_DIS **/ UINT8 X2apic; -/** Offset 0x00C2 - Usage type for DDR frequency limit - Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C2 - DDR frequency limit + Enable(Default) or Disable Processor X2apic Function **/ UINT8 DdrFreqLimit; -/** Offset 0x00C3 - Usage type for Memory Serial Debug Message Level - Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C3 - Memory Serial Debug Message Level + Enable(Default) or Disable Processor X2apic Function **/ UINT8 serialDebugMsgLvl; /** Offset 0x00C4 - IIO ConfigIOU0 ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU0[8]; /** Offset 0x00CC - IIO ConfigIOU1 ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU1[8]; /** Offset 0x00D4 - IIO ConfigIOU2 ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU2[8]; /** Offset 0x00DC - IIO ConfigIOU3 ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU3[8]; /** Offset 0x00E4 - IIO ConfigIOU4 ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU4[8]; -/** Offset 0x00EC - Usage type for IIO PCIE Config Table Ptr - IIO PCIE Config Table Ptr +/** Offset 0x00EC - IIO PCIE Config Table Ptr + Pointer to array of UPD_IIO_PCIE_PORT_CONFIG **/ UINT32 IioPcieConfigTablePtr; -/** Offset 0x00F0 - Usage type for IIO PCIE Config Table Number - IIO PCIE Config Table Number +/** Offset 0x00F0 - IIO PCIE Config Table Number + Number of elements in IioPcieConfigTablePtr array. **/ UINT32 IioPcieConfigTableNumber; -/** Offset 0x00F4 - Usage type for IIO PCIE Root Port Enable or Disable - IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, - the value is 0x00 +/** Offset 0x00F4 - IIO PCIE Root Port Enable + Enable(Default) or Disable IIO PCH rootport **/ UINT8 IIOPcieRootPortEnable; -/** Offset 0x00F5 - Usage type for IIO DeEmphasis - IIO DeEmphasis +/** Offset 0x00F5 - IIO DeEmphasis + IIO DeEmphasis. Default: 0x1 **/ UINT8 DeEmphasis; -/** Offset 0x00F6 - Usage type for IIO PCIE Root Port link speed - IIO root port link speed +/** Offset 0x00F6 - IIO PCIe Root Port Link Speed + IIO PCIe Root Port Link Speed. 0: Auto(Default), 1: Gen1, 2: Gen2, 3: Gen3, 4: Gen4 + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3, 4:Gen4 **/ UINT8 IIOPciePortLinkSpeed; -/** Offset 0x00F7 - Usage type for IIO PCIE Root Port Max Payload - IIO Root Port Max Payload +/** Offset 0x00F7 - IIO PCIe Root Port Max Payload + IIO PCIe Root Port Max Payload. 0: 128B, 1: 256B, 2: 512B, 7: Auto(Default) + 0:128B, 1: 256B, 2:512B, 7:Auto **/ UINT8 IIOPcieMaxPayload; -/** Offset 0x00F8 - Usage type for IIO DfxDnTxPreset - IIO DfxDnTxPreset +/** Offset 0x00F8 - IIO DfxDnTxPreset + IIO Downstream Transmitter Preset. Default: Auto(0xFF), otherwise preset 0-10 **/ UINT8 DfxDnTxPreset; -/** Offset 0x00F9 - Usage type for IIO DfxRxPreset - IIO DfxRxPreset +/** Offset 0x00F9 - IIO DfxRxPreset + IIO Downstream Reciever Preset. Default: Auto(0xFF), otherwise preset 0-10 **/ UINT8 DfxRxPreset; -/** Offset 0x00FA - Usage type for IIO DfxUpTxPreset - IIO DfxUpTxPreset +/** Offset 0x00FA - IIO DfxUpTxPreset + IIO Upstream Transmitter Preset. Default: Auto(0xFF), otherwise preset 0-10 **/ UINT8 DfxUpTxPreset; -/** Offset 0x00FB - Usage type for IIO PcieCommonClock - IIO PcieCommonClock +/** Offset 0x00FB - IIO PCIe Common Clock + IIO PCIe Common Clock. 0: Disable, 1: Enable(Default), 2: Auto **/ UINT8 PcieCommonClock; -/** Offset 0x00FC - Usage type for IIO NtbPpd - IIO NtbPpd +/** Offset 0x00FC - IIO Non-Transparent Port Definition + IIO Non-Transparent Port Definition. 0: Transparent(Default), 1: Non-Transparent + Bridge, 2: Non-Transparent Root Port **/ UINT8 NtbPpd; -/** Offset 0x00FD - Usage type for IIO NtbBarSizeOverride - IIO NtbBarSizeOverride +/** Offset 0x00FD - IIO Non-Transparent Bridge BAR Size Override + Enable or Disable(Default) IIO Non-Transparent Bridge BAR Size Override. **/ UINT8 NtbBarSizeOverride; -/** Offset 0x00FE - Usage type for IIO NtbSplitBar - IIO NtbSplitBar +/** Offset 0x00FE - IIO Non-Transparent Bridge Split BAR Mode + Enable or Disable(Default) IIO Non-Transparent Bridge Split BAR Mode **/ UINT8 NtbSplitBar; -/** Offset 0x00FF - Usage type for IIO NtbBarSizeImBar1 - IIO NtbBarSizeImBar1 +/** Offset 0x00FF - IIO NtbBarSizeImBar1 + IIO NtbBarSizeImBar1. Default: 0x16 **/ UINT8 NtbBarSizeImBar1; -/** Offset 0x0100 - Usage type for IIO NtbBarSizeImBar2 - IIO PNtbBarSizeImBar2 +/** Offset 0x0100 - IIO NtbBarSizeImBar2 + IIO PNtbBarSizeImBar2. Default: 0x16 **/ UINT8 NtbBarSizeImBar2; -/** Offset 0x0101 - Usage type for IIO NtbBarSizeImBar2_0 - IIO PNtbBarSizeImBar2_0 +/** Offset 0x0101 - IIO NtbBarSizeImBar2_0 + IIO PNtbBarSizeImBar2_0. Default: 0x0C **/ UINT8 NtbBarSizeImBar2_0; -/** Offset 0x0102 - Usage type for IIO NtbBarSizeImBar2_1 - IIO NtbBarSizeImBar2_1 +/** Offset 0x0102 - IIO NtbBarSizeImBar2_1 + IIO NtbBarSizeImBar2_1. Default: 0x0C **/ UINT8 NtbBarSizeImBar2_1; -/** Offset 0x0103 - Usage type for IIO NtbBarSizeEmBarSZ1 - IIO NtbBarSizeEmBarSZ1 +/** Offset 0x0103 - IIO NtbBarSizeEmBarSZ1 + IIO NtbBarSizeEmBarSZ1. . Default: 0x16 **/ UINT8 NtbBarSizeEmBarSZ1; -/** Offset 0x0104 - Usage type for IIO NtbBarSizeEmBarSZ2 - IIO NtbBarSizeEmBarSZ2 +/** Offset 0x0104 - IIO NtbBarSizeEmBarSZ2 + IIO NtbBarSizeEmBarSZ2. . Default: 0x16 **/ UINT8 NtbBarSizeEmBarSZ2; -/** Offset 0x0105 - Usage type for IIO NtbBarSizeEmBarSZ2_0 - IIO NtbBarSizeEmBarSZ2_0 +/** Offset 0x0105 - IIO NtbBarSizeEmBarSZ2_0 + IIO NtbBarSizeEmBarSZ2_0. . Default: 0x0C **/ UINT8 NtbBarSizeEmBarSZ2_0; -/** Offset 0x0106 - Usage type for IIO NtbBarSizeEmBarSZ2_1 - IIO NtbBarSizeEmBarSZ2_1 +/** Offset 0x0106 - IIO NtbBarSizeEmBarSZ2_1 + IIO NtbBarSizeEmBarSZ2_1. . Default: 0x0C **/ UINT8 NtbBarSizeEmBarSZ2_1; -/** Offset 0x0107 - Usage type for IIO NtbXlinkCtlOverride - IIO NtbXlinkCtlOverride +/** Offset 0x0107 - IIO Non-Transparent Cross Link Override + IIO Non-Transparent Cross Link Override. 1:Operate as RP, 2:Operate as NTB-NTB (NT + Port), 3:Operate as NTB-> DSP (NTB EP)(Default) **/ UINT8 NtbXlinkCtlOverride; -/** Offset 0x0108 - Usage type for IIO VT-D Function - IIO VT-D Function, if supported, the value is 0x01, if not supported, the value is 0x00 +/** Offset 0x0108 - VT-d Support + Enable or Disable(Default) VT-d Support **/ UINT8 VtdSupport; -/** Offset 0x0109 - Usage type for IIO Pcie Port Hide +/** Offset 0x0109 - IIO PCIe Port Hide Hide or visible for IIO Pcie Port, 1 : Hide, 0 : Visible **/ UINT8 PEXPHIDE; -/** Offset 0x010A - Usage type for IIO Pcie Port Menu Hide - Hide or visible for IIO Pcie Port Menu, 1 : Hide, 0 : Visible +/** Offset 0x010A - IIO Pcie Port Menu Hide + Hide or visible for IIO PCIe Port Menu, 1 : Hide, 0 : Visible **/ UINT8 HidePEXPMenu; /** Offset 0x010B - PchSirqMode - Enable or Disable PchSirqMode + PchSirqMode. 0: Quiet Mode(Default) 1: Continuous Mode **/ UINT8 PchSirqMode; /** Offset 0x010C - PchAdrEn - Enable or Disable PchAdr + PchAdr 0:PLATFORM POR, 1:FORCE ENABLE(Default), 2:FORCE DISABLE **/ UINT8 PchAdrEn; /** Offset 0x010D - ThermalDeviceEnable - Enable or Disable ThermalDeviceEnable with PCI or ACPI mode + Thermal Device Mode. 0: Disable, 1: Enabled in PCI mode, 2: Enabled in ACPI + mode(Default) **/ UINT8 ThermalDeviceEnable; -/** Offset 0x010E - } TYPE:{Combo - Root port swapping based on device connection status : TRUE or FALSE +/** Offset 0x010E - PchPcieRootPortFunctionSwap + Root port swapping based on device connection status : TRUE(Default) or FALSE TRUE : 0x01, FALSE : 0x00 **/ UINT8 PchPcieRootPortFunctionSwap; /** Offset 0x010F - PCH PCIE PLL Ssc Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC - of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF + of 2.0%), Auto : 0xFE(Set to hardware default), Disable(Default) : 0xFF **/ UINT8 PchPciePllSsc; -/** Offset 0x0110 - Usage type for PCH PCIE Root Port Index +/** Offset 0x0110 - PCH PCIE Root Port Index Index assigned to every PCH PCIE Root Port **/ UINT8 PchPciePortIndex[20]; -/** Offset 0x0124 - Usage type for PCH PCIE Root Port Enable or Disable - 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, - the value is 0x00 +/** Offset 0x0124 - PCH PCIE Root Port Enable or Disable + 0-19: PCH rootport, if port is enabled(Default), the value is 0x01, if the port + is disabled, the value is 0x00 **/ UINT8 PchPcieForceEnable[20]; -/** Offset 0x0138 - Usage type for PCH PCIE Root Port Link Speed - 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie - Gen2 Speed, 0x03 : Pcie Gen3 Speed +/** Offset 0x0138 - PCH PCIE Root Port Link Speed + 0-19: PCH rootport, 0x00 : Pcie Auto Speed(Default), 0x01 : Pcie Gen1 Speed, 0x02 + : Pcie Gen2 Speed, 0x03 : Pcie Gen3 Speed **/ UINT8 PchPciePortLinkSpeed[20]; /** Offset 0x014C - PchDciEn - Enable or Disable Pch DciEn + Enable or Disable(Default) PCH DCI **/ UINT8 PchDciEn; @@ -706,7 +719,7 @@ typedef struct { UINT8 MeUmaEnable; /** Offset 0x014E - SerialIoUartDebugEnable - Enable SerialIo Uart debug library in FSP. + Enable(Default) or Disable SerialIo Uart debug library in FSP. 0:Disable, 1:Enable **/ UINT8 SerialIoUartDebugEnable; From 14e34fb10b52ddf078f45d6b5791b285a8d4eee1 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Fri, 6 Nov 2020 14:39:18 +0530 Subject: [PATCH 096/262] mb/intel/adlrvp: Configure the HPD GPIO's This patch configures the HPD1 and HPD2 GPIO's. BUG=b:170607415 TEST=Built and booted adlrvp. Verified the hotplug functionality is working. Change-Id: Ied2d4c56220212a15103e9a2fbd01ce6f0811a74 Signed-off-by: V Sowmya Reviewed-on: https://review.coreboot.org/c/coreboot/+/47290 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c index e142e88e57..c7029fc10b 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c @@ -277,6 +277,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), + /* HPD_1 (A19) and HPD_2 (A20) pins */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* IMGCLKOUT */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), From 73caae977213b8d25616dcaa043259c7b2dc2a60 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Fri, 6 Nov 2020 13:47:04 +0530 Subject: [PATCH 097/262] mb/intel/adlrvp: Enable TCSS xDCI, TBT PCIe RP and DMA controllers This patch enables TCSS xDCI, TBT PCIe root ports and DMA controllers for ADLRVP. BUG=b:170607415 TEST=Built and booted on ADLRVP. Change-Id: Iabd6cc7c589d1c20cde9d66c0a63e2cf16316b33 Signed-off-by: V Sowmya Reviewed-on: https://review.coreboot.org/c/coreboot/+/47288 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- .../intel/adlrvp/variants/adlrvp_p/devicetree.cb | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index ea75d5d161..44c324bcbb 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -173,17 +173,17 @@ chip soc/intel/alderlake device pci 04.0 on end # DPTF device pci 05.0 on end # IPU device pci 06.0 on end # PEG60 - device pci 07.0 off end # TBT_PCIe0 - device pci 07.1 off end # TBT_PCIe1 - device pci 07.2 off end # TBT_PCIe2 - device pci 07.3 off end # TBT_PCIe3 + device pci 07.0 on end # TBT_PCIe0 + device pci 07.1 on end # TBT_PCIe1 + device pci 07.2 on end # TBT_PCIe2 + device pci 07.3 on end # TBT_PCIe3 device pci 08.0 off end # GNA device pci 09.0 off end # NPK device pci 0a.0 off end # Crash-log SRAM device pci 0d.0 on end # USB xHCI - device pci 0d.1 off end # USB xDCI (OTG) - device pci 0d.2 off end # TBT DMA0 - device pci 0d.3 off end # TBT DMA1 + device pci 0d.1 on end # USB xDCI (OTG) + device pci 0d.2 on end # TBT DMA0 + device pci 0d.3 on end # TBT DMA1 device pci 0e.0 off end # VMD device pci 10.0 off end device pci 10.1 off end From f2de1e7e19dccb1901c93ff5093360566f6b88e8 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Thu, 5 Nov 2020 14:18:38 +0530 Subject: [PATCH 098/262] mb/intel: Enable ALC711 Audio codec over SNDW0 link The patch enables ALC711 Audio codec. Test=Verified on ADL RVP. Signed-off-by: Sridhar Siricilla Change-Id: I73f480dad1047cebd7ffc66e0104ff10cacc300b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47278 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: V Sowmya --- src/mainboard/intel/adlrvp/Kconfig | 1 + src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb | 5 +++++ src/soc/intel/alderlake/soundwire.c | 3 +-- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 97b4bf7a2b..2a3dbb021c 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_SPI_ACPI select SOC_INTEL_ALDERLAKE select HAVE_SPD_IN_CBFS + select DRIVERS_SOUNDWIRE_ALC711 config CHROMEOS bool diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index 44c324bcbb..ce55fa3914 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -258,6 +258,11 @@ chip soc/intel/alderlake device pci 1f.3 on chip drivers/intel/soundwire device generic 0 on + chip drivers/soundwire/alc711 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end end end end # Intel Audio SNDW diff --git a/src/soc/intel/alderlake/soundwire.c b/src/soc/intel/alderlake/soundwire.c index 38a2c37758..9899df36c2 100644 --- a/src/soc/intel/alderlake/soundwire.c +++ b/src/soc/intel/alderlake/soundwire.c @@ -37,8 +37,7 @@ static const struct soundwire_link link_xtal_24 = { static struct intel_soundwire_controller intel_controller = { .acpi_address = 0x40000000, .sdw = { - /* TODO: Verified Audio in nocodec mode, add codec support */ - .master_list_count = 0 + .master_list_count = 1 } }; From 344a1bd43c63dbfeb3cff04e63d531f32242aba4 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Thu, 5 Nov 2020 21:36:39 +0530 Subject: [PATCH 099/262] mb/intel/adlrvp: Configure GPIOs to enable DMIC The patch configures GPIO pins to enable DMIC. Signed-off-by: Sridhar Siricilla Change-Id: I2907737071f7d6b3c88c492d90edf8455d1fa50a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47279 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: V Sowmya --- src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c index c7029fc10b..f91b94faf4 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c @@ -224,17 +224,17 @@ static const struct pad_config gpio_table[] = { /* SNDW1_DATA */ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SNDW2_CLK */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* SNDW2_DATA */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* SNDW3_CLK */ - PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* SNDW3_DATA */ - PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* SNDW4_CLK */ - PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* SNDW4_DATA */ - PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), From 4b519f7c62d55b06c1d99ee6b39a0226475777ad Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 30 Oct 2020 17:36:16 +0100 Subject: [PATCH 100/262] sb/intel/*/lpc.c: Don't try to write read-only PCICMD bits For all these southbridges, the lower nibble of PCICMD is read-only. Tested on Asrock B85M Pro4 (Lynxpoint-H), LPC's PCICMD does not change. Change-Id: Ib3b16b1b9651f7f3bd06ff8bc27dafd8a323e93c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47038 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/bd82x6x/lpc.c | 5 ----- src/southbridge/intel/i82801dx/lpc.c | 5 ----- src/southbridge/intel/i82801gx/lpc.c | 5 ----- src/southbridge/intel/i82801ix/lpc.c | 5 ----- src/southbridge/intel/i82801jx/lpc.c | 5 ----- src/southbridge/intel/ibexpeak/lpc.c | 5 ----- src/southbridge/intel/lynxpoint/lpc.c | 5 ----- 7 files changed, 35 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index df5625afa5..a498f870a0 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -519,11 +519,6 @@ static void lpc_init(struct device *dev) /* Print detected platform */ report_pch_info(dev); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* IO APIC initialization. */ pch_enable_ioapic(dev); diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index dec12666fc..f207c11556 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -252,11 +252,6 @@ static void enable_hpet(struct device *dev) static void lpc_init(struct device *dev) { - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - i82801dx_enable_acpi(dev); /* IO APIC initialization. */ i82801dx_enable_ioapic(dev); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index eb59eb031c..721735cb15 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -341,11 +341,6 @@ static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "i82801gx: %s\n", __func__); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* IO APIC initialization. */ i82801gx_enable_ioapic(dev); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index ad7141ac49..652da54103 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -355,11 +355,6 @@ static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "i82801ix: %s\n", __func__); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* IO APIC initialization. */ i82801ix_enable_apic(dev); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 2f7b516a2a..1f4cf29187 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -347,11 +347,6 @@ static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "i82801jx: %s\n", __func__); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* IO APIC initialization. */ i82801jx_enable_apic(dev); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 8269dd9f22..dddecd79d0 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -433,11 +433,6 @@ static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: %s\n", __func__); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* IO APIC initialization. */ pch_enable_ioapic(dev); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4286e6ca0a..2872a0b556 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -505,11 +505,6 @@ static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: %s\n", __func__); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* IO APIC initialization. */ pch_enable_ioapic(dev); From f47117134d0b19914eb266af2f4f8094ca7621e6 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 4 Nov 2020 00:38:28 +0100 Subject: [PATCH 101/262] sb/intel: Don't set ACPI_EN twice It is already done once when enabling PMBASE in early init. Change-Id: I14289c9164ee1488c192fce721d86c89fa5cc736 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47207 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/bd82x6x/early_pch.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 3 --- src/southbridge/intel/i82801gx/lpc.c | 3 --- src/southbridge/intel/ibexpeak/early_pch.c | 2 +- src/southbridge/intel/ibexpeak/lpc.c | 3 --- src/southbridge/intel/lynxpoint/early_pch.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 3 --- 7 files changed, 3 insertions(+), 15 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 452adb1033..767d3ad936 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -222,7 +222,7 @@ static void pch_enable_bars(void) pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index a498f870a0..8af80654e9 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -44,9 +44,6 @@ static void pch_enable_ioapic(struct device *dev) pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); - /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 721735cb15..9ac894254c 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -35,9 +35,6 @@ */ static void i82801gx_enable_ioapic(struct device *dev) { - /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x02); /* diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index ace09e292f..df380c5bde 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -33,7 +33,7 @@ void ibexpeak_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); printk(BIOS_DEBUG, " done.\n"); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index dddecd79d0..d2a3404880 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -39,9 +39,6 @@ static void pch_enable_ioapic(struct device *dev) { u32 reg32; - /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x01); /* affirm full set of redirection table entries ("write once") */ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 465aa1e710..8cc6a8760c 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -40,7 +40,7 @@ static void pch_enable_bars(void) pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 2872a0b556..2db4b59006 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -41,9 +41,6 @@ static void pch_enable_ioapic(struct device *dev) pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); - /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ From 244a425efdd2b291ba4e347e4b79181212a5bf52 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 5 Nov 2020 10:42:20 +0100 Subject: [PATCH 102/262] sb/intel/lynxpoint: Correct SATA DTLE IOBP registers Testing shows that these registers are backwards. Use the definitions from Broadwell instead. All affected boards use the same value for both. Change-Id: Ie47c9fddc2e9e15ce4c64821ea3a69356ac31b1a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47234 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/lynxpoint/pch.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 66cd05e66a..429dcc032b 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -267,10 +267,10 @@ void mainboard_config_rcba(void); /* SATA IOBP Registers */ #define SATA_IOBP_SP0G3IR 0xea000151 #define SATA_IOBP_SP1G3IR 0xea000051 -#define SATA_IOBP_SP0DTLE_DATA 0xea002550 -#define SATA_IOBP_SP0DTLE_EDGE 0xea002554 -#define SATA_IOBP_SP1DTLE_DATA 0xea002750 -#define SATA_IOBP_SP1DTLE_EDGE 0xea002754 +#define SATA_IOBP_SP0DTLE_DATA 0xea002750 +#define SATA_IOBP_SP0DTLE_EDGE 0xea002754 +#define SATA_IOBP_SP1DTLE_DATA 0xea002550 +#define SATA_IOBP_SP1DTLE_EDGE 0xea002554 #define SATA_DTLE_MASK 0xF #define SATA_DTLE_DATA_SHIFT 24 From a7174b7c1ddd227969961537f8363954e756166e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 30 Oct 2020 20:23:41 +0100 Subject: [PATCH 103/262] sb/intel/lynxpoint/lpc.c: Correct GPI routing check Code does not match comment, but this time the comment is right. Change-Id: I4e277a802c68c8a4e858b2e33e7ec69b41dd9773 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47044 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/lpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 2db4b59006..4464f919ee 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -243,7 +243,7 @@ static void pch_power_options(struct device *dev) * Set the board's GPI routing on LynxPoint-H. * This is done as part of GPIO configuration on LynxPoint-LP. */ - if (pch_is_lp()) + if (!pch_is_lp()) pch_gpi_routing(dev, config); /* GPE setup based on device tree configuration */ From 1464a059332c7f9ff9a80455309265bb285c58c8 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 30 Oct 2020 20:21:37 +0100 Subject: [PATCH 104/262] sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` function Change-Id: I957556bcb3f2d793ed2d9a9c966b2081f9be090c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47042 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/lpc.c | 38 +++++++++++++-------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4464f919ee..232ad2ec95 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -70,6 +70,25 @@ static void pch_enable_serial_irqs(struct device *dev) #endif } +static void enable_hpet(struct device *const dev) +{ + u32 reg32; + size_t i; + + /* Assign unique bus/dev/fn for each HPET */ + for (i = 0; i < 8; ++i) + pci_write_config16(dev, LPC_HnBDF(i), + PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); + + /* Move HPET to default address 0xfed00000 and enable it */ + reg32 = RCBA32(HPTC); + reg32 |= (1 << 7); // HPET Address Enable + reg32 &= ~(3 << 0); + RCBA32(HPTC) = reg32; + /* Read it back to stick. It's affected by posted write syndrome. */ + RCBA32(HPTC); +} + /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved * 0x01 - 0001 = Reserved @@ -371,25 +390,6 @@ static void lpt_lp_pm_init(struct device *dev) RCBA32_OR(0x33c8, (1 << 15)); } -static void enable_hpet(struct device *const dev) -{ - u32 reg32; - size_t i; - - /* Assign unique bus/dev/fn for each HPET */ - for (i = 0; i < 8; ++i) - pci_write_config16(dev, LPC_HnBDF(i), - PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); - - /* Move HPET to default address 0xfed00000 and enable it */ - reg32 = RCBA32(HPTC); - reg32 |= (1 << 7); // HPET Address Enable - reg32 &= ~(3 << 0); - RCBA32(HPTC) = reg32; - /* Read it back to stick. It's affected by posted write syndrome. */ - RCBA32(HPTC); -} - static void enable_clock_gating(struct device *dev) { /* LynxPoint Mobile */ From a575759c401d7bebaeb8909d5bce6a78edfb0bb4 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 5 Nov 2020 11:35:54 +0100 Subject: [PATCH 105/262] sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled Setting registers 64h[19:18] = 2 and 68h[14:13] = 3 enables OBFF, and setting registers 64h[19:18] = 0 and 68h[14:13] = 0 disables OBFF. Register at offset 0x64 is DCAP2, and offset 0x68 is DCTL2. However, current code doesn't account for this. The result is that register 64h[19:18] = 2 and 68h[14:13] = 0, which means the hardware is OBFF-capable but support is disabled, which makes no sense. Given that reference code and Broadwell both disable OBFF, disable it here too. Change-Id: I6c1cafdb435ee22909b077128b3ae5bde5543039 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47240 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/lynxpoint/pcie.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 4a245b1899..19eb9fa396 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -645,9 +645,9 @@ static void pch_pcie_early(struct device *dev) pci_and_config32(dev, 0x338, ~(1 << 26)); } - /* Enable LTR in Root Port. */ - pci_or_config32(dev, 0x64, 1 << 11); - pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); + /* Enable LTR in Root Port. Disable OBFF. */ + pci_update_config32(dev, 0x64, ~(3 << 18), 1 << 11); + pci_update_config16(dev, 0x68, ~(3 << 13), 1 << 10); pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); From 092245dfbbf574cd9a3ea101fd77f6aa010ffd46 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Fri, 6 Nov 2020 10:45:38 -0700 Subject: [PATCH 106/262] mainboard/ocp/tiogapass: Set longer BMC timeout The BMC isn't always ready in 60 seconds if it printing debug output. Give it 90 seconds to finish before timing out in coreboot. Change-Id: I3932d3e8fad067e8971e82b45b499801fc78079f Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/47306 Tested-by: build bot (Jenkins) Reviewed-by: Jay Talbott Reviewed-by: Arthur Heymans Reviewed-by: Javier Galindo --- src/mainboard/ocp/tiogapass/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 33f4090751..008633b1a1 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -74,7 +74,7 @@ chip soc/intel/xeon_sp/skx chip drivers/ipmi # BMC KCS device pnp ca2.0 on end register "bmc_i2c_address" = "0x20" - register "bmc_boot_timeout" = "60" + register "bmc_boot_timeout" = "90" end end # Intel Corporation C621 Series Chipset LPC/eSPI Controller device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller From d13d7c27353cade44f0718d956f2689aa5d4f391 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Tue, 3 Nov 2020 09:55:02 -0700 Subject: [PATCH 107/262] mainboard/ocp/deltalake: Use xeon_sp pch.asl Use the xeon_sp pch.asl to pickup the common block lpc.asl. This allows deltalake to pick up any general pch asl updates. Currently, generates the same asl. Change-Id: I5005032b030d288fdf5ca2f99d21fe8e6c752037 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/47304 Reviewed-by: Jay Talbott Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/ocp/deltalake/dsdt.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl index 6afd4cb74f..1541134e72 100644 --- a/src/mainboard/ocp/deltalake/dsdt.asl +++ b/src/mainboard/ocp/deltalake/dsdt.asl @@ -24,6 +24,6 @@ DefinitionBlock( // LPC related entries Scope (\_SB.PC00) { - #include + #include } } From fc62013fd11662e8627ba55694c611e994705d0a Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Tue, 3 Nov 2020 09:58:26 -0700 Subject: [PATCH 108/262] mainboard/ocp/tiogapass: Add xeon_sp pch.asl Use the xeon_sp pch.asl to include the intel common lpc.asl. Change-Id: I22ee9d325888808a9c775ecee0591b661e2bba4e Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/47305 Tested-by: build bot (Jenkins) Reviewed-by: Jay Talbott Reviewed-by: Javier Galindo Reviewed-by: Arthur Heymans --- src/mainboard/ocp/tiogapass/dsdt.asl | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index ddc716093f..7905a9c5ef 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -15,4 +15,8 @@ DefinitionBlock( #include #include #include + Scope (\_SB.PC00) + { + #include + } } From b6ef297564b0ea173d889a47fbd5a811de532e99 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 6 Nov 2020 00:27:23 +0100 Subject: [PATCH 109/262] soc/amd/common/psp: expand CPU family names in Kconfig help text Expand fam17h to family 17h to make the help text slightly easier to understand and add family 19h to the description of SOC_AMD_COMMON_BLOCK_PSP_GEN2. Change-Id: I9284c9c638e1d217d4605523dde004781f4343f9 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47275 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/common/block/psp/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index bf0477b5ac..85ec9872a9 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -11,14 +11,14 @@ config SOC_AMD_COMMON_BLOCK_PSP_GEN1 default n select SOC_AMD_COMMON_BLOCK_PSP help - Used by the PSP in AMD systems before fam17h, e.g. stoneyridge. + Used by the PSP in AMD systems before family 17h, e.g. stoneyridge. config SOC_AMD_COMMON_BLOCK_PSP_GEN2 bool default n select SOC_AMD_COMMON_BLOCK_PSP help - Used by the PSP in AMD fam17h CPUs and possibly newer ones. + Used by the PSP in AMD family 17h, 19h and possibly newer CPUs. config SOC_AMD_PSP_SELECTABLE_SMU_FW bool From 3190ba863daecf6ac9300f57beb8c7eae74b8c50 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 5 Nov 2020 11:20:19 -0700 Subject: [PATCH 110/262] soc/amd/common: Don't program GPIOs if the table isn't set Currently, there's no check for the table being programmed. This skips programming a table if the table size is zero, or the pointer to the table has been set to NULL. BUG=None TEST=Set table pointer to NULL, table doesn't run. BRANCH=Zork Signed-off-by: Martin Roth Change-Id: I7d09b47e7d619428b64cc0695f220fb64c71ef4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/47307 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Furquan Shaikh --- src/soc/amd/common/block/gpio_banks/gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 74ea696448..91773d9966 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -187,6 +187,8 @@ void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) size_t gev_items; const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && ENV_SEPARATE_VERSTAGE); + if (!gpio_list_ptr || !size) + return; /* * Disable blocking wake/interrupt status generation while updating From c98baa7a80ff5bc0a2f8c4d2a5fa24cd8f139979 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Wed, 4 Nov 2020 21:49:49 -0700 Subject: [PATCH 111/262] libpayload: Add compiler.h to compiler parameters Headers in libpayload define various structs like so: struct struct_name { ... } __packed; However, these header files do not include the compiler.h macro that defines what __packed is, so they are actually defining a variable named __packed and *not* declaring a packed struct. This leads to defining the same variable multiple times, which was caught by GCC 10. Add compiler.h to the compiler parameters so it is included in all files automatically. Signed-off-by: Jacob Garber Change-Id: Ia67182520dc94149e06fe9e03a14b3fc2ee29973 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47153 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- payloads/libpayload/Makefile.inc | 3 ++- payloads/libpayload/bin/lpgcc | 3 ++- payloads/libpayload/include/cbfs_core.h | 1 - payloads/libpayload/include/libpayload.h | 1 - 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 1b2a883b16..6188ddefa7 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -55,7 +55,8 @@ subdirs-$(CONFIG_LP_CBFS) += libcbfs subdirs-$(CONFIG_LP_LZMA) += liblzma subdirs-$(CONFIG_LP_LZ4) += liblz4 -INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) -include include/kconfig.h +INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) +INCLUDES += -include include/kconfig.h -include include/compiler.h CFLAGS += $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc -ggdb3 CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 2657a1a1b1..aa09c1d116 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -152,7 +152,8 @@ fi trygccoption -fno-stack-protector [ $? -eq 0 ] && _CFLAGS="$_CFLAGS -fno-stack-protector" -_CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include" +_CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -include $BASE/../include/compiler.h" +_CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include" _LDFLAGS="-L$BASE/../lib -L$_LIBDIR $_LDSCRIPT -static" diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h index 397e08b301..fc4caa4417 100644 --- a/payloads/libpayload/include/cbfs_core.h +++ b/payloads/libpayload/include/cbfs_core.h @@ -49,7 +49,6 @@ #include #include #include -#include /** These are standard values for the known compression alogrithms that coreboot knows about for stages and diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index fa501a7801..f206fea2f9 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -44,7 +44,6 @@ #include #include -#include #include #include #include From 85d93ffc0a7b1eb5f24d6b8ec637497c4bdbd090 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 2 Nov 2020 21:32:08 -0700 Subject: [PATCH 112/262] libpayload: Make OHCI enums into types The OHCI header file declares various enums as follows: enum { ... } enum_name; Since the name is at the end, this is actually declaring a variable called enum_name and *not* a type, which is causing a multiple definition error in GCC 10. Move the enum_name before the opening brace to prevent this. Signed-off-by: Jacob Garber Change-Id: I452c0a1b118990942aa53f1e7e77f5e8378e8975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47224 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- .../libpayload/drivers/usb/ohci_private.h | 58 ++++++++++--------- 1 file changed, 30 insertions(+), 28 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ohci_private.h b/payloads/libpayload/drivers/usb/ohci_private.h index 796be29a01..e29e5901bf 100644 --- a/payloads/libpayload/drivers/usb/ohci_private.h +++ b/payloads/libpayload/drivers/usb/ohci_private.h @@ -36,7 +36,7 @@ // FIXME: fake typedef enum { CMD} reg; - enum { + enum HcRhDescriptorAReg { NumberDownstreamPorts = 1 << 0, PowerSwitchingMode = 1 << 8, NoPowerSwitching = 1 << 9, @@ -44,19 +44,19 @@ OverCurrentProtectionMode = 1 << 11, NoOverCurrentProtection = 1 << 12, PowerOnToPowerGoodTime = 1 << 24 - } HcRhDescriptorAReg; + }; - enum { + enum HcRhDescriptorAMask { NumberDownstreamPortsMask = MASK(0, 8), PowerOnToPowerGoodTimeMask = MASK(24, 8) - } HcRhDescriptorAMask; + }; - enum { + enum HcRhDescriptorBReg { DeviceRemovable = 1 << 0, PortPowerControlMask = 1 << 16 - } HcRhDescriptorBReg; + }; - enum { + enum HcRhPortStatusRead { CurrentConnectStatus = 1 << 0, PortEnableStatus = 1 << 1, PortSuspendStatus = 1 << 2, @@ -69,8 +69,9 @@ PortSuspendStatusChange = 1 << 18, PortOverCurrentIndicatorChange = 1 << 19, PortResetStatusChange = 1 << 20 - } HcRhPortStatusRead; - enum { + }; + + enum HcRhPortStatusSet { ClearPortEnable = 1 << 0, SetPortEnable = 1 << 1, SetPortSuspend = 1 << 2, @@ -78,29 +79,30 @@ SetPortReset = 1 << 4, SetPortPower = 1 << 8, ClearPortPower = 1 << 9, - } HcRhPortStatusSet; + }; - enum { + enum HcRhStatusReg { LocalPowerStatus = 1 << 0, OverCurrentIndicator = 1 << 1, DeviceRemoteWakeupEnable = 1 << 15, LocalPowerStatusChange = 1 << 16, OverCurrentIndicatorChange = 1 << 17, ClearRemoteWakeupEnable = 1 << 31 - } HcRhStatusReg; + }; - enum { + enum HcFmIntervalOffset { FrameInterval = 1 << 0, FSLargestDataPacket = 1 << 16, FrameIntervalToggle = 1 << 31 - } HcFmIntervalOffset; - enum { + }; + + enum HcFmIntervalMask { FrameIntervalMask = MASK(0, 14), FSLargestDataPacketMask = MASK(16, 15), FrameIntervalToggleMask = MASK(31, 1) - } HcFmIntervalMask; + }; - enum { + enum HcControlReg { ControlBulkServiceRatio = 1 << 0, PeriodicListEnable = 1 << 2, IsochronousEnable = 1 << 3, @@ -110,12 +112,12 @@ InterruptRouting = 1 << 8, RemoteWakeupConnected = 1 << 9, RemoteWakeupEnable = 1 << 10 - } HcControlReg; + }; - enum { + enum HcControlMask { ControlBulkServiceRatioMask = MASK(0, 2), HostControllerFunctionalStateMask = MASK(6, 2) - } HcControlMask; + }; enum { USBReset = 0*HostControllerFunctionalState, @@ -124,24 +126,24 @@ USBSuspend = 3*HostControllerFunctionalState }; - enum { + enum HcCommandStatusReg { HostControllerReset = 1 << 0, ControlListFilled = 1 << 1, BulkListFilled = 1 << 2, OwnershipChangeRequest = 1 << 3, SchedulingOverrunCount = 1 << 16 - } HcCommandStatusReg; + }; - enum { + enum HcCommandStatusMask { SchedulingOverrunCountMask = MASK(16, 2) - } HcCommandStatusMask; + }; - enum { + enum HcFmRemainingReg { FrameRemaining = 1 << 0, FrameRemainingToggle = 1 << 31 - } HcFmRemainingReg; + }; - enum { + enum HcInterruptStatusReg { SchedulingOverrung = 1 << 0, WritebackDoneHead = 1 << 1, StartofFrame = 1 << 2, @@ -150,7 +152,7 @@ FrameNumberOverflow = 1 << 5, RootHubStatusChange = 1 << 6, OwnershipChange = 1 << 30 - } HcInterruptStatusReg; + }; typedef struct { // Control and Status Partition From 0a61ecef35f0b72c747961e5c0eb14f800b10d8a Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 7 Nov 2020 13:01:49 +0530 Subject: [PATCH 113/262] mb/intel/adlrvp: Refactor ADLRVP code to get rid of 'variants/baseboard' List of changes: 1. Use devicetree.cb from default location 2. Create variant directory for ADL RVP with external EC as 'adlrvp_p_ext_ec' 3. Add initial overridetree.cb for 'adlrvp_p' and 'adlrvp_p_ext_ec' to override 'devicetree.cb' as applicable. 4. Move all common files between 'adlrvp_p' and 'adlrvp_p_ext_ec' to mainboard directory TEST=Build and boot both ADLRVP with onboard and external EC. Change-Id: I3591e214ed32dc9baaa49b92dff59579f29c7bd6 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/47335 Reviewed-by: V Sowmya Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/intel/adlrvp/Kconfig | 7 ++++--- src/mainboard/intel/adlrvp/Makefile.inc | 6 ++++-- .../intel/adlrvp/{variants/adlrvp_p => }/devicetree.cb | 0 .../intel/adlrvp/{variants/adlrvp_p => }/early_gpio.c | 0 src/mainboard/intel/adlrvp/{variants/adlrvp_p => }/gpio.c | 0 .../adlrvp/{variants/baseboard => }/include/baseboard/ec.h | 0 .../{variants/baseboard => }/include/baseboard/gpio.h | 0 .../{variants/baseboard => }/include/baseboard/variants.h | 0 .../intel/adlrvp/{variants/adlrvp_p => }/memory.c | 2 +- src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc | 7 ------- .../intel/adlrvp/variants/adlrvp_p/overridetree.cb | 4 ++++ .../intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb | 4 ++++ 12 files changed, 17 insertions(+), 13 deletions(-) rename src/mainboard/intel/adlrvp/{variants/adlrvp_p => }/devicetree.cb (100%) rename src/mainboard/intel/adlrvp/{variants/adlrvp_p => }/early_gpio.c (100%) rename src/mainboard/intel/adlrvp/{variants/adlrvp_p => }/gpio.c (100%) rename src/mainboard/intel/adlrvp/{variants/baseboard => }/include/baseboard/ec.h (100%) rename src/mainboard/intel/adlrvp/{variants/baseboard => }/include/baseboard/gpio.h (100%) rename src/mainboard/intel/adlrvp/{variants/baseboard => }/include/baseboard/variants.h (100%) rename src/mainboard/intel/adlrvp/{variants/adlrvp_p => }/memory.c (98%) delete mode 100644 src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc create mode 100644 src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb create mode 100644 src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 2a3dbb021c..a41c18659d 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -32,7 +32,8 @@ config MAINBOARD_DIR config VARIANT_DIR string - default "adlrvp_p" + default "adlrvp_p" if BOARD_INTEL_ADLRVP_P + default "adlrvp_p_ext_ec" if BOARD_INTEL_ADLRVP_P_EXT_EC config GBB_HWID string @@ -47,9 +48,9 @@ config MAINBOARD_FAMILY string default "Intel_adlrvp" -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" config DIMM_SPD_SIZE int diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index 2ca32f3760..de924067d1 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -4,12 +4,14 @@ subdirs-y += spd bootblock-y += bootblock.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c +bootblock-y += early_gpio.c verstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c romstage-y += board_id.c +romstage-y += memory.c smm-y += smihandler.c @@ -17,8 +19,8 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c ramstage-y += board_id.c +ramstage-y += gpio.c -subdirs-y += variants/baseboard -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb similarity index 100% rename from src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb rename to src/mainboard/intel/adlrvp/devicetree.cb diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c b/src/mainboard/intel/adlrvp/early_gpio.c similarity index 100% rename from src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c rename to src/mainboard/intel/adlrvp/early_gpio.c diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/gpio.c similarity index 100% rename from src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c rename to src/mainboard/intel/adlrvp/gpio.c diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/include/baseboard/ec.h similarity index 100% rename from src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h rename to src/mainboard/intel/adlrvp/include/baseboard/ec.h diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h similarity index 100% rename from src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h rename to src/mainboard/intel/adlrvp/include/baseboard/gpio.h diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h similarity index 100% rename from src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h rename to src/mainboard/intel/adlrvp/include/baseboard/variants.h diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c b/src/mainboard/intel/adlrvp/memory.c similarity index 98% rename from src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c rename to src/mainboard/intel/adlrvp/memory.c index ec7ae88135..d51caf783a 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include "../../board_id.h" +#include "board_id.h" #include #include diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc deleted file mode 100644 index 513963ebd5..0000000000 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += early_gpio.c - -romstage-y += memory.c - -ramstage-y += gpio.c diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb new file mode 100644 index 0000000000..e58e9fbdce --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/alderlake + + device domain 0 on end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb new file mode 100644 index 0000000000..e58e9fbdce --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/alderlake + + device domain 0 on end +end From 645bca48101e96c48941b154ec25871e5aeeb7b9 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 2 Nov 2020 14:29:46 -0700 Subject: [PATCH 114/262] soc/intel/xeon_sp/skx: Reorder soc_util.c Reorder soc_util.c and remove the un-needed #if ENV_RAMSTAGE to match cpx version in preparation for more de-duplication. Change-Id: Iab343e903e2478709fe91739c9ca77f587286df7 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/47171 Tested-by: build bot (Jenkins) Reviewed-by: Jay Talbott Reviewed-by: Stefan Reinauer --- src/soc/intel/xeon_sp/skx/soc_util.c | 198 +++++++++++++-------------- 1 file changed, 98 insertions(+), 100 deletions(-) diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 5a2b3c6ca5..3faaed0f06 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -45,18 +45,42 @@ * +-------------------------+ */ -static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) +const struct SystemMemoryMapHob *get_system_memory_map(void) +{ + size_t hob_size; + const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + const struct SystemMemoryMapHob *memmap_addr; + + memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); + assert(memmap_addr != NULL && hob_size != 0); + + return memmap_addr; +} + +uint8_t get_iiostack_info(struct iiostack_resource *info) { size_t hob_size; - const IIO_UDS *hob; const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob; - assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK); - - hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); + hob = fsp_find_extension_hob_by_guid( + fsp_hob_iio_universal_data_guid, &hob_size); assert(hob != NULL && hob_size != 0); - return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; + // copy IIO Stack info from FSP HOB + info->no_of_stacks = 0; + for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { + for (int x = 0; x < MAX_IIO_STACK; ++x) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; + // TODO: do we have situation with only bux 0 and one stack? + if (ri->BusBase >= ri->BusLimit) + continue; + assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK)); + memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); + } + } + + return hob->PlatformData.Pci64BitResourceAllocation; } /* return 1 if command timed out else 0 */ @@ -79,26 +103,6 @@ static uint32_t wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t ma return 0; /* successful */ } -/* return 1 if command timed out else 0 */ -static int set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask, - uint32_t pcode_init_mask, uint32_t val) -{ - uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); - pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); - - uint32_t reg = pci_mmio_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG); - reg &= (uint32_t) ~rst_cpl_mask; - reg |= rst_cpl_mask; - reg |= val; - - /* update BIOS RESET completion bit */ - pci_mmio_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg); - - /* wait for PCU ack */ - return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask, - pcode_init_mask); -} - /* return 1 if command timed out else 0 */ static uint32_t write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data) { @@ -123,54 +127,38 @@ static uint32_t write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32 BIOS_MB_RUN_BUSY_MASK, 0); } -void config_reset_cpl3_csrs(void) +static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) { - uint32_t data, plat_info, max_min_turbo_limit_ratio; + size_t hob_size; + const IIO_UDS *hob; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) { - uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK); - /* configure PCU_CR0_FUN csrs */ - pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN); - data = pci_mmio_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS); - data |= P_STATE_LIMITS_LOCK; - pci_mmio_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data); + hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); - plat_info = pci_mmio_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO); - dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO); - max_min_turbo_limit_ratio = - (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> - MAX_NON_TURBO_LIM_RATIO_SHIFT; - printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n", - plat_info, max_min_turbo_limit_ratio); + return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; +} - /* configure PCU_CR1_FUN csrs */ - pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); +/* return 1 if command timed out else 0 */ +static int set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask, + uint32_t pcode_init_mask, uint32_t val) +{ + uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); - data = pci_mmio_read_config32(cr1_dev, PCU_CR1_SAPMCTL); - /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */ - data &= 0x0fffffff; - data |= SAPMCTL_LOCK_MASK; - pci_mmio_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data); + uint32_t reg = pci_mmio_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG); + reg &= (uint32_t) ~rst_cpl_mask; + reg |= rst_cpl_mask; + reg |= val; - /* configure PCU_CR1_FUN csrs */ - pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN); + /* update BIOS RESET completion bit */ + pci_mmio_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg); - data = PCIE_IN_PKGCSTATE_L1_MASK; - pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data); - - data = KTI_IN_PKGCSTATE_L1_MASK; - pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data); - - data = PROCHOT_RATIO; - printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data); - pci_mmio_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data); - dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG); - - data = pci_mmio_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL); - data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT; - pci_mmio_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data); - } + /* wait for PCU ack */ + return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask, + pcode_init_mask); } static void set_bios_init_completion_for_package(uint32_t socket) @@ -229,43 +217,54 @@ void set_bios_init_completion(void) set_bios_init_completion_for_package(sbsp_socket_id); } -uint8_t get_iiostack_info(struct iiostack_resource *info) +void config_reset_cpl3_csrs(void) { - size_t hob_size; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob; + uint32_t data, plat_info, max_min_turbo_limit_ratio; - hob = fsp_find_extension_hob_by_guid( - fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); + for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) { + uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); - // copy IIO Stack info from FSP HOB - info->no_of_stacks = 0; - for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { - for (int x = 0; x < MAX_IIO_STACK; ++x) { - const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; - // TODO: do we have situation with only bux 0 and one stack? - if (ri->BusBase >= ri->BusLimit) - continue; - assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK)); - memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); - } + /* configure PCU_CR0_FUN csrs */ + pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN); + data = pci_mmio_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS); + data |= P_STATE_LIMITS_LOCK; + pci_mmio_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data); + + plat_info = pci_mmio_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO); + dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO); + max_min_turbo_limit_ratio = + (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> + MAX_NON_TURBO_LIM_RATIO_SHIFT; + printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n", + plat_info, max_min_turbo_limit_ratio); + + /* configure PCU_CR1_FUN csrs */ + pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + + data = pci_mmio_read_config32(cr1_dev, PCU_CR1_SAPMCTL); + /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */ + data &= 0x0fffffff; + data |= SAPMCTL_LOCK_MASK; + pci_mmio_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data); + + /* configure PCU_CR1_FUN csrs */ + pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN); + + data = PCIE_IN_PKGCSTATE_L1_MASK; + pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data); + + data = KTI_IN_PKGCSTATE_L1_MASK; + pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data); + + data = PROCHOT_RATIO; + printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data); + pci_mmio_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data); + dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG); + + data = pci_mmio_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL); + data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT; + pci_mmio_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data); } - - return hob->PlatformData.Pci64BitResourceAllocation; -} - -#if ENV_RAMSTAGE -const struct SystemMemoryMapHob *get_system_memory_map(void) -{ - size_t hob_size; - const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; - const struct SystemMemoryMapHob *memmap_addr; - - memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); - assert(memmap_addr != NULL && hob_size != 0); - - return memmap_addr; } /* @@ -296,4 +295,3 @@ int soc_get_stack_for_port(int port) else return -1; } -#endif From 83e41055abc0e4c7f5da6412be2d3c5cd43b6454 Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Tue, 3 Nov 2020 18:00:59 +0800 Subject: [PATCH 115/262] mb/google/puff/var/dooly: Set default I2C0 frequency This setting copy from puff reference board and should measure again after whole system build. BUG=b:155261464 BRANCH=puff TEST=emerge-puff coreboot and check system speaker has sound output. Change-Id: Idd5c3276e9306e81ea766d14ed1415a68dedc2ad Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/47161 Reviewed-by: Edward O'Callaghan Reviewed-by: Sam McNally Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/dooly/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index ee91dd3653..f4b6d63897 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -125,8 +125,8 @@ chip soc/intel/cannonlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, + .rise_time_ns = 60, + .fall_time_ns = 60, }, .i2c[2] = { .speed = I2C_SPEED_FAST, From e569e3e248f7df389d4b86ebc1c145d6781de45e Mon Sep 17 00:00:00 2001 From: Thomas Heijligen Date: Thu, 5 Nov 2020 14:33:15 +0100 Subject: [PATCH 116/262] libpayload: storage.c: remove unneeded #if CONFIG() Change-Id: I6e5679f66840105b3f9628071ac7aace9128107f Signed-off-by: Thomas Heijligen Reviewed-on: https://review.coreboot.org/c/coreboot/+/47248 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- payloads/libpayload/drivers/storage/storage.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c index a3b31c598d..4b585bae3a 100644 --- a/payloads/libpayload/drivers/storage/storage.c +++ b/payloads/libpayload/drivers/storage/storage.c @@ -28,9 +28,7 @@ #include #include -#if CONFIG(LP_STORAGE_AHCI) -# include -#endif +#include #include static storage_dev_t **devices = NULL; From 04582e900102357056aa218e5a413edb52409e87 Mon Sep 17 00:00:00 2001 From: Johnny Li Date: Thu, 5 Nov 2020 13:13:44 +0800 Subject: [PATCH 117/262] mb/google/volteer/variants/volteer2: Tune I2C3 camera bus freq 400 kHz The current I2C3 bus frequency is 341 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C3 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C3 frequency is 394kHz. Signed-off-by: Johnny Li Change-Id: Ie1ef95bb39d71fbb113120a0ec88305bc23e7ab9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47225 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali --- .../google/volteer/variants/volteer2/overridetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index bb4db53e32..1cb0b52b03 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -39,6 +39,12 @@ chip soc/intel/tigerlake }, .i2c[3] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 153, + .scl_hcnt = 75, + .sda_hold = 36, + }, }, .i2c[5] = { .speed = I2C_SPEED_FAST, From d1c0f958d1986a94ac55ae1d196ba286c311b90f Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 2 Nov 2020 16:26:52 -0700 Subject: [PATCH 118/262] acpi: Call acpi_fill_ssdt() only for enabled devices Individual drivers check whether the concerned device is enabled before filling in the SSDT. Move the check before calling acpi_fill_ssdt() and remove the check in the individual drivers. BUG=None TEST=util/abuild/abuild Change-Id: Ib042bec7e8c68b38fafa60a8e965d781bddcd1f0 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47148 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Sumeet R Pawnikar Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons Reviewed-by: Christian Walter --- src/acpi/acpi.c | 2 +- src/drivers/generic/adau7002/adau7002.c | 2 +- src/drivers/generic/gpio_keys/gpio_keys.c | 2 +- src/drivers/generic/max98357a/max98357a.c | 2 +- src/drivers/gfx/generic/generic.c | 2 +- src/drivers/i2c/da7219/da7219.c | 2 +- src/drivers/i2c/designware/dw_i2c.c | 3 --- src/drivers/i2c/generic/generic.c | 2 +- src/drivers/i2c/gpiomux/bus/bus.c | 2 +- src/drivers/i2c/gpiomux/mux/mux.c | 2 +- src/drivers/i2c/max98373/max98373.c | 2 +- src/drivers/i2c/max98390/max98390.c | 2 +- src/drivers/i2c/max98927/max98927.c | 2 +- src/drivers/i2c/nau8825/nau8825.c | 2 +- src/drivers/i2c/rt1011/rt1011.c | 2 +- src/drivers/i2c/rt5663/rt5663.c | 2 +- src/drivers/i2c/sx9310/sx9310.c | 2 +- src/drivers/i2c/tpm/chip.c | 2 +- src/drivers/intel/ish/ish.c | 2 +- src/drivers/intel/mipi_camera/camera.c | 3 --- src/drivers/intel/pmc_mux/conn/conn.c | 3 --- src/drivers/intel/soundwire/soundwire.c | 2 +- src/drivers/intel/usb4/retimer/retimer.c | 2 +- src/drivers/soundwire/alc5682/alc5682.c | 2 +- src/drivers/soundwire/alc711/alc711.c | 2 +- src/drivers/soundwire/max98373/max98373.c | 2 +- src/drivers/spi/acpi/acpi.c | 2 +- src/drivers/uart/acpi/acpi.c | 2 +- src/drivers/usb/acpi/usb_acpi.c | 2 +- src/drivers/wifi/generic/acpi.c | 6 ------ src/ec/google/chromeec/audio_codec/audio_codec.c | 2 +- src/ec/google/chromeec/ec_acpi.c | 3 --- src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c | 2 +- src/ec/google/wilco/chip.c | 3 --- src/soc/intel/common/block/scs/sd.c | 3 --- src/soc/intel/common/block/usb4/pcie.c | 2 +- src/soc/intel/common/block/usb4/usb4.c | 3 --- 37 files changed, 29 insertions(+), 56 deletions(-) diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 89f2a46a8d..259813bc26 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -468,7 +468,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) { struct device *dev; for (dev = all_devices; dev; dev = dev->next) - if (dev->ops && dev->ops->acpi_fill_ssdt) + if (dev->enabled && dev->ops && dev->ops->acpi_fill_ssdt) dev->ops->acpi_fill_ssdt(dev); current = (unsigned long) acpigen_get_current(); } diff --git a/src/drivers/generic/adau7002/adau7002.c b/src/drivers/generic/adau7002/adau7002.c index 88ee34da7b..26da09b264 100644 --- a/src/drivers/generic/adau7002/adau7002.c +++ b/src/drivers/generic/adau7002/adau7002.c @@ -17,7 +17,7 @@ static void adau7002_fill_ssdt(const struct device *dev) struct drivers_generic_adau7002_config *config; struct acpi_dp *dp; - if (!dev || !dev->enabled) + if (!dev) return; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index 80ac407904..3d273a030f 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -57,7 +57,7 @@ static void gpio_keys_fill_ssdt_generator(const struct device *dev) const char *drv_string = config->is_polled ? "gpio-keys-polled" : "gpio-keys"; - if (!dev->enabled || !scope || !path || !config->gpio.pin_count) + if (!scope || !path || !config->gpio.pin_count) return; /* Device */ diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 44f8802490..9ae4bf4658 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -18,7 +18,7 @@ static void max98357a_fill_ssdt(const struct device *dev) const char *path; struct acpi_dp *dp; - if (!dev->enabled || !config) + if (!config) return; const char *scope = acpi_device_scope(dev); diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c index 546f30bead..d3a4518d40 100644 --- a/src/drivers/gfx/generic/generic.c +++ b/src/drivers/gfx/generic/generic.c @@ -106,7 +106,7 @@ static void gfx_fill_ssdt_generator(const struct device *dev) const char *scope = acpi_device_scope(dev); - if (!scope || !dev->enabled) + if (!scope) return; acpigen_write_scope(scope); diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c index 1d98023ff5..0423460049 100644 --- a/src/drivers/i2c/da7219/da7219.c +++ b/src/drivers/i2c/da7219/da7219.c @@ -27,7 +27,7 @@ static void da7219_fill_ssdt(const struct device *dev) }; struct acpi_dp *dsd, *aad; - if (!dev->enabled || !scope) + if (!scope) return; /* Device */ diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index e01b5a8446..3181e7a0cf 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -824,9 +824,6 @@ void dw_i2c_acpi_fill_ssdt(const struct device *dev) const char *path; unsigned int speed; - if (!dev->enabled) - return; - bus = dw_i2c_soc_dev_to_bus(dev); if (bus < 0) diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 18fd55cd58..cd7406893b 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -57,7 +57,7 @@ void i2c_generic_fill_ssdt(const struct device *dev, int reset_gpio_index = -1, enable_gpio_index = -1, irq_gpio_index = -1; const char *path = acpi_device_path(dev); - if (!dev->enabled || !scope) + if (!scope) return; if (!config->hid) { diff --git a/src/drivers/i2c/gpiomux/bus/bus.c b/src/drivers/i2c/gpiomux/bus/bus.c index 66aef8e8c0..0bcf36a3f4 100644 --- a/src/drivers/i2c/gpiomux/bus/bus.c +++ b/src/drivers/i2c/gpiomux/bus/bus.c @@ -22,7 +22,7 @@ static void i2c_gpiomux_bus_fill_ssdt(const struct device *dev) const char *scope = acpi_device_scope(dev); const char *path = acpi_device_path(dev); - if (!dev || !dev->enabled || !scope || !path) + if (!dev || !scope || !path) return; /* Device */ diff --git a/src/drivers/i2c/gpiomux/mux/mux.c b/src/drivers/i2c/gpiomux/mux/mux.c index 66c8cc5cc3..c1ae758226 100644 --- a/src/drivers/i2c/gpiomux/mux/mux.c +++ b/src/drivers/i2c/gpiomux/mux/mux.c @@ -27,7 +27,7 @@ static void i2c_gpiomux_mux_fill_ssdt(const struct device *dev) struct acpi_gpio_res_params param[MAX_NUM_MUX_GPIOS]; int i; - if (!dev->enabled || !scope || !path) + if (!scope || !path) return; /* Device */ diff --git a/src/drivers/i2c/max98373/max98373.c b/src/drivers/i2c/max98373/max98373.c index 1f8a4f3b29..b078674ef0 100644 --- a/src/drivers/i2c/max98373/max98373.c +++ b/src/drivers/i2c/max98373/max98373.c @@ -24,7 +24,7 @@ static void max98373_fill_ssdt(const struct device *dev) }; struct acpi_dp *dp; - if (!dev->enabled || !scope) { + if (!scope) { printk(BIOS_ERR, "%s: dev not enabled\n", __func__); return; } diff --git a/src/drivers/i2c/max98390/max98390.c b/src/drivers/i2c/max98390/max98390.c index 24c500bd2e..c216391e04 100644 --- a/src/drivers/i2c/max98390/max98390.c +++ b/src/drivers/i2c/max98390/max98390.c @@ -28,7 +28,7 @@ static void max98390_fill_ssdt(const struct device *dev) struct acpi_dp *dp; uint64_t r0_value, temp_value; - if (!dev->enabled || !scope) + if (!scope) return; /* Device */ diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c index 9429e4aa0d..642eccfd36 100644 --- a/src/drivers/i2c/max98927/max98927.c +++ b/src/drivers/i2c/max98927/max98927.c @@ -24,7 +24,7 @@ static void max98927_fill_ssdt(const struct device *dev) }; struct acpi_dp *dp; - if (!dev->enabled || !scope) + if (!scope) return; /* Device */ diff --git a/src/drivers/i2c/nau8825/nau8825.c b/src/drivers/i2c/nau8825/nau8825.c index e995ebd06d..a0769d0422 100644 --- a/src/drivers/i2c/nau8825/nau8825.c +++ b/src/drivers/i2c/nau8825/nau8825.c @@ -30,7 +30,7 @@ static void nau8825_fill_ssdt(const struct device *dev) }; struct acpi_dp *dp = NULL; - if (!dev->enabled || !scope) + if (!scope) return; if (config->sar_threshold_num > NAU8825_MAX_BUTTONS) return; diff --git a/src/drivers/i2c/rt1011/rt1011.c b/src/drivers/i2c/rt1011/rt1011.c index d1732f7440..70f1881b6c 100644 --- a/src/drivers/i2c/rt1011/rt1011.c +++ b/src/drivers/i2c/rt1011/rt1011.c @@ -28,7 +28,7 @@ static void rt1011_fill_ssdt(const struct device *dev) struct acpi_dp *dp; uint64_t r0_value, temp_value; - if (!dev->enabled || !scope) + if (!scope) return; /* Device */ diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c index 272cf78319..565e3bb29c 100644 --- a/src/drivers/i2c/rt5663/rt5663.c +++ b/src/drivers/i2c/rt5663/rt5663.c @@ -27,7 +27,7 @@ static void rt5663_fill_ssdt(const struct device *dev) }; struct acpi_dp *dp; - if (!dev->enabled || !scope) + if (!scope) return; /* Device */ diff --git a/src/drivers/i2c/sx9310/sx9310.c b/src/drivers/i2c/sx9310/sx9310.c index c12e4ea524..8dc57a2d98 100644 --- a/src/drivers/i2c/sx9310/sx9310.c +++ b/src/drivers/i2c/sx9310/sx9310.c @@ -28,7 +28,7 @@ static void i2c_sx9310_fill_ssdt(const struct device *dev) }; struct acpi_dp *dsd; - if (!dev->enabled || !scope || !config) + if (!scope || !config) return; if (config->speed) diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c index 2baec423f1..07791c33a4 100644 --- a/src/drivers/i2c/tpm/chip.c +++ b/src/drivers/i2c/tpm/chip.c @@ -20,7 +20,7 @@ static void i2c_tpm_fill_ssdt(const struct device *dev) .resource = scope, }; - if (!dev->enabled || !scope) + if (!scope) return; if (!config->hid) { diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index f82f7fc7f6..19cbd82fa5 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -13,7 +13,7 @@ static void ish_fill_ssdt_generator(const struct device *dev) struct device *root = dev->bus->dev; struct acpi_dp *dsd; - if (!dev->enabled || !config || !config->firmware_name) + if (!config || !config->firmware_name) return; acpigen_write_scope(acpi_device_path(root)); diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index d4cf33d9fb..7dfd6502f5 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -909,9 +909,6 @@ static void camera_fill_ssdt(const struct device *dev) const char *scope = NULL; const struct device *pdev; - if (!dev->enabled) - return; - if (config->has_power_resource) { pdev = dev->bus->dev; if (!pdev || !pdev->enabled) diff --git a/src/drivers/intel/pmc_mux/conn/conn.c b/src/drivers/intel/pmc_mux/conn/conn.c index 16d113bcb1..9fd85431f3 100644 --- a/src/drivers/intel/pmc_mux/conn/conn.c +++ b/src/drivers/intel/pmc_mux/conn/conn.c @@ -32,9 +32,6 @@ static void conn_fill_ssdt(const struct device *dev) const char *scope; const char *name; - if (!dev->enabled) - return; - /* Reference the existing scope and write CONx device */ scope = acpi_device_scope(dev); name = acpi_device_name(dev); diff --git a/src/drivers/intel/soundwire/soundwire.c b/src/drivers/intel/soundwire/soundwire.c index 34ecd86021..c7e84a5339 100644 --- a/src/drivers/intel/soundwire/soundwire.c +++ b/src/drivers/intel/soundwire/soundwire.c @@ -50,7 +50,7 @@ static void intel_soundwire_fill_ssdt(const struct device *dev) struct intel_soundwire_controller *controller; const char *scope = acpi_device_scope(dev); - if (!dev->enabled || !scope) + if (!scope) return; if (soc_fill_soundwire_controller(&controller) < 0 || !controller) diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c index be9ec35230..7a693ff531 100644 --- a/src/drivers/intel/usb4/retimer/retimer.c +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -101,7 +101,7 @@ static void usb4_retimer_fill_ssdt(const struct device *dev) const struct drivers_intel_usb4_retimer_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); - if (!dev->enabled || !scope || !config) + if (!scope || !config) return; if (!config->power_gpio.pin_count) { diff --git a/src/drivers/soundwire/alc5682/alc5682.c b/src/drivers/soundwire/alc5682/alc5682.c index 79ed610ab8..e15ecd421a 100644 --- a/src/drivers/soundwire/alc5682/alc5682.c +++ b/src/drivers/soundwire/alc5682/alc5682.c @@ -128,7 +128,7 @@ static void soundwire_alc5682_fill_ssdt(const struct device *dev) const char *scope = acpi_device_scope(dev); struct acpi_dp *dsd; - if (!dev->enabled || !scope) + if (!scope) return; acpigen_write_scope(scope); diff --git a/src/drivers/soundwire/alc711/alc711.c b/src/drivers/soundwire/alc711/alc711.c index 8382fc94fb..44a9e98deb 100644 --- a/src/drivers/soundwire/alc711/alc711.c +++ b/src/drivers/soundwire/alc711/alc711.c @@ -105,7 +105,7 @@ static void soundwire_alc711_fill_ssdt(const struct device *dev) const char *scope = acpi_device_scope(dev); struct acpi_dp *dsd; - if (!dev->enabled || !scope) + if (!scope) return; acpigen_write_scope(scope); diff --git a/src/drivers/soundwire/max98373/max98373.c b/src/drivers/soundwire/max98373/max98373.c index 231385cd57..28796c06bc 100644 --- a/src/drivers/soundwire/max98373/max98373.c +++ b/src/drivers/soundwire/max98373/max98373.c @@ -114,7 +114,7 @@ static void soundwire_max98373_fill_ssdt(const struct device *dev) const char *scope = acpi_device_scope(dev); struct acpi_dp *dsd; - if (!dev->enabled || !scope) + if (!scope) return; acpigen_write_scope(scope); diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index c0e776eee1..b23bc9d7a9 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -77,7 +77,7 @@ static void spi_acpi_fill_ssdt_generator(const struct device *dev) int reset_gpio_index = -1; int enable_gpio_index = -1; - if (!dev->enabled || !scope) + if (!scope) return; if (spi_acpi_get_bus(dev) == -1) { diff --git a/src/drivers/uart/acpi/acpi.c b/src/drivers/uart/acpi/acpi.c index f9d9d8fa19..d4b14aac04 100644 --- a/src/drivers/uart/acpi/acpi.c +++ b/src/drivers/uart/acpi/acpi.c @@ -46,7 +46,7 @@ static void uart_acpi_fill_ssdt(const struct device *dev) int reset_gpio_index = -1; int enable_gpio_index = -1; - if (!dev->enabled || !scope) + if (!scope) return; if (!config->hid) { diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index d33b7deeaf..55ef1d361f 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -24,7 +24,7 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev) struct drivers_usb_acpi_config *config = dev->chip_info; const char *path = acpi_device_path(dev); - if (!dev->enabled || !path || !config) + if (!path || !config) return; /* Don't generate output for hubs, only ports */ diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index ac2c5eb5ba..1cc4bd080f 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -222,9 +222,6 @@ void wifi_pcie_fill_ssdt(const struct device *dev) { const char *path; - if (!is_dev_enabled(dev)) - return; - path = acpi_device_path(dev); if (!path) return; @@ -247,9 +244,6 @@ void wifi_cnvi_fill_ssdt(const struct device *dev) { const char *path; - if (!is_dev_enabled(dev)) - return; - path = acpi_device_path(dev->bus->dev); if (!path) return; diff --git a/src/ec/google/chromeec/audio_codec/audio_codec.c b/src/ec/google/chromeec/audio_codec/audio_codec.c index 612b1f6995..53037eb01b 100644 --- a/src/ec/google/chromeec/audio_codec/audio_codec.c +++ b/src/ec/google/chromeec/audio_codec/audio_codec.c @@ -15,7 +15,7 @@ static void crosec_audio_codec_fill_ssdt(const struct device *dev) const char *scope = acpi_device_scope(dev); struct ec_google_chromeec_audio_codec_config *cfg = dev->chip_info; - if (!dev->enabled || !scope || !cfg) + if (!scope || !cfg) return; acpigen_write_scope(scope); diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 448ea4dadd..fff395411c 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -223,9 +223,6 @@ void google_chromeec_fill_ssdt_generator(const struct device *dev) struct device_path path; struct device *ec; - if (!dev->enabled) - return; - /* Set up a minimal EC0 device to pass to the DPTF helpers */ path.type = DEVICE_PATH_GENERIC; path.generic.id = 0; diff --git a/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c index ec8bdfc2bf..e61ecfd8c1 100644 --- a/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c +++ b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c @@ -17,7 +17,7 @@ static void crosec_i2c_tunnel_fill_ssdt(const struct device *dev) struct ec_google_chromeec_i2c_tunnel_config *cfg = dev->chip_info; struct acpi_dp *dsd; - if (!dev->enabled || !scope || !cfg) + if (!scope || !cfg) return; acpigen_write_scope(scope); diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index dccaa23d01..911eb25074 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -184,9 +184,6 @@ static void wilco_ec_fill_ssdt_generator(const struct device *dev) void *region_ptr; size_t ucsi_alloc_region_len; - if (!dev->enabled) - return; - ucsi_alloc_region_len = ucsi_region_len < UCSI_MIN_ALLOC_REGION_LEN ? UCSI_MIN_ALLOC_REGION_LEN : ucsi_region_len; region_ptr = cbmem_add(CBMEM_ID_ACPI_UCSI, ucsi_alloc_region_len); diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 04ebb1305d..be59a3db72 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -12,9 +12,6 @@ static void sd_fill_ssdt(const struct device *dev) struct acpi_gpio default_gpio = { 0 }; struct acpi_dp *dp; - if (!dev->enabled) - return; - if (sd_fill_soc_gpio_info(&default_gpio, dev) != 0) return; diff --git a/src/soc/intel/common/block/usb4/pcie.c b/src/soc/intel/common/block/usb4/pcie.c index eae9027511..81496ce70a 100644 --- a/src/soc/intel/common/block/usb4/pcie.c +++ b/src/soc/intel/common/block/usb4/pcie.c @@ -26,7 +26,7 @@ static void usb4_pcie_acpi_fill_ssdt(const struct device *dev) return; } - if (!dev->enabled || !parent->enabled) + if (!parent->enabled) return; config = config_of(dev); diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c index df2dfdde37..a8ab7364a8 100644 --- a/src/soc/intel/common/block/usb4/usb4.c +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -28,9 +28,6 @@ static void tbt_dma_fill_ssdt(const struct device *dev) { struct acpi_dp *dsd, *pkg; - if (!dev->enabled) - return; - acpigen_write_scope(acpi_device_path(dev)); dsd = acpi_dp_new_table("_DSD"); From e94f86571c0d327b67ab290e9f01f59a5561c29a Mon Sep 17 00:00:00 2001 From: Jes Klinke Date: Fri, 30 Oct 2020 13:46:39 -0700 Subject: [PATCH 119/262] mb/google/volteer: Skip TPM detection except on SPI Production Volteer devices have Cr50 TPM connected via SPI, depending on Cr50 firmware version it may or may not support long enough interrupt pulses for the SoC to safely be able to enable lowest power mode. Some reworked Volteer devices have had the Cr50 (Haven) TPM replaced with Dauntless, communicating via I2C. The I2C drivers do not support being accessed early in ramstage, before chip init and memory mapping, (tlcl_lib_init() will halt with an error finding the I2C controller base address.) Since the Dauntless device under development can be made to support longer interrupts, or a completely new interrupt signalling mode, there is no need to try to go through the same discovery as is done via SPI. This CL will skip the discovery, enabling the S0i3.4 sleep mode in all cases, on the reworked test devices. BUG=b:169526865, b:172509545 TEST=abuild -t GOOGLE_VOLTEER2 -c max -x Change-Id: I08a533cede30a3c0ab943938961dc7e4b572d4ce Signed-off-by: Jes Bodi Klinke Reviewed-on: https://review.coreboot.org/c/coreboot/+/47049 Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/mainboard.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index acba9722dc..0850e745db 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -96,13 +96,23 @@ static void mainboard_enable(struct device *dev) void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg) { int ret; + if (!CONFIG(MAINBOARD_HAS_SPI_TPM_CR50)) { + /* + * Negotiation of long interrupt pulses is only supported via SPI. I2C is only + * used on reworked prototypes on which the TPM is replaced with Dauntless under + * development, it will use long pulses by default, or use the interrupt line in + * a different way altogether. + */ + return; + } + ret = tlcl_lib_init(); if (ret != VB2_SUCCESS) { printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); return; } - if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && cr50_is_long_interrupt_pulse_enabled()) { + if (cr50_is_long_interrupt_pulse_enabled()) { printk(BIOS_INFO, "Enabling S0i3.4\n"); } else { /* From 25f3c4d083ef86b97604894b7752f30841ed01d6 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 3 Nov 2020 16:13:18 +0800 Subject: [PATCH 120/262] mb/google/variant/voema: Select USE_CAR_NEM_ENHANCED_V2 for voema BUG=b:171755775 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu Change-Id: Ibedbbe8f9ac039cbde114ace3266ec067a4003ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/47159 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/volteer/Kconfig.name | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 6c9248e99d..5eeaa994eb 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -86,3 +86,4 @@ config BOARD_GOOGLE_ELEMI config BOARD_GOOGLE_VOEMA bool "-> Voema" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select USE_CAR_NEM_ENHANCED_V2 From 2f6875518ecb31fc46219c9031d2feb16df1afbe Mon Sep 17 00:00:00 2001 From: David Wu Date: Wed, 4 Nov 2020 14:12:39 +0800 Subject: [PATCH 121/262] mb/google/volteer/var/voema: config CSE LITE Config voema to use CSE LITE BUG=b:171755775 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu Change-Id: Ic4ca82ce844e6367da70ed052445943572ae7b09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47203 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/volteer/Kconfig.name | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 5eeaa994eb..7aaaea77a2 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -86,4 +86,5 @@ config BOARD_GOOGLE_ELEMI config BOARD_GOOGLE_VOEMA bool "-> Voema" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU select USE_CAR_NEM_ENHANCED_V2 From 6e98292821ad70ebf970d2ae90faa062d960a5bf Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 3 Nov 2020 19:23:34 +0100 Subject: [PATCH 122/262] soc/intel/*/chip: Remove unused devicetree entry InternalGfx isn't used so drop it. Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/47176 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 1 - src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 1 - src/mainboard/google/sarien/variants/arcada/devicetree.cb | 1 - src/mainboard/google/sarien/variants/sarien/devicetree.cb | 1 - .../prodrive/hermes/variants/baseboard/overridetree.cb | 4 +--- src/soc/intel/cannonlake/chip.h | 1 - src/soc/intel/elkhartlake/chip.h | 1 - src/soc/intel/icelake/chip.h | 1 - src/soc/intel/jasperlake/chip.h | 1 - src/soc/intel/tigerlake/chip.h | 1 - 10 files changed, 1 insertion(+), 12 deletions(-) diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index aeacaa48dd..f3ce6286be 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -30,7 +30,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index dddbca421d..01c0d234f9 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -18,7 +18,6 @@ chip soc/intel/cannonlake register "gen3_dec" = "0x00fc0901" # FSP configuration - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 8562046237..74529d049d 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -19,7 +19,6 @@ chip soc/intel/cannonlake register "SataMode" = "Sata_AHCI" register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[2]" = "1" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 1334749542..519c3eb6d9 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -23,7 +23,6 @@ chip soc/intel/cannonlake register "SataPortsDevSlp[0]" = "1" register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[2]" = "1" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 1bf65ff5a1..025510e7ce 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -161,9 +161,7 @@ chip soc/intel/cannonlake device domain 0 on - device pci 02.0 on # Integrated Graphics Device - register "InternalGfx" = "1" - end + device pci 02.0 on end # Integrated Graphics Device device pci 14.3 on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 7f428a21f0..dc24e9bd8f 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -230,7 +230,6 @@ struct soc_intel_cannonlake_config { /* Gfx related */ uint8_t IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 26d0f0d666..7cd29b4f40 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -140,7 +140,6 @@ struct soc_intel_elkhartlake_config { /* Gfx related */ uint8_t IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index e1b697e3c7..956793acd5 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -152,7 +152,6 @@ struct soc_intel_icelake_config { /* Gfx related */ uint8_t IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 5e9053063b..f157f9218b 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -141,7 +141,6 @@ struct soc_intel_jasperlake_config { /* Gfx related */ uint8_t IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f752b5f415..6a48ad03be 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -261,7 +261,6 @@ struct soc_intel_tigerlake_config { /* Gfx related */ uint8_t IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; From ac12976f0c411c1b337bf9a9619b2b54e81f362b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 3 Nov 2020 18:33:02 +0100 Subject: [PATCH 123/262] nb/intel/pineview: Fix clearing memory The regions TSEG, GSM, GMS should not be marked as cacheable resources. Change-Id: I083b096cf3ed250bca722674abe9feffdb2436d1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47174 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/northbridge/intel/pineview/northbridge.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index a04b62b5d5..e98c16bd92 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -98,9 +98,9 @@ static void mch_domain_read_resources(struct device *dev) /* Report the memory regions */ ram_resource(dev, index++, 0, 640); ram_resource(dev, index++, 768, tomk - 768); - reserved_ram_resource(dev, index++, tseg_basek, tseg_sizek); - reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek); - reserved_ram_resource(dev, index++, igd_basek, gms_sizek); + mmio_resource(dev, index++, tseg_basek, tseg_sizek); + mmio_resource(dev, index++, gtt_basek, gsm_sizek); + mmio_resource(dev, index++, igd_basek, gms_sizek); reserved_ram_resource(dev, index++, cbmem_topk, delta_cbmem); /* From 8e57299a0da5dc9928b97d94b0265cf6883de005 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Wed, 4 Nov 2020 10:23:15 +0530 Subject: [PATCH 124/262] mb/intel/jasperlake_rvp: Update Power Limit2 minimum value Update Power Limit2 (PL2) minimum value to the same as maximum value for jasperlake rvp board. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=None BRANCH=None TEST=Build and test on jasperlake rvp board Change-Id: I862f7106846de5fb37f74419807eedc3096ded8a Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/47201 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 06cf4f6a63..abb5dc83a1 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -189,7 +189,7 @@ chip soc/intel/jasperlake .time_window_max = 1 * MSECS_PER_SEC, .granularity = 200,}" register "controls.power_limits.pl2" = "{ - .min_power = 6000, + .min_power = 20000, .max_power = 20000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, From 207ffb07fe629d84bf2dd34bb9df503e7fd30526 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Tue, 3 Nov 2020 09:41:06 +0530 Subject: [PATCH 125/262] mb/google/dedede/variants: Update Power Limit2 minimum value Update Power Limit2 (PL2) minimum value to the same as maximum value for dedede variants (baseboard and drawcia). Currently, variants like boten, waddledee, waddledoo, metaknight and wheelie uses the DTT entries from baseboard devicetree since there is no override present for these variants. So, these variants will also reflect this change of PL1 minimum value. For madoo variant, PL2 minimum value already set the same as PL2 maximum value. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=None BRANCH=None TEST=Build and test on drawcia system Change-Id: I7ecf1ffcc7871192ebe18eb8c3c3fd3e1193721e Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/47154 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/dedede/variants/drawcia/overridetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index a5ff128079..ce28123036 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -212,7 +212,7 @@ chip soc/intel/jasperlake .granularity = 200, }, .pl2 = { - .min_power = 6000, + .min_power = 20000, .max_power = 20000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 594212190a..202e0f4dc5 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -115,7 +115,7 @@ chip soc/intel/jasperlake .granularity = 200, }, .pl2 = { - .min_power = 6000, + .min_power = 20000, .max_power = 20000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, From 78e0acfb3eeff045f83506e54830066271143756 Mon Sep 17 00:00:00 2001 From: Benjamin Doron Date: Wed, 4 Nov 2020 16:40:57 +0000 Subject: [PATCH 126/262] ec/purism/librem/ec.asl: End comment End comment that (likely mistakenly) removed an EC query method. Change-Id: Id192d665a22a8885d7cec56cd6b8ea207fb54402 Signed-off-by: Benjamin Doron Reviewed-on: https://review.coreboot.org/c/coreboot/+/47115 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Stefan Reinauer --- src/ec/purism/librem/acpi/ec.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl index bf855af35b..143dd04494 100644 --- a/src/ec/purism/librem/acpi/ec.asl +++ b/src/ec/purism/librem/acpi/ec.asl @@ -176,7 +176,7 @@ Device (EC) Notify (\_SB.SLPB, 0x80) } - /* KEY_F13 (Touchpad Enable/Disable) + /* KEY_F13 (Touchpad Enable/Disable) */ Method (_Q34) { TPSN (0x87) From 65a9f4e78d5b1d480a35fb557f2885ed2ccebb8b Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 3 Nov 2020 14:48:47 -0700 Subject: [PATCH 127/262] mb/google/dedede: Enable Wake on AC connect and disconnect Handle AC connect and disconnect notifications from Embedded Controller (EC) and wake from S3/S0ix. BUG=b:172266344 TEST=Build and Boot to OS in Drawlat. Ensure that the system wakes up from suspend on AC connect and disconnect on both the TypeC ports. 276 | 2020-11-04 12:21:29 | S0ix Enter 277 | 2020-11-04 12:21:40 | S0ix Exit 278 | 2020-11-04 12:21:40 | EC Event | AC Disconnected 279 | 2020-11-04 12:21:57 | S0ix Enter 280 | 2020-11-04 12:22:03 | S0ix Exit 281 | 2020-11-04 12:22:03 | EC Event | AC Connected 282 | 2020-11-04 12:22:35 | S0ix Enter 283 | 2020-11-04 12:22:47 | S0ix Exit 284 | 2020-11-04 12:22:47 | EC Event | AC Disconnected 285 | 2020-11-04 12:23:08 | S0ix Enter 286 | 2020-11-04 12:23:16 | S0ix Exit 287 | 2020-11-04 12:23:16 | EC Event | AC Connected Change-Id: I7fa4ac0096548fd63af86e9f56c4c1ee25491399 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47210 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest Reviewed-by: Furquan Shaikh --- .../google/dedede/variants/baseboard/include/baseboard/ec.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h index d9b031eb40..24fe264455 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h @@ -38,9 +38,12 @@ * 2. Power button * 3. Key press * 4. Mode change + * 5. AC Connect/Disconnect */ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) From 8e4182f20d3df2dde8dfb88973de86d4eeaafed8 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 5 Nov 2020 00:33:15 -0700 Subject: [PATCH 128/262] mb/google/dedede/var/drawcia: Remove camera EEPROM power resource EEPROM in the camera module does not require any specific power resources. This will ensure that no unnecessary resources are turned on while accessing the camera EEPROM. BUG=b:167938257 TEST=Build and boot to OS in Drawlat. Ensure that the camera EEPROM is listed in the output of i2cdetect. Change-Id: Iece9b3f657bf94a21cc08bf1745353575858f9b2 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47230 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest Reviewed-by: Furquan Shaikh --- src/mainboard/google/dedede/variants/drawcia/overridetree.cb | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 202e0f4dc5..574ae38db0 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -274,8 +274,6 @@ chip soc/intel/jasperlake register "chip_name" = ""GT24C08"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" - register "pr0" = ""\\_SB.PCI0.I2C3.CAM1.PRIC"" - register "nvm_size" = "0x0400" register "nvm_pagesize" = "1" register "nvm_readonly" = "1" From ec2e3e479af0dc66041ae3b599b7df93b10160b9 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 3 Nov 2020 15:19:08 -0800 Subject: [PATCH 129/262] acpigen: Add more useful helper functions acpigen_write_debug_namestr() - Debug = NAME acpigen_write_return_namestr() - Return (NAME) acpigen_set_package_op_element_int() - Set package pointer element DeRefOf (PKG[ELEM]) = INT acpigen_get_package_element() - Get package (not pointer) element dest_op = PKG[ELEM] acpigen_set_package_element_int() - Set package element to integer PKG[ELEM] = INT acpigen_set_package_element_namestr() - Set package element to namestr PKG[ELEM] = NAME acpigen_write_delay_until_namestr_int() - Delay while waiting for register to equal expected value. BUG=b:160996445 Signed-off-by: Duncan Laurie Change-Id: I9b20a23872b7d4a50f03761032426ffbb722b9ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/47196 Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/acpi/acpigen.c | 94 +++++++++++++++++++++++++++++++++++++- src/include/acpi/acpigen.h | 23 +++++++++- 2 files changed, 115 insertions(+), 2 deletions(-) diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 4a7dfc9325..244ac548c9 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -342,7 +342,7 @@ void acpigen_write_scope(const char *name) void acpigen_get_package_op_element(uint8_t package_op, unsigned int element, uint8_t dest_op) { - /* = DeRefOf ([ = DeRefOf ([]) */ acpigen_write_store(); acpigen_emit_byte(DEREF_OP); acpigen_emit_byte(INDEX_OP); @@ -352,6 +352,52 @@ void acpigen_get_package_op_element(uint8_t package_op, unsigned int element, ui acpigen_emit_byte(dest_op); } +void acpigen_set_package_op_element_int(uint8_t package_op, unsigned int element, uint64_t src) +{ + /* DeRefOf ([]) = */ + acpigen_write_store(); + acpigen_write_integer(src); + acpigen_emit_byte(DEREF_OP); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_byte(package_op); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ +} + +void acpigen_get_package_element(const char *package, unsigned int element, uint8_t dest_op) +{ + /* = [] */ + acpigen_write_store(); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring(package); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ + acpigen_emit_byte(dest_op); +} + +void acpigen_set_package_element_int(const char *package, unsigned int element, uint64_t src) +{ + /* [] = */ + acpigen_write_store(); + acpigen_write_integer(src); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring(package); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ +} + +void acpigen_set_package_element_namestr(const char *package, unsigned int element, + const char *src) +{ + /* [] = */ + acpigen_write_store(); + acpigen_emit_namestring(src); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring(package); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ +} + void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) { /* @@ -1320,6 +1366,14 @@ void acpigen_write_debug_op(uint8_t op) acpigen_emit_ext_op(DEBUG_OP); } +/* Store (str, DEBUG) */ +void acpigen_write_debug_namestr(const char *str) +{ + acpigen_write_store(); + acpigen_emit_namestring(str); + acpigen_emit_ext_op(DEBUG_OP); +} + void acpigen_write_if(void) { acpigen_emit_byte(IF_OP); @@ -1455,6 +1509,12 @@ void acpigen_write_return_integer(uint64_t arg) acpigen_write_integer(arg); } +void acpigen_write_return_namestr(const char *arg) +{ + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring(arg); +} + void acpigen_write_return_string(const char *arg) { acpigen_emit_byte(RETURN_OP); @@ -2098,3 +2158,35 @@ void acpigen_write_xpss_object(const struct acpi_xpss_sw_pstate *pstate_values, acpigen_pop_len(); } + +/* Delay up to wait_ms until provided namestr matches expected value. */ +void acpigen_write_delay_until_namestr_int(uint32_t wait_ms, const char *name, uint64_t value) +{ + uint32_t wait_ms_segment = 1; + uint32_t segments = wait_ms; + + /* Sleep in 16ms segments if delay is more than 32ms. */ + if (wait_ms > 32) { + wait_ms_segment = 16; + segments = wait_ms / 16; + } + + acpigen_write_store_int_to_op(segments, LOCAL7_OP); + acpigen_emit_byte(WHILE_OP); + acpigen_write_len_f(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL7_OP); + acpigen_emit_byte(ZERO_OP); + + /* If name is not provided then just delay in a loop. */ + if (name) { + acpigen_write_if_lequal_namestr_int(name, value); + acpigen_emit_byte(BREAK_OP); + acpigen_pop_len(); /* If */ + } + + acpigen_write_sleep(wait_ms_segment); + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_byte(LOCAL7_OP); + acpigen_pop_len(); /* While */ +} diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 6360614c71..15af0192a3 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -286,6 +286,7 @@ struct cppc_config { }; void acpigen_write_return_integer(uint64_t arg); +void acpigen_write_return_namestr(const char *arg); void acpigen_write_return_string(const char *arg); void acpigen_write_len_f(void); void acpigen_pop_len(void); @@ -374,6 +375,7 @@ void acpigen_write_xor(uint8_t arg1, uint8_t arg2, uint8_t res); void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res); void acpigen_write_not(uint8_t arg, uint8_t res); void acpigen_write_debug_string(const char *str); +void acpigen_write_debug_namestr(const char *str); void acpigen_write_debug_integer(uint64_t val); void acpigen_write_debug_op(uint8_t op); void acpigen_write_if(void); @@ -466,7 +468,7 @@ int get_cst_entries(acpi_cstate_t **); /* * Get element from package into specified destination op: - * = DeRefOf ([ = DeRefOf ([]) * * Example: * acpigen_get_package_op_element(ARG0_OP, 0, LOCAL0_OP) @@ -474,6 +476,25 @@ int get_cst_entries(acpi_cstate_t **); */ void acpigen_get_package_op_element(uint8_t package_op, unsigned int element, uint8_t dest_op); +/* Set element of package op to specified op: DeRefOf ([]) = */ +void acpigen_set_package_op_element_int(uint8_t package_op, unsigned int element, uint64_t src); + +/* Get element from package to specified op: = [] */ +void acpigen_get_package_element(const char *package, unsigned int element, uint8_t dest_op); + +/* Set element of package to specified op: [] = */ +void acpigen_set_package_element_int(const char *package, unsigned int element, uint64_t src); + +/* Set element of package to specified namestr: [] = */ +void acpigen_set_package_element_namestr(const char *package, unsigned int element, + const char *src); + +/* + * Delay up to wait_ms milliseconds until the provided name matches the expected value. + * If wait_ms is >= 32ms then it will wait in 16ms chunks. This function uses LOCAL7_OP. + */ +void acpigen_write_delay_until_namestr_int(uint32_t wait_ms, const char *name, uint64_t value); + /* * Soc-implemented functions for generating ACPI AML code for GPIO handling. All * these functions are expected to use only Local5, Local6 and Local7 From 6719c824508c42366af4cc741c36fa12a2cb09a3 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Mon, 2 Nov 2020 16:47:29 -0800 Subject: [PATCH 130/262] drivers/intel/gma: Add Kconfig option for vbt data size From Tigerlake FSP v3373 onwards vbt binary size changed from 8KiB to 9KiB. Commit cf5d58328fe004d967466be42de62d6bab4c3133 had changed the size from 8 to 9 Kib. This change adds Kconfig option to choose vbt data size based on platform. BUG=b:171401992 BRANCH=none TEST=build and boot delbin and verify fw screen is loaded Signed-off-by: Srinidhi N Kaushik Change-Id: Ia294fc94ce759666fb664dfdb910ecd403e6a2e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47151 Reviewed-by: Wonkyu Kim Reviewed-by: Nico Huber Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/drivers/intel/gma/Kconfig | 4 ++++ src/drivers/intel/gma/opregion.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index c515888a1b..3f75ab9350 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -59,6 +59,10 @@ config INTEL_GMA_SWSMISCI config INTEL_GMA_LIBGFXINIT_EDID bool +config VBT_DATA_SIZE_KB + int + default 8 + config GFX_GMA_ANALOG_I2C_HDMI_B bool diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 8f1d2e6373..ea051241e8 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -19,7 +19,7 @@ const char *mainboard_vbt_filename(void) return "vbt.bin"; } -static char vbt_data[9 * KiB]; +static char vbt_data[CONFIG_VBT_DATA_SIZE_KB * KiB]; static size_t vbt_data_sz; void *locate_vbt(size_t *vbt_size) From 74c16d0a8ba76f07b17d0db58071933b7d7f12b6 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Wed, 4 Nov 2020 11:29:33 -0800 Subject: [PATCH 131/262] soc/intel/tigerlake: Utilize vbt data size Kconfig option From Tigerlake FSP v3373 onwards vbt binary size changed from 8KiB to 9KiB. Commit cf5d58328fe004d967466be42de62d6bab4c3133 had changed the size from 8 to 9 Kib in drivers/gma. This change makes use of Kconfig option to pick the size for tigerlake. BUG=b:171401992 BRANCH=none TEST=build and boot delbin and verify fw screen is loaded Signed-off-by: Srinidhi N Kaushik Change-Id: I21a0bba9ae01bac326f0f931641c98e8d308310f Reviewed-on: https://review.coreboot.org/c/coreboot/+/47209 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim Reviewed-by: Nico Huber Reviewed-by: Furquan Shaikh --- src/soc/intel/tigerlake/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index ed35bd6f2b..b9a5b60e17 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -186,6 +186,10 @@ config CHROMEOS config TPM_CR50 select CR50_USE_LONG_INTERRUPT_PULSES +config VBT_DATA_SIZE_KB + int + default 9 + config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY From 44caa1963fb9e3aa0a392223dab3b9c33acdc441 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Sat, 10 Oct 2020 00:05:36 +0000 Subject: [PATCH 132/262] intel/common/pmc: Add functions for IPC mailbox in ACPI This change adds two functions that provide an IPC mailbox method via ACPI for runtime clock configuration. pmc_acpi_fill_ssdt_ipc_write_method() will provide a method in the SSDT that can be called by other ACPI devices to send an IPC mailbox command. This function is exported because some SOCs override the default PMC device and need to call this function to write the method into the SSDT. pmc_acpi_set_pci_clock() will call the method defined by the previous function to enable or disable the PCIe SRCCLK for a specified root port and clock pin. It can be called by the PCIe root port after turning off power to the attached device. BUG=b:160996445 TEST=boot on volteer device and disassemble the SSDT to ensure that this method exists. Signed-off-by: Duncan Laurie Change-Id: I95f5a1ba2bc6905e0f8ce0e8b2342ad1287a23a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46259 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .../block/include/intelblocks/pmc_ipc.h | 33 ++++ src/soc/intel/common/block/pmc/Kconfig | 8 + src/soc/intel/common/block/pmc/Makefile.inc | 1 + src/soc/intel/common/block/pmc/pmc_ipc.c | 156 +++++++++++++++++- 4 files changed, 195 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h index 0c90cd7df6..fbf9a6ee0e 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h @@ -21,6 +21,14 @@ #define PMC_IPC_CMD_NO_MSI 0 +/* IPC command to enable/disable PCIe SRCCLK */ +#define PMC_IPC_CMD_ID_SET_PCIE_CLOCK 0xAC + +/* IPC return values */ +#define PMC_IPC_SUCCESS 0 +#define PMC_IPC_ERROR 1 +#define PMC_IPC_TIMEOUT 2 + /* * Create the IPC CMD to send to PMC */ @@ -46,4 +54,29 @@ struct pmc_ipc_buffer { enum cb_err pmc_send_ipc_cmd(uint32_t cmd, const struct pmc_ipc_buffer *wbuf, struct pmc_ipc_buffer *rbuf); +/* + * Provides an ACPI method in the SSDT to read/write to the IPC mailbox which is + * defined in the PMC device MMIO address space. + * + * One possible use of this method is to to enable/disable the clock for a + * particular PCIe root port at runtime when the device is in D3 state. + * + * The ACPI method takes 7 arguments: + * IPCW (COMMAND, SUB_ID, SIZE, DATA0, DATA1, DATA2, DATA3) + * + * And will return a package with 5 elements: + * 0 = Return code + * PMC_IPC_SUCCESS + * PMC_IPC_ERROR + * PMC_IPC_TIMEOUT + * 1..4 = Data read from IPC if return code is PMC_IPC_SUCCESS + */ +void pmc_ipc_acpi_fill_ssdt(void); + +/* + * Call the ACPI method to write to the IPC mailbox and enable/disable the + * specified clock pin connected to the specified PCIe root port. + */ +void pmc_ipc_acpi_set_pci_clock(unsigned int pcie_rp, unsigned int clock_pin, bool enable); + #endif /* SOC_INTEL_COMMON_BLOCK_PMC_IPC_H */ diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index ce41b23620..5cb2bea1d9 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -22,6 +22,14 @@ config PMC_INVALID_READ_AFTER_WRITE Enable this for PMC devices where a read back of ACPI BAR and IO access bit does not return the previously written value. +config PMC_IPC_ACPI_INTERFACE + bool + default n + depends on HAVE_ACPI_TABLES + help + Enable this to have the PMC IPC mailbox ACPI interface added + to the SSDT for use by other drivers. + config PMC_GLOBAL_RESET_ENABLE_LOCK bool help diff --git a/src/soc/intel/common/block/pmc/Makefile.inc b/src/soc/intel/common/block/pmc/Makefile.inc index 796a039aed..49a0902847 100644 --- a/src/soc/intel/common/block/pmc/Makefile.inc +++ b/src/soc/intel/common/block/pmc/Makefile.inc @@ -6,4 +6,5 @@ ramstage-y += pmclib.c pmc_ipc.c smm-y += pmclib.c verstage-y += pmclib.c postcar-y += pmclib.c +ramstage-$(CONFIG_PMC_IPC_ACPI_INTERFACE) += pmc_ipc.c endif diff --git a/src/soc/intel/common/block/pmc/pmc_ipc.c b/src/soc/intel/common/block/pmc/pmc_ipc.c index 7decf790a9..7c811aed44 100644 --- a/src/soc/intel/common/block/pmc/pmc_ipc.c +++ b/src/soc/intel/common/block/pmc/pmc_ipc.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include #include +#include #include #include @@ -64,16 +66,16 @@ static int check_ipc_sts(void) if (IPC_STS_HAS_ERROR(ipc_sts)) { printk(BIOS_ERR, "IPC_STS.error_code 0x%x\n", IPC_STS_ERROR_CODE(ipc_sts)); - return -1; + return PMC_IPC_ERROR; } - return 0; + return PMC_IPC_SUCCESS; } udelay(50); } while (!stopwatch_expired(&sw)); printk(BIOS_ERR, "PMC IPC timeout after %u ms\n", PMC_IPC_XFER_TIMEOUT_MS); - return -1; + return PMC_IPC_TIMEOUT; } enum cb_err pmc_send_ipc_cmd(uint32_t cmd, const struct pmc_ipc_buffer *wbuf, @@ -94,3 +96,151 @@ enum cb_err pmc_send_ipc_cmd(uint32_t cmd, const struct pmc_ipc_buffer *wbuf, return CB_SUCCESS; } + +void pmc_ipc_acpi_fill_ssdt(void) +{ + const struct fieldlist ipcs_fields[] = { + FIELDLIST_OFFSET(PMC_IPC_CMD_OFFSET), /* Command */ + FIELDLIST_NAMESTR("ICMD", 32), /* Command Register */ + FIELDLIST_OFFSET(PMC_IPC_STS_OFFSET), /* Status */ + FIELDLIST_NAMESTR("IBSY", 1), /* Status Busy */ + FIELDLIST_NAMESTR("IERR", 1), /* Status Error */ + FIELDLIST_RESERVED(14), + FIELDLIST_NAMESTR("IERC", 8), /* Status Error Code */ + FIELDLIST_OFFSET(IPC_WBUF0), /* Write Buffer */ + FIELDLIST_NAMESTR("IWB0", 32), /* Write Buffer 0 */ + FIELDLIST_NAMESTR("IWB1", 32), /* Write Buffer 1 */ + FIELDLIST_NAMESTR("IWB2", 32), /* Write Buffer 2 */ + FIELDLIST_NAMESTR("IWB3", 32), /* Write Buffer 3 */ + FIELDLIST_OFFSET(IPC_RBUF0), /* Read Buffer */ + FIELDLIST_NAMESTR("IRB0", 32), /* Read Buffer 0 */ + FIELDLIST_NAMESTR("IRB1", 32), /* Read Buffer 1 */ + FIELDLIST_NAMESTR("IRB2", 32), /* Read Buffer 2 */ + FIELDLIST_NAMESTR("IRB3", 32), /* Read Buffer 3 */ + }; + const struct opregion ipcs_opregion = OPREGION("IPCM", SYSTEMMEMORY, + soc_read_pmc_base(), 0xff); + int i; + + /* Package with return value and read buffer. */ + acpigen_write_name("RVAL"); + acpigen_write_package(5); + for (i = 0; i < 5; ++i) + acpigen_write_integer(0); + acpigen_pop_len(); + + acpigen_write_method_serialized("IPCS", 7); + + acpigen_write_opregion(&ipcs_opregion); + acpigen_write_field("IPCM", ipcs_fields, ARRAY_SIZE(ipcs_fields), + FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); + + /* Fill write buffer data registers. */ + acpigen_write_store_op_to_namestr(ARG3_OP, "IWB0"); + acpigen_write_store_op_to_namestr(ARG4_OP, "IWB1"); + acpigen_write_store_op_to_namestr(ARG5_OP, "IWB2"); + acpigen_write_store_op_to_namestr(ARG6_OP, "IWB3"); + + /* Program the command register with command and size of write data. */ + acpigen_write_store_int_to_op(0, LOCAL0_OP); + + /* Local0 += (Arg0 << PMC_IPC_CMD_COMMAND_SHIFT) */ + acpigen_emit_byte(ADD_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_shiftleft_op_int(ARG0_OP, PMC_IPC_CMD_COMMAND_SHIFT); + acpigen_emit_byte(LOCAL0_OP); + + /* Local0 += (Arg1 << PMC_IPC_CMD_SUB_COMMAND_SHIFT) */ + acpigen_emit_byte(ADD_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_shiftleft_op_int(ARG1_OP, PMC_IPC_CMD_SUB_COMMAND_SHIFT); + acpigen_emit_byte(LOCAL0_OP); + + /* Local1 = PMC_IPC_CMD_NO_MSI */ + acpigen_write_store_int_to_op(PMC_IPC_CMD_NO_MSI, LOCAL1_OP); + /* Local0 += (Local1 << PMC_IPC_CMD_MSI_SHIFT) */ + acpigen_emit_byte(ADD_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_shiftleft_op_int(LOCAL1_OP, PMC_IPC_CMD_MSI_SHIFT); + acpigen_emit_byte(LOCAL0_OP); + + /* Local0 += (Arg1 << PMC_IPC_CMD_SIZE_SHIFT) */ + acpigen_emit_byte(ADD_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_shiftleft_op_int(ARG2_OP, PMC_IPC_CMD_SIZE_SHIFT); + acpigen_emit_byte(LOCAL0_OP); + + /* Start mailbox command with one 32bit write. */ + acpigen_write_store_op_to_namestr(LOCAL0_OP, "ICMD"); + + /* Read status register to get busy/error status. */ + acpigen_write_store_int_to_op(PMC_IPC_XFER_TIMEOUT_MS, LOCAL1_OP); + + /* While (Local1 > 0) */ + acpigen_emit_byte(WHILE_OP); + acpigen_write_len_f(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_emit_byte(ZERO_OP); + + /* If (IBSY == 0) { Return (SUCCESS) } */ + acpigen_write_if_lequal_namestr_int("IBSY", 0); + acpigen_set_package_element_int("RVAL", 0, PMC_IPC_SUCCESS); + acpigen_set_package_element_namestr("RVAL", 1, "IRB0"); + acpigen_set_package_element_namestr("RVAL", 2, "IRB1"); + acpigen_set_package_element_namestr("RVAL", 3, "IRB2"); + acpigen_set_package_element_namestr("RVAL", 4, "IRB3"); + acpigen_write_return_namestr("RVAL"); + acpigen_pop_len(); + + /* If (IERR == 1) { Return (ERROR) } */ + acpigen_write_if_lequal_namestr_int("IERR", 1); + acpigen_write_debug_string("IPCS ERROR"); + acpigen_write_debug_namestr("IERC"); + acpigen_set_package_element_int("RVAL", 0, PMC_IPC_ERROR); + acpigen_write_return_namestr("RVAL"); + acpigen_pop_len(); + + /* Sleep (1) */ + acpigen_write_sleep(1); + /* Decrement (Local1) */ + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_pop_len(); /* While */ + + /* Return (TIMEOUT) */ + acpigen_write_debug_string("IPCS TIMEOUT"); + acpigen_set_package_element_int("RVAL", 0, PMC_IPC_TIMEOUT); + acpigen_write_return_namestr("RVAL"); + + acpigen_pop_len(); /* Method */ +} + +void pmc_ipc_acpi_set_pci_clock(unsigned int pcie_rp, unsigned int clock_pin, bool enable) +{ + const uint32_t data[] = { + 1 << clock_pin, /* Clock pin to be modified */ + (enable ? 1 : 0) << clock_pin, /* Clock pin to set */ + 1 << pcie_rp, /* PCIe root port to be modified */ + (enable ? 1 : 0) << pcie_rp, /* PCIe root port to set */ + }; + const char *method = acpi_device_path_join(pcidev_path_on_root(PCH_DEVFN_PMC), "IPCS"); + + if (!method) { + printk(BIOS_ERR, "%s: Unable to find PMC device IPCS method\n", __func__); + return; + } + + /* + * The PMC IPC mailbox method takes 7 arguments: + * IPCS (COMMAND, SUB_ID, SIZE, DATA0, DATA1, DATA2, DATA3) + */ + acpigen_emit_namestring(method); + acpigen_write_integer(PMC_IPC_CMD_ID_SET_PCIE_CLOCK); + acpigen_write_integer(0); + acpigen_write_integer(sizeof(data)); + acpigen_write_dword(data[0]); + acpigen_write_dword(data[1]); + acpigen_write_dword(data[2]); + acpigen_write_dword(data[3]); +} From 5742357e4d9f9acd2b13d6db32bf22bb58545c17 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Thu, 27 Aug 2020 23:39:10 -0700 Subject: [PATCH 133/262] Atlas: Wake up AP on AC plug and unplug This patch makes Atlas resume from S0ix by AC plug and unplug. BUG=b:165328935 BRANCH=atlas TEST=Put Atlas in suspend. Wake it up by AC plug. TEST=Put Atlas in suspend. Wake it up by AC unplug. Signed-off-by: Daisuke Nojiri Change-Id: I95676d785bfc1488a8c1bdd3d56f2c38d95f3fb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47144 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali --- .../google/poppy/variants/atlas/include/variant/ec.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h index 5e377f2168..50afd42956 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h @@ -32,12 +32,14 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) /* - * EC can wake from S3 with lid or power button or key press or - * mode change event. + * EC can wake from S3 with lid, power button, key press, + * mode change event, or AC plug/unplug. */ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)) #define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) From e0c60f3d39182a1105aa9e39683abdbc2e600162 Mon Sep 17 00:00:00 2001 From: Jakub Czapiga Date: Fri, 9 Oct 2020 10:07:47 +0200 Subject: [PATCH 134/262] tests: Add lib/timestamp-test test case Signed-off-by: Jakub Czapiga Change-Id: I39abfc644fef085cef2175086a0e45a040b244de Reviewed-on: https://review.coreboot.org/c/coreboot/+/46968 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg --- tests/include/stubs/timestamp.h | 6 ++ tests/lib/Makefile.inc | 8 +- tests/lib/timestamp-test.c | 138 ++++++++++++++++++++++++++++++++ tests/stubs/timestamp.c | 29 +++++++ 4 files changed, 180 insertions(+), 1 deletion(-) create mode 100644 tests/include/stubs/timestamp.h create mode 100644 tests/lib/timestamp-test.c create mode 100644 tests/stubs/timestamp.c diff --git a/tests/include/stubs/timestamp.h b/tests/include/stubs/timestamp.h new file mode 100644 index 0000000000..10b81598c4 --- /dev/null +++ b/tests/include/stubs/timestamp.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include + +void dummy_timestamp_set(uint64_t v); + +void dummy_timestamp_tick_freq_mhz_set(int v); diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 3062bcaa70..27773b7f39 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -4,6 +4,7 @@ tests-y += string-test tests-y += b64_decode-test tests-y += hexstrtobin-test tests-y += imd-test +tests-y += timestamp-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -17,4 +18,9 @@ hexstrtobin-test-srcs += src/lib/hexstrtobin.c imd-test-srcs += tests/lib/imd-test.c imd-test-srcs += tests/stubs/console.c -imd-test-srcs += src/lib/imd.c \ No newline at end of file +imd-test-srcs += src/lib/imd.c + +timestamp-test-srcs += tests/lib/timestamp-test.c +timestamp-test-srcs += tests/stubs/timestamp.c +timestamp-test-srcs += tests/stubs/console.c +timestamp-test-stage := romstage diff --git a/tests/lib/timestamp-test.c b/tests/lib/timestamp-test.c new file mode 100644 index 0000000000..8dc103d203 --- /dev/null +++ b/tests/lib/timestamp-test.c @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "../lib/timestamp.c" +#include +#include +#include "stubs/timestamp.h" + +/* Timestamp region definition */ +#define TIMESTAMP_REGION_SIZE (1 * KiB) +TEST_REGION(timestamp, TIMESTAMP_REGION_SIZE); + +void test_timestamp_init(void **state) +{ + timestamp_init(1000); + + assert_non_null(glob_ts_table); +} + +void test_timestamp_add(void **state) +{ + const int base_multipler = 2000; + const int timestamp_base = 1000; + struct timestamp_entry *entry; + int i; + + timestamp_init(timestamp_base); + + timestamp_add(TS_START_ROMSTAGE, base_multipler); + + assert_int_equal(1, glob_ts_table->num_entries); + + entry = &glob_ts_table->entries[0]; + assert_int_equal(1, entry->entry_id); + assert_int_equal(base_multipler - timestamp_base, /* Added timestamp reduced by base */ + entry->entry_stamp); + + /* Add few timestamps to check if all of them will be added properly */ + for (i = 1; i < 10; ++i) + timestamp_add(i + 1, base_multipler * (i + 1)); + + assert_int_equal(10, glob_ts_table->num_entries); + + for (i = 0; i < 10; ++i) { + entry = &glob_ts_table->entries[i]; + assert_int_equal(i + 1, entry->entry_id); + assert_int_equal(base_multipler * (i + 1) - timestamp_base, + entry->entry_stamp); + } +} + +void test_timestamp_add_now(void **state) +{ + const int base_multipler = 2000; + const int timestamp_base = 1000; + struct timestamp_entry *entry; + + /* Initialize with base timestamp of 1000. + * This value will be subtracted from each timestamp + * when adding it. + */ + timestamp_init(timestamp_base); + + dummy_timestamp_set(base_multipler); + + timestamp_add_now(TS_START_ROMSTAGE); + + assert_int_equal(1, glob_ts_table->num_entries); + + entry = &glob_ts_table->entries[0]; + + assert_int_equal(1, entry->entry_id); + assert_int_equal(base_multipler - timestamp_base, /* Added timestamp reduced by base */ + entry->entry_stamp); +} + +void test_timestamp_rescale_table(void **state) +{ + const int base_multipler = 1000; + int i; + + timestamp_init(0); + + /* Add few timestamps to check if all of them will be rescaled properly */ + for (i = 1; i <= 10; ++i) + timestamp_add(i, base_multipler * i); + + /* Check if all entries were added to table */ + assert_int_equal(10, glob_ts_table->num_entries); + + timestamp_rescale_table(2, 4); + + /* Check if there is the same number of entries */ + assert_int_equal(10, glob_ts_table->num_entries); + + for (i = 0; i < glob_ts_table->num_entries; ++i) + assert_int_equal(base_multipler * (i + 1) / 4 * 2, + glob_ts_table->entries[i].entry_stamp); +} + +void test_get_us_since_boot(void **state) +{ + const int base_multipler = 10000; + const int timestamp_base = 1000; + const int freq_base = 100; + + timestamp_init(timestamp_base); + dummy_timestamp_set(base_multipler); + dummy_timestamp_tick_freq_mhz_set(freq_base); + /* There is a need to update this field manually, because cbmem hooks are not used. */ + glob_ts_table->tick_freq_mhz = freq_base; + + assert_int_equal((base_multipler - timestamp_base) / freq_base, get_us_since_boot()); +} + +int setup_timestamp_and_freq(void **state) +{ + dummy_timestamp_set(0); + dummy_timestamp_tick_freq_mhz_set(1); + + return 0; +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup(test_timestamp_init, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_timestamp_add, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_timestamp_add_now, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_timestamp_rescale_table, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_get_us_since_boot, setup_timestamp_and_freq), + }; + +#if CONFIG(COLLECT_TIMESTAMPS) + return cmocka_run_group_tests(tests, NULL, NULL); +#else + return 0; +#endif +} diff --git a/tests/stubs/timestamp.c b/tests/stubs/timestamp.c new file mode 100644 index 0000000000..3fd739f6f5 --- /dev/null +++ b/tests/stubs/timestamp.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "stubs/timestamp.h" + +static uint64_t timestamp_value = 0; +static int timestamp_tick_freq_mhz_value = 1; + +/* Provides way to control timestamp value */ +void dummy_timestamp_set(uint64_t v) +{ + timestamp_value = v; +} + +/* Provides way to control timestamp tick frequency MHz value */ +void dummy_timestamp_tick_freq_mhz_set(int v) +{ + timestamp_tick_freq_mhz_value = v; +} + +/* Reimplementation of timestamp getter to control behaviour */ +uint64_t timestamp_get(void) +{ + return timestamp_value; +} + +int timestamp_tick_freq_mhz(void) +{ + return timestamp_tick_freq_mhz_value; +} From a944b547dcec1bb52cd8e04c6a6286bc3ec902cb Mon Sep 17 00:00:00 2001 From: David Wu Date: Wed, 4 Nov 2020 17:36:36 +0800 Subject: [PATCH 135/262] mb/google/volteer/var/voema: Add memory parts and generate DRAM IDs This change adds memory parts used by variant voema to mem_parts_used.txt and generates DRAM IDs allocated to these parts. Added memory 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E BUG=b:171755775 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu Change-Id: I24d466f92a7e0fa3ab2f6241f0b5af025c53ed98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47228 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Caveh Jalali --- .../google/volteer/variants/voema/memory/Makefile.inc | 5 +++-- .../volteer/variants/voema/memory/dram_id.generated.txt | 2 ++ .../google/volteer/variants/voema/memory/mem_parts_used.txt | 6 ++---- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc index b0ca2223a8..3c8ea4876f 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = MT53E1G64D8NW-046 WT:E diff --git a/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt index fa247902ee..02e7443467 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt @@ -1 +1,3 @@ DRAM Part Name ID to assign +MT53E512M64D4NW-046 WT:E 0 (0000) +MT53E1G64D8NW-046 WT:E 1 (0001) diff --git a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt index f51b3af398..b74da4a5f0 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt +++ b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt @@ -1,4 +1,2 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/ddr4 or util/spd_tools/lp4x -# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. +MT53E512M64D4NW-046 WT:E +MT53E1G64D8NW-046 WT:E From 835a2fa73727578e95fc7d0058f6ef89e93d56dc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 5 Nov 2020 15:04:54 +0100 Subject: [PATCH 136/262] soc/intel/common/acpi: create pep.asl from lpit.asl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Copy lpit.asl to pep.asl to have a clean patch series without moving files and to be able to keep the replace-patch CB:46471 as small as possible to avoid confusion. Change-Id: Ib1c019039ef0c518cf678af6109ba914b7f47bb6 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/47245 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/acpi/acpi/pep.asl | 103 +++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 src/soc/intel/common/block/acpi/acpi/pep.asl diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl new file mode 100644 index 0000000000..6159685b53 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/pep.asl @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define LPID_DSM_ARG2_ENUM_FUNCTIONS 0 +#define LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS 1 + +#define LPID_DSM_ARG2_GET_CRASH_DUMP_DEV 2 +#define LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY 3 +#define LPID_DSM_ARG2_DISPLAY_ON_NOTIFY 4 +#define LPID_DSM_ARG2_S0IX_ENTRY 5 +#define LPID_DSM_ARG2_S0IX_EXIT 6 + +External(\_SB.MS0X, MethodObj) +External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj) +External(\_SB.PCI0.EGPM, MethodObj) +External(\_SB.PCI0.RGPM, MethodObj) + +Scope(\_SB) +{ + Device(LPID) + { + Name(_ADR, 0x00000000) + Name(_CID, EISAID("PNP0D80")) + Name(UUID, ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66")) + Method(_DSM, 4) + { + If(Arg0 == ^UUID) { + /* + * Enum functions + */ + If(Arg2 == LPID_DSM_ARG2_ENUM_FUNCTIONS) { + Return(Buffer(One) {0x60}) + } + /* + * Function 1 - Get Device Constraints + */ + If(Arg2 == LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { + Return(Package(5) {0, Ones, Ones, Ones, Ones}) + } + /* + * Function 2 - Get Crash Dump Device + */ + If(Arg2 == LPID_DSM_ARG2_GET_CRASH_DUMP_DEV) { + Return(Buffer(One) {0x0}) + } + /* + * Function 3 - Display Off Notification + */ + If(Arg2 == LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY) { + } + /* + * Function 4 - Display On Notification + */ + If(Arg2 == LPID_DSM_ARG2_DISPLAY_ON_NOTIFY) { + } + /* + * Function 5 - Low Power S0 Entry Notification + */ + If(Arg2 == LPID_DSM_ARG2_S0IX_ENTRY) { + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(1) + } + + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(1) + } + + /* + * Save the current PM bits then + * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG + */ + If (CondRefOf (\_SB.PCI0.EGPM)) + { + \_SB.PCI0.EGPM () + } + } + /* + * Function 6 - Low Power S0 Exit Notification + */ + If(Arg2 == LPID_DSM_ARG2_S0IX_EXIT) { + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(0) + } + + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(0) + } + + /* Restore GPIO all Community PM */ + If (CondRefOf (\_SB.PCI0.RGPM)) + { + \_SB.PCI0.RGPM () + } + } + } + + Return(Buffer(One) {0x00}) + } // Method(_DSM) + } // Device (LPID) +} // End Scope(\_SB) From 5eac877b75f4c21970f4df777461879aeec2520e Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 23 Oct 2020 15:15:01 -0600 Subject: [PATCH 137/262] driver/usb/acpi: Add power resources for devices on USB ports Allow a USB device to define PowerResource in its SSDT AML code. PowerResouce ACPI generation expects SoC to define the callbacks for generating AML code for GPIO manipulation. Device requiring PowerResource needs to define following parameters: * Reset GPIO - Optional, GPIO to put device into reset or take it out of reset. * Reset delay - Delay after reset GPIO is asserted (default 0). * Reset off delay - Delay after reset GPIO is de-asserted (default 0). * Enable GPIO - Optional, GPIO to enable device. * Enable delay - Delay after enable GPIO is asserted (default 0). * Enable off delay - Delay after enable GPIO is de-asserted (default 0). BUG=b:163100335 TEST=Ensure that the Power Resource ACPI object is added under the concerned USB device. Change-Id: Icc1aebfb9e3e646a7f608f0cd391079fd30dd1c0 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/46713 Reviewed-by: Tim Wawrzynczak Reviewed-by: Peichao Wang Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/drivers/usb/acpi/chip.h | 14 ++++++++++++++ src/drivers/usb/acpi/usb_acpi.c | 20 ++++++++++++++++++-- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 8cd926888d..8afdf6fc8e 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -44,7 +44,21 @@ struct drivers_usb_acpi_config { bool use_custom_pld; struct acpi_pld custom_pld; + /* Does the device have a power resource? */ + bool has_power_resource; + + /* GPIO used to take device out of reset or to put it into reset. */ struct acpi_gpio reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned int reset_delay_ms; + /* Delay to be inserted after device is put into reset. */ + unsigned int reset_off_delay_ms; + /* GPIO used to enable device. */ + struct acpi_gpio enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned int enable_delay_ms; + /* Delay to be inserted after device is disabled. */ + unsigned int enable_off_delay_ms; }; #endif /* __USB_ACPI_CHIP_H__ */ diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 55ef1d361f..8a597e3e9e 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -11,9 +11,10 @@ static bool usb_acpi_add_gpios_to_crs(struct drivers_usb_acpi_config *cfg) { /* - * Return false if reset GPIO is not provided. + * Return false if reset GPIO is not provided or is provided as part of power + * resource. */ - if (cfg->reset_gpio.pin_count == 0) + if (cfg->has_power_resource || cfg->reset_gpio.pin_count == 0) return false; return true; @@ -61,6 +62,21 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev) acpi_dp_write(dsd); } + if (config->has_power_resource) { + const struct acpi_power_res_params power_res_params = { + &config->reset_gpio, + config->reset_delay_ms, + config->reset_off_delay_ms, + &config->enable_gpio, + config->enable_delay_ms, + config->enable_off_delay_ms, + NULL, + 0, + 0 + }; + acpi_device_add_power_res(&power_res_params); + } + acpigen_pop_len(); printk(BIOS_INFO, "%s: %s at %s\n", path, From 2313e54bf91761e61c777a699cf4047a5f4689cc Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 19 Aug 2020 12:40:25 -0600 Subject: [PATCH 138/262] mb/google/dedede: Add support for variant specific SMI sleep flow This support is required to power off certain components that exist only in certain variants. BUG=None TEST=Build and boot Boten to OS. Change-Id: Ib43ada784666919a4d26246a683dad7f3546fabb Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/44587 Tested-by: build bot (Jenkins) Reviewed-by: Peichao Wang Reviewed-by: Marco Chen Reviewed-by: Furquan Shaikh --- src/mainboard/google/dedede/smihandler.c | 6 ++++++ .../dedede/variants/baseboard/include/baseboard/variants.h | 3 +++ 2 files changed, 9 insertions(+) diff --git a/src/mainboard/google/dedede/smihandler.c b/src/mainboard/google/dedede/smihandler.c index 20f0207edb..c50578da70 100644 --- a/src/mainboard/google/dedede/smihandler.c +++ b/src/mainboard/google/dedede/smihandler.c @@ -21,6 +21,8 @@ void mainboard_smi_sleep(u8 slp_typ) pads = variant_sleep_gpio_table(&num); gpio_configure_pads(pads, num); + variant_smi_sleep(slp_typ); + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } @@ -41,3 +43,7 @@ void mainboard_smi_espi_handler(void) { chromeec_smi_process_events(); } + +void __weak variant_smi_sleep(u8 slp_typ) +{ +} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index bb41e45931..e7bfd868aa 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -36,4 +36,7 @@ int variant_memory_sku(void); */ bool variant_mem_is_half_populated(void); +/* Allow each variants to customize SMI sleep flow. */ +void variant_smi_sleep(u8 slp_typ); + #endif /*__BASEBOARD_VARIANTS_H__ */ From 3d4513e7c8e27dbb9c6b941c4eb4144d38ff5cee Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 23 Oct 2020 16:54:11 -0600 Subject: [PATCH 139/262] mb/google/dedede/var/boten: Add LTE power on/off sequence LTE module used in boten has a specific power on/off sequence. GPIOs related to power sequnce are: * GPP_A10 - LTE_PWR_OFF_R_ODL * GPP_H17 - LTE_RESET_R_ODL 1. Power on: GPP_A10 -> 20ms -> GPP_H17 2. Power off: GPP_H17 -> 10ms -> GPP_A10 3. Warm reset: Power off -> 500ms -> Power on Configure the GPIOs based on these requirements. BUG=b:163100335 TEST=Build and boot Boten to OS. Ensure that the LTE module power sequence requirements are met. Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/44588 Tested-by: build bot (Jenkins) Reviewed-by: Peichao Wang Reviewed-by: Marco Chen Reviewed-by: Furquan Shaikh --- .../google/dedede/variants/boten/Makefile.inc | 2 ++ .../google/dedede/variants/boten/gpio.c | 5 ++++ .../dedede/variants/boten/overridetree.cb | 5 ++++ .../google/dedede/variants/boten/variant.c | 23 +++++++++++++++++++ 4 files changed, 35 insertions(+) create mode 100644 src/mainboard/google/dedede/variants/boten/variant.c diff --git a/src/mainboard/google/dedede/variants/boten/Makefile.inc b/src/mainboard/google/dedede/variants/boten/Makefile.inc index a3527099b9..67a7ab235a 100644 --- a/src/mainboard/google/dedede/variants/boten/Makefile.inc +++ b/src/mainboard/google/dedede/variants/boten/Makefile.inc @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/boten/gpio.c b/src/mainboard/google/dedede/variants/boten/gpio.c index f889c7fd69..c27daa4854 100644 --- a/src/mainboard/google/dedede/variants/boten/gpio.c +++ b/src/mainboard/google/dedede/variants/boten/gpio.c @@ -7,6 +7,9 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { + /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ + PAD_CFG_GPO(GPP_A10, 0, PLTRST), + /* C12 : AP_PEN_DET_ODL */ PAD_CFG_GPI_SCI(GPP_C12, NONE, DEEP, EDGE_SINGLE, NONE), /* C18 : AP_I2C_EMR_SDA */ @@ -38,6 +41,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_H6, NONE), /* H7 : AP_I2C_CAM_SCL */ PAD_NC(GPP_H7, NONE), + /* H17 : WWAN_RST_L => LTE_RESET_R_ODL */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), }; const struct pad_config *variant_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 4ec64579c2..4966aac491 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -65,6 +65,11 @@ chip soc/intel/jasperlake chip drivers/usb/acpi register "desc" = ""LTE"" register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" + register "reset_off_delay_ms" = "10" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "enable_delay_ms" = "20" device usb 2.3 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/dedede/variants/boten/variant.c b/src/mainboard/google/dedede/variants/boten/variant.c new file mode 100644 index 0000000000..2540fc7f2a --- /dev/null +++ b/src/mainboard/google/dedede/variants/boten/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static void power_off_lte_module(void) +{ + gpio_output(GPP_H17, 0); + mdelay(10); + gpio_output(GPP_A10, 0); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* + * Once the FW_CONFIG is provisioned, power off LTE module only under + * the situation where it is stuffed. + */ + if (slp_typ == ACPI_S5) + power_off_lte_module(); +} From 8a1ad138225e5a31d75cd77b9d7f183f3ab6d39c Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 5 Nov 2020 14:38:51 -0700 Subject: [PATCH 140/262] device: Move pci_dev_is_wake_source function Move this function to pci_ops.c, which is already included in the smm build. This is required to use this function in elog functionality, which is called from SMM. Signed-off-by: Tim Wawrzynczak Change-Id: Ie5583c04366c9a16bc1b00a6892d39eeafe5da49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47260 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian --- src/device/pci_device.c | 18 ------------------ src/device/pci_ops.c | 18 ++++++++++++++++++ src/include/device/pci.h | 9 --------- src/include/device/pci_ops.h | 8 ++++++++ 4 files changed, 26 insertions(+), 27 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 691ad6b316..6075ebeac7 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1648,21 +1648,3 @@ void pci_dev_disable_bus_master(const struct device *dev) pci_update_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER, 0x0); } #endif - -bool pci_dev_is_wake_source(const struct device *dev) -{ - unsigned int pm_cap; - uint16_t pmcs; - - if (dev->path.type != DEVICE_PATH_PCI) - return false; - - pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM); - if (!pm_cap) - return false; - - pmcs = pci_read_config16(dev, pm_cap + PCI_PM_CTRL); - - /* PCI Device is a wake source if PME_ENABLE and PME_STATUS are set in PMCS register. */ - return (pmcs & PCI_PM_CTRL_PME_ENABLE) && (pmcs & PCI_PM_CTRL_PME_STATUS); -} diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 90f45bf21a..aaa9f95fb1 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -78,3 +78,21 @@ void __noreturn pcidev_die(void) { die("PCI: dev is NULL!\n"); } + +bool pci_dev_is_wake_source(const struct device *dev) +{ + unsigned int pm_cap; + uint16_t pmcs; + + if (dev->path.type != DEVICE_PATH_PCI) + return false; + + pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM); + if (!pm_cap) + return false; + + pmcs = pci_s_read_config16(PCI_BDF(dev), pm_cap + PCI_PM_CTRL); + + /* PCI Device is a wake source if PME_ENABLE and PME_STATUS are set in PMCS register. */ + return (pmcs & PCI_PM_CTRL_PME_ENABLE) && (pmcs & PCI_PM_CTRL_PME_STATUS); +} diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 777f030355..045eec1aa6 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -79,15 +79,6 @@ void pci_bus_enable_resources(struct device *dev); void pci_bus_reset(struct bus *bus); struct device *pci_probe_dev(struct device *dev, struct bus *bus, unsigned int devfn); - -/* - * Determine if the given PCI device is the source of wake from sleep by checking PME_STATUS and - * PME_ENABLE bits in PM control and status register. - * - * Returns true if PCI device is wake source, false otherwise. - */ -bool pci_dev_is_wake_source(const struct device *dev); - void do_pci_scan_bridge(struct device *dev, void (*do_scan_bus)(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn)); diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index cdf02d6a56..7fe7d429e2 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -209,4 +209,12 @@ u16 pci_find_capability(const struct device *dev, u16 cap) return pci_s_find_capability(PCI_BDF(dev), cap); } +/* + * Determine if the given PCI device is the source of wake from sleep by checking PME_STATUS and + * PME_ENABLE bits in PM control and status register. + * + * Returns true if PCI device is wake source, false otherwise. + */ +bool pci_dev_is_wake_source(const struct device *dev); + #endif /* PCI_OPS_H */ From 8a78f5903952f1dee3ecbde8b8ea613c78639d48 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 3 Nov 2020 13:16:27 -0700 Subject: [PATCH 141/262] soc/intel/tigerlake: Add PCH PCIe RPs wake up events to event log All wakes by a PCH PCIe root port were lumped under one event source; this commit splits them up so each root port gets its own ID in the event log. BUG=b:172279061 BRANCH=volteer Signed-off-by: Tim Wawrzynczak Change-Id: Icebcac3b69c605ecf6df37733b641397ea3c3ad0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47182 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian --- src/soc/intel/tigerlake/elog.c | 39 ++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 84f0a7ed4f..a46afbb24c 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -2,11 +2,13 @@ #include #include -#include +#include #include #include #include #include +#include +#include static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { @@ -20,6 +22,39 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } +static void pch_log_rp_wake_source(void) +{ + size_t i; + struct pme_map { + pci_devfn_t devfn; + unsigned int wake_source; + }; + + const struct pme_map pme_map[] = { + { PCH_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 }, + { PCH_DEVFN_PCIE2, ELOG_WAKE_SOURCE_PME_PCIE2 }, + { PCH_DEVFN_PCIE3, ELOG_WAKE_SOURCE_PME_PCIE3 }, + { PCH_DEVFN_PCIE4, ELOG_WAKE_SOURCE_PME_PCIE4 }, + { PCH_DEVFN_PCIE5, ELOG_WAKE_SOURCE_PME_PCIE5 }, + { PCH_DEVFN_PCIE6, ELOG_WAKE_SOURCE_PME_PCIE6 }, + { PCH_DEVFN_PCIE7, ELOG_WAKE_SOURCE_PME_PCIE7 }, + { PCH_DEVFN_PCIE8, ELOG_WAKE_SOURCE_PME_PCIE8 }, + { PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 }, + { PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 }, + { PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 }, + { PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 }, + }; + + for (i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); ++i) { + const struct device *dev = pcidev_path_on_root(pme_map[i].devfn); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) + elog_add_event_wake(pme_map[i].wake_source, 0); + } +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -32,7 +67,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) /* PCI Express (TODO: determine wake device) */ if (ps->pm1_sts & PCIEXPWAK_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + pch_log_rp_wake_source(); /* PME (TODO: determine wake device) */ if (ps->gpe0_sts[GPE_STD] & PME_STS) From 5145e23a3510b6c6129b5e8aa56876fcfcb1adb6 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 3 Nov 2020 13:24:14 -0700 Subject: [PATCH 142/262] soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log All wakes by a PCH PCIe root port were lumped under one event source; this commit splits them up so each root port gets its own ID in the event log. BUG=b:172279061 BRANCH=volteer Change-Id: Icdb10043700c20ddb6ae93747a731005fd233a70 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/47183 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian --- src/soc/intel/jasperlake/elog.c | 41 ++++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index 235dc6e3cf..0546bb0215 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -2,11 +2,13 @@ #include #include -#include +#include #include #include #include #include +#include +#include static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { @@ -20,6 +22,39 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } +static void pch_log_rp_wake_source(void) +{ + size_t i; + struct pme_map { + pci_devfn_t devfn; + unsigned int wake_source; + }; + + const struct pme_map pme_map[] = { + { PCH_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 }, + { PCH_DEVFN_PCIE2, ELOG_WAKE_SOURCE_PME_PCIE2 }, + { PCH_DEVFN_PCIE3, ELOG_WAKE_SOURCE_PME_PCIE3 }, + { PCH_DEVFN_PCIE4, ELOG_WAKE_SOURCE_PME_PCIE4 }, + { PCH_DEVFN_PCIE5, ELOG_WAKE_SOURCE_PME_PCIE5 }, + { PCH_DEVFN_PCIE6, ELOG_WAKE_SOURCE_PME_PCIE6 }, + { PCH_DEVFN_PCIE7, ELOG_WAKE_SOURCE_PME_PCIE7 }, + { PCH_DEVFN_PCIE8, ELOG_WAKE_SOURCE_PME_PCIE8 }, + { PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 }, + { PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 }, + { PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 }, + { PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 }, + }; + + for (i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); ++i) { + const struct device *dev = pcidev_path_on_root(pme_map[i].devfn); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) + elog_add_event_wake(pme_map[i].wake_source, 0); + } +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -30,9 +65,9 @@ static void pch_log_wake_source(struct chipset_power_state *ps) if (ps->pm1_sts & RTC_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - /* PCI Express (TODO: determine wake device) */ + /* PCI Express */ if (ps->pm1_sts & PCIEXPWAK_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + pch_log_rp_wake_source(); /* PME (TODO: determine wake device) */ if (ps->gpe0_sts[GPE_STD] & PME_STS) From 8af39ff63364e71b142e5ca4ce3d560ac651af08 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Fri, 6 Nov 2020 12:00:10 +0530 Subject: [PATCH 143/262] mb/google/dedede/variants/magolor: Update Power Limit2 minimum value Update Power Limit2 (PL2) minimum value to the same as maximum value for magolor board. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=b:168353037 BRANCH=None TEST=Build and test on magolor board Change-Id: I74e960de506d366cba2c8aefb23f9e69337fd163 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/47285 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/dedede/variants/magolor/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 625546e7ff..33b89d605b 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -92,7 +92,7 @@ chip soc/intel/jasperlake .time_window_max = 1 * MSECS_PER_SEC, .granularity = 200,}" register "controls.power_limits.pl2" = "{ - .min_power = 7000, + .min_power = 12000, .max_power = 12000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, From df79757a3f3d969b00fa198d50efcdd6517e00fe Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Date: Mon, 5 Oct 2020 12:44:18 +0000 Subject: [PATCH 144/262] drivers/usb/acpi: Add support for privacy_gpio Some devices, such as cameras, can implement a physical switch to disable the input on demand. Think of it like the typical privacy sticker on the notebooks, but more elegant. In order to notify the system about the status this feature, a GPIO is typically used. The map between a GPIO and the feature is done via ACPI, the same way as the reset_gpio works. This patch implements an extra field for the described privacy gpio. This gpio does not require any extra handling from the power management. BUG=b:169840271 Change-Id: Idcc65c9a13eca6f076ac3c68aaa1bed3c481df3d Signed-off-by: Ricardo Ribalda Reviewed-on: https://review.coreboot.org/c/coreboot/+/46961 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/usb/acpi/chip.h | 7 +++++ src/drivers/usb/acpi/usb_acpi.c | 47 ++++++++++++++++++++++++++------- 2 files changed, 44 insertions(+), 10 deletions(-) diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 8afdf6fc8e..73c69cc89f 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -59,6 +59,13 @@ struct drivers_usb_acpi_config { unsigned int enable_delay_ms; /* Delay to be inserted after device is disabled. */ unsigned int enable_off_delay_ms; + + /* + * Define a GPIO that shows the privacy status of the USB device. + * E.g. On a camera: if it is one, it is recording black frames. + * E.g. On a mic: if it is one, it is recording white-noise. + */ + struct acpi_gpio privacy_gpio; }; #endif /* __USB_ACPI_CHIP_H__ */ diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 8a597e3e9e..9d68d0a923 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -10,14 +10,27 @@ static bool usb_acpi_add_gpios_to_crs(struct drivers_usb_acpi_config *cfg) { - /* - * Return false if reset GPIO is not provided or is provided as part of power - * resource. - */ - if (cfg->has_power_resource || cfg->reset_gpio.pin_count == 0) - return false; + if (cfg->privacy_gpio.pin_count) + return true; - return true; + if (cfg->reset_gpio.pin_count && !cfg->has_power_resource) + return true; + + return false; +} + +static int usb_acpi_write_gpio(struct acpi_gpio *gpio, int *curr_index) +{ + int ret = -1; + + if (gpio->pin_count == 0) + return ret; + + acpi_device_write_gpio(gpio); + ret = *curr_index; + (*curr_index)++; + + return ret; } static void usb_acpi_fill_ssdt_generator(const struct device *dev) @@ -50,15 +63,29 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev) /* Resources */ if (usb_acpi_add_gpios_to_crs(config) == true) { struct acpi_dp *dsd; + int idx = 0; + int reset_gpio_index = -1; + int privacy_gpio_index; acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); - acpi_device_write_gpio(&config->reset_gpio); + if (!config->has_power_resource) { + reset_gpio_index = usb_acpi_write_gpio( + &config->reset_gpio, &idx); + } + privacy_gpio_index = usb_acpi_write_gpio(&config->privacy_gpio, + &idx); acpigen_write_resourcetemplate_footer(); dsd = acpi_dp_new_table("_DSD"); - acpi_dp_add_gpio(dsd, "reset-gpio", path, 0, 0, - config->reset_gpio.active_low); + if (reset_gpio_index >= 0) + acpi_dp_add_gpio(dsd, "reset-gpio", path, + reset_gpio_index, 0, + config->reset_gpio.active_low); + if (privacy_gpio_index >= 0) + acpi_dp_add_gpio(dsd, "privacy-gpio", path, + privacy_gpio_index, 0, + config->privacy_gpio.active_low); acpi_dp_write(dsd); } From 43d0a7e66c1503a9fbd9f8653861a343a3225f45 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Date: Mon, 5 Oct 2020 12:53:46 +0000 Subject: [PATCH 145/262] mb/google/hatch/jinlon: Describe the privacy_gpio Add information regarding the privacy pin on the overridetree and gpio. BUG=b:169840271 Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7 Signed-off-by: Ricardo Ribalda Reviewed-on: https://review.coreboot.org/c/coreboot/+/46962 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/jinlon/gpio.c | 2 ++ .../google/hatch/variants/jinlon/overridetree.cb | 13 +++++++++++++ 2 files changed, 15 insertions(+) diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 88f009202d..4029f062db 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -18,6 +18,8 @@ static const struct pad_config gpio_table[] = { * using this pin, expose this pin to driver. */ PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* D4 : Camera Privacy Status */ + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH), /* E0 : View Angle Management */ PAD_CFG_GPO(GPP_E0, 0, DEEP), /* F3 : MEM_STRAP_3 */ diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index fc3bb854b0..f042401b0c 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -80,6 +80,19 @@ chip soc/intel/cannonlake device generic 0 on end end end # Integrated Graphics Device + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + # The Linux Kernel does not allow an inverted BOTH_EDGE irq + # So we need to use GpioIO() instead of GpioInt() + # https://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt + register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D4)" + device usb 2.6 on end + end + end + end + end # USB xHCI device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" From 2b13ca5bcdc15b894665c7f0a0d26c45c1e46efc Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Date: Thu, 29 Oct 2020 15:00:26 +0100 Subject: [PATCH 146/262] mb/google/volteer/eldrid: Describe the privacy_gpio Add information regarding the privacy pin on the overridetree and the gpio. BUG=b:171888751 Change-Id: I1ab19a863715ba5a928dd7c16402d398e5475edc Signed-off-by: Ricardo Ribalda Reviewed-on: https://review.coreboot.org/c/coreboot/+/46964 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/volteer/Kconfig | 1 + src/mainboard/google/volteer/variants/eldrid/gpio.c | 2 +- src/mainboard/google/volteer/variants/eldrid/overridetree.cb | 4 ++++ 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 23dbf68fe9..a5cc1966dc 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -14,6 +14,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_SPI_ACPI select DRIVERS_SOUNDWIRE_ALC5682 select DRIVERS_SOUNDWIRE_MAX98373 + select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SKUID diff --git a/src/mainboard/google/volteer/variants/eldrid/gpio.c b/src/mainboard/google/volteer/variants/eldrid/gpio.c index 4f6650b2f9..3d627e3b81 100644 --- a/src/mainboard/google/volteer/variants/eldrid/gpio.c +++ b/src/mainboard/google/volteer/variants/eldrid/gpio.c @@ -63,7 +63,7 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPO(GPP_C23, 1, DEEP), /* D4 : IMGCLKOUT0# ==> CAMMERA_SWITCH */ - PAD_CFG_GPI(GPP_D4, NONE, DEEP), + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH), /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 249505fc41..91fbbea5d0 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -227,6 +227,10 @@ chip soc/intel/tigerlake chip drivers/usb/acpi register "desc" = ""USB2 Camera"" register "type" = "UPC_TYPE_INTERNAL" + # The Linux Kernel does not allow an inverted BOTH_EDGE irq + # So we need to use GpioIO() instead of GpioInt() + # https://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt + register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D4)" device ref usb2_port5 on end end chip drivers/usb/acpi From e3f030ecbbcef21ea8c6858e656bd9a7c07e5df8 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Thu, 5 Nov 2020 13:04:38 +0530 Subject: [PATCH 147/262] soc/intel/jasperlake: Update reserved GPIO names in gpio_soc_defs.h Multiple GPIOs were defined as a reserved GPIO in JasperLake. Correcting this GPIOs with proper name to align with EDS volume 2 Also removing unused GPIOs at the end of community 4 (group E). Since those reserved GPIOs are at the end of the community, it won't affect the offset calculations within community. This change will also help us aligning pad numbering with kernel pin-ctrl drivers too. Reference: DOC#618876 (EDS volume 2) BUG=None BRANCH=None TEST=Platform boots fine and basic functionality such as SD, Wifi works. Change-Id: I8326b7181d47a177261656f51602638d8ce80fbb Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/47232 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/gpio.c | 35 ++- .../jasperlake/include/soc/gpio_soc_defs.h | 243 +++++++++--------- 2 files changed, 132 insertions(+), 146 deletions(-) diff --git a/src/soc/intel/jasperlake/gpio.c b/src/soc/intel/jasperlake/gpio.c index 52c147fb04..2f13015534 100644 --- a/src/soc/intel/jasperlake/gpio.c +++ b/src/soc/intel/jasperlake/gpio.c @@ -34,10 +34,10 @@ static const struct reset_mapping rst_map_com0[] = { static const struct pad_group jsl_community0_groups[] = { INTEL_GPP_BASE(GPP_F0, GPP_F0, GPP_F19, 0), /* GPP_F */ - INTEL_GPP(GPP_F0, GPIO_RSVD_0, GPIO_RSVD_8), + INTEL_GPP(GPP_F0, GPIO_SPI0_IO_2, GPIO_SPI0_CLK_LOOPBK), INTEL_GPP_BASE(GPP_F0, GPP_B0, GPP_B23, 32), /* GPP_B */ - INTEL_GPP(GPP_F0, GPIO_RSVD_9, GPIO_RSVD_10), - INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_RSVD_11, 64), /* GPP_A */ + INTEL_GPP(GPP_F0, GPIO_GSPI0_CLK_LOOPBK, GPIO_GSPI1_CLK_LOOPBK), + INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_ESPI_CLK_LOOPBK, 64), /* GPP_A */ INTEL_GPP_BASE(GPP_F0, GPP_S0, GPP_S7, 96), /* GPP_S */ INTEL_GPP_BASE(GPP_F0, GPP_R0, GPP_R7, 128), /* GPP_R */ }; @@ -45,7 +45,7 @@ static const struct pad_group jsl_community0_groups[] = { static const struct pad_group jsl_community1_groups[] = { INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 160), /* GPP_H */ INTEL_GPP_BASE(GPP_H0, GPP_D0, GPP_D23, 192), /* GPP_D */ - INTEL_GPP(GPP_H0, GPIO_RSVD_12, GPIO_RSVD_13), + INTEL_GPP(GPP_H0, GPIO_GSPI2_CLK_LOOPBK, GPIO_SPI1_CLK_LOOPBK), INTEL_GPP_BASE(GPP_H0, VGPIO_0, VGPIO_39, 224), /* VGPIO */ INTEL_GPP_BASE(GPP_H0, GPP_C0, GPP_C23, 256), /* GPP_C */ }; @@ -53,13 +53,12 @@ static const struct pad_group jsl_community1_groups[] = { /* This community is not visible to the OS */ static const struct pad_group jsl_community2_groups[] = { INTEL_GPP(GPD0, GPD0, GPD10), /* GPD */ - INTEL_GPP(GPD0, GPIO_RSVD_14, GPIO_RSVD_17), + INTEL_GPP(GPD0, GPIO_INPUT3VSEL, GPIO_DRAM_RESETB), }; static const struct pad_group jsl_community4_groups[] = { - INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_18, GPIO_RSVD_23), - INTEL_GPP_BASE(GPIO_RSVD_18, GPP_E0, GPP_E23, 288), /* GPP_E */ - INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_24, GPIO_RSVD_36), + INTEL_GPP(GPIO_L_BKLTEN, GPIO_L_BKLTEN, GPIO_MLK_RSTB), + INTEL_GPP_BASE(GPIO_L_BKLTEN, GPP_E0, GPP_E23, 288), /* GPP_E */ }; static const struct pad_group jsl_community5_groups[] = { @@ -70,8 +69,8 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { /* GPP F, B, A, S, R */ [COMM_0] = { .port = PID_GPIOCOM0, - .first_pad = GPP_F0, - .last_pad = GPP_R7, + .first_pad = GPIO_COM0_START, + .last_pad = GPIO_COM0_END, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -90,8 +89,8 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { /* GPP H, D, VGPIO, C */ [COMM_1] = { .port = PID_GPIOCOM1, - .first_pad = GPP_H0, - .last_pad = GPP_C23, + .first_pad = GPIO_COM1_START, + .last_pad = GPIO_COM1_END, .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -110,8 +109,8 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { /* GPD */ [COMM_2] = { .port = PID_GPIOCOM2, - .first_pad = GPD0, - .last_pad = GPIO_RSVD_17, + .first_pad = GPIO_COM2_START, + .last_pad = GPIO_COM2_END, .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -130,8 +129,8 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { /* GPP E */ [COMM_4] = { .port = PID_GPIOCOM4, - .first_pad = GPIO_RSVD_18, - .last_pad = GPIO_RSVD_36, + .first_pad = GPIO_COM4_START, + .last_pad = GPIO_COM4_END, .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -150,8 +149,8 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { /* GPP G */ [COMM_5] = { .port = PID_GPIOCOM5, - .first_pad = GPP_G0, - .last_pad = GPP_G7, + .first_pad = GPIO_COM5_START, + .last_pad = GPIO_COM5_END, .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h index 8d6064c8f7..25a0625842 100644 --- a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h @@ -53,64 +53,64 @@ #define GPP_F19 19 /* Group B */ -#define GPIO_RSVD_0 20 -#define GPIO_RSVD_1 21 -#define GPIO_RSVD_2 22 -#define GPIO_RSVD_3 23 -#define GPIO_RSVD_4 24 -#define GPIO_RSVD_5 25 -#define GPIO_RSVD_6 26 -#define GPIO_RSVD_7 27 -#define GPIO_RSVD_8 28 -#define GPP_B0 29 -#define GPP_B1 30 -#define GPP_B2 31 -#define GPP_B3 32 -#define GPP_B4 33 -#define GPP_B5 34 -#define GPP_B6 35 -#define GPP_B7 36 -#define GPP_B8 37 -#define GPP_B9 38 -#define GPP_B10 39 -#define GPP_B11 40 -#define GPP_B12 41 -#define GPP_B13 42 -#define GPP_B14 43 -#define GPP_B15 44 -#define GPP_B16 45 -#define GPP_B17 46 -#define GPP_B18 47 -#define GPP_B19 48 -#define GPP_B20 49 -#define GPP_B21 50 -#define GPP_B22 51 -#define GPP_B23 52 -#define GPIO_RSVD_9 53 -#define GPIO_RSVD_10 54 +#define GPIO_SPI0_IO_2 20 +#define GPIO_SPI0_IO_3 21 +#define GPIO_SPI0_MOSI_IO_0 22 +#define GPIO_SPI0_MOSI_IO_1 23 +#define GPIO_SPI0_TPM_CSB 24 +#define GPIO_SPI0_FLASH_0_CSB 25 +#define GPIO_SPI0_FLASH_1_CSB 26 +#define GPIO_SPI0_CLK 27 +#define GPIO_SPI0_CLK_LOOPBK 28 +#define GPP_B0 29 +#define GPP_B1 30 +#define GPP_B2 31 +#define GPP_B3 32 +#define GPP_B4 33 +#define GPP_B5 34 +#define GPP_B6 35 +#define GPP_B7 36 +#define GPP_B8 37 +#define GPP_B9 38 +#define GPP_B10 39 +#define GPP_B11 40 +#define GPP_B12 41 +#define GPP_B13 42 +#define GPP_B14 43 +#define GPP_B15 44 +#define GPP_B16 45 +#define GPP_B17 46 +#define GPP_B18 47 +#define GPP_B19 48 +#define GPP_B20 49 +#define GPP_B21 50 +#define GPP_B22 51 +#define GPP_B23 52 +#define GPIO_GSPI0_CLK_LOOPBK 53 +#define GPIO_GSPI1_CLK_LOOPBK 54 /* Group A */ -#define GPP_A0 55 -#define GPP_A1 56 -#define GPP_A2 57 -#define GPP_A3 58 -#define GPP_A4 59 -#define GPP_A5 60 -#define GPP_A6 61 -#define GPP_A7 62 -#define GPP_A8 63 -#define GPP_A9 64 -#define GPP_A10 65 -#define GPP_A11 66 -#define GPP_A12 67 -#define GPP_A13 68 -#define GPP_A14 69 -#define GPP_A15 70 -#define GPP_A16 71 -#define GPP_A17 72 -#define GPP_A18 73 -#define GPP_A19 74 -#define GPIO_RSVD_11 75 +#define GPP_A0 55 +#define GPP_A1 56 +#define GPP_A2 57 +#define GPP_A3 58 +#define GPP_A4 59 +#define GPP_A5 60 +#define GPP_A6 61 +#define GPP_A7 62 +#define GPP_A8 63 +#define GPP_A9 64 +#define GPP_A10 65 +#define GPP_A11 66 +#define GPP_A12 67 +#define GPP_A13 68 +#define GPP_A14 69 +#define GPP_A15 70 +#define GPP_A16 71 +#define GPP_A17 72 +#define GPP_A18 73 +#define GPP_A19 74 +#define GPIO_ESPI_CLK_LOOPBK 75 /* Group S */ #define GPP_S0 76 @@ -163,32 +163,32 @@ #define GPP_H23 115 /* Group D */ -#define GPP_D0 116 -#define GPP_D1 117 -#define GPP_D2 118 -#define GPP_D3 119 -#define GPP_D4 120 -#define GPP_D5 121 -#define GPP_D6 122 -#define GPP_D7 123 -#define GPP_D8 124 -#define GPP_D9 125 -#define GPP_D10 126 -#define GPP_D11 127 -#define GPP_D12 128 -#define GPP_D13 129 -#define GPP_D14 130 -#define GPP_D15 131 -#define GPP_D16 132 -#define GPP_D17 133 -#define GPP_D18 134 -#define GPP_D19 135 -#define GPP_D20 136 -#define GPP_D21 137 -#define GPP_D22 138 -#define GPP_D23 139 -#define GPIO_RSVD_12 140 -#define GPIO_RSVD_13 141 +#define GPP_D0 116 +#define GPP_D1 117 +#define GPP_D2 118 +#define GPP_D3 119 +#define GPP_D4 120 +#define GPP_D5 121 +#define GPP_D6 122 +#define GPP_D7 123 +#define GPP_D8 124 +#define GPP_D9 125 +#define GPP_D10 126 +#define GPP_D11 127 +#define GPP_D12 128 +#define GPP_D13 129 +#define GPP_D14 130 +#define GPP_D15 131 +#define GPP_D16 132 +#define GPP_D17 133 +#define GPP_D18 134 +#define GPP_D19 135 +#define GPP_D20 136 +#define GPP_D21 137 +#define GPP_D22 138 +#define GPP_D23 139 +#define GPIO_GSPI2_CLK_LOOPBK 140 +#define GPIO_SPI1_CLK_LOOPBK 141 /* Group VGPIO */ #define VGPIO_0 142 @@ -252,33 +252,33 @@ #define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1) /* Group GPD */ -#define GPD0 195 -#define GPD1 196 -#define GPD2 197 -#define GPD3 198 -#define GPD4 199 -#define GPD5 200 -#define GPD6 201 -#define GPD7 202 -#define GPD8 203 -#define GPD9 204 -#define GPD10 205 -#define GPIO_RSVD_14 206 -#define GPIO_RSVD_15 207 -#define GPIO_RSVD_16 208 -#define GPIO_RSVD_17 209 +#define GPD0 195 +#define GPD1 196 +#define GPD2 197 +#define GPD3 198 +#define GPD4 199 +#define GPD5 200 +#define GPD6 201 +#define GPD7 202 +#define GPD8 203 +#define GPD9 204 +#define GPD10 205 +#define GPIO_INPUT3VSEL 206 +#define GPIO_SLP_SUSB 207 +#define GPIO_WAKEB 208 +#define GPIO_DRAM_RESETB 209 #define GPIO_COM2_START GPD0 -#define GPIO_COM2_END GPIO_RSVD_17 +#define GPIO_COM2_END GPIO_DRAM_RESETB #define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1) /* Group E */ -#define GPIO_RSVD_18 210 -#define GPIO_RSVD_19 211 -#define GPIO_RSVD_20 212 -#define GPIO_RSVD_21 213 -#define GPIO_RSVD_22 214 -#define GPIO_RSVD_23 215 +#define GPIO_L_BKLTEN 210 +#define GPIO_L_BKLTCTL 211 +#define GPIO_L_VDDEN 212 +#define GPIO_SYS_PWROK 213 +#define GPIO_SYS_RESETB 214 +#define GPIO_MLK_RSTB 215 #define GPP_E0 216 #define GPP_E1 217 #define GPP_E2 218 @@ -303,39 +303,26 @@ #define GPP_E21 237 #define GPP_E22 238 #define GPP_E23 239 -#define GPIO_RSVD_24 240 -#define GPIO_RSVD_25 241 -#define GPIO_RSVD_26 242 -#define GPIO_RSVD_27 243 -#define GPIO_RSVD_28 244 -#define GPIO_RSVD_29 245 -#define GPIO_RSVD_30 246 -#define GPIO_RSVD_31 247 -#define GPIO_RSVD_32 248 -#define GPIO_RSVD_33 249 -#define GPIO_RSVD_34 250 -#define GPIO_RSVD_35 251 -#define GPIO_RSVD_36 252 -#define GPIO_COM4_START GPIO_RSVD_18 -#define GPIO_COM4_END GPIO_RSVD_36 +#define GPIO_COM4_START GPIO_L_BKLTEN +#define GPIO_COM4_END GPP_E23 #define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1) /* Group G */ -#define GPP_G0 253 -#define GPP_G1 254 -#define GPP_G2 255 -#define GPP_G3 256 -#define GPP_G4 257 -#define GPP_G5 258 -#define GPP_G6 259 -#define GPP_G7 260 +#define GPP_G0 240 +#define GPP_G1 241 +#define GPP_G2 242 +#define GPP_G3 243 +#define GPP_G4 244 +#define GPP_G5 245 +#define GPP_G6 246 +#define GPP_G7 247 #define GPIO_COM5_START GPP_G0 #define GPIO_COM5_END GPP_G7 #define NUM_GPIO_COM5_PADS (GPIO_COM5_END - GPIO_COM5_START + 1) -#define TOTAL_PADS 261 +#define TOTAL_PADS 248 #define COMM_0 0 #define COMM_1 1 From 4a08736242d04fab5b6db09a6118cd992e038f9e Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Tue, 27 Oct 2020 17:19:20 +0530 Subject: [PATCH 148/262] soc/intel/jasperlake: Correct GPIO pad sequence for community pad group In gpio.c file, we have community group array for each comm, representing gpio groups within that community. Like there might be group H,D, VGPIO and C within community 1. Community also may have some reserved gpio and we also define those in an array which indicates OS can't use those GPIO (through PAD_BASE_NONE) Now when we define reserved pads in the middle of actual community pads, it creates an issue while calculating an offset for GPIO host own pad register. This is because function actually checks current gpio index (lets say vgpio_39 in our case) and tries to get group index from an array which we have defined. If we have defined reserved gpios in between 2 communities, index calculated will also account for reserved GPIO and register offset calculation will move to next set of register (offset 0xC instead of offset 0x8). Because of this coreboot won't configure HOST_OWN_PAD register correctly and driver will not be able to get non-SMI interrupts for related gpio. Align pad group as per EDS and pin-ctrl driver in linux kernel. Reference: DOC#618876 (EDS volume 2) BUG=None BRANCH=None TEST=VGPIO community index is correctly calculated. Drawlat board boots fine with this change and warm reset also works. Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/46842 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian --- src/soc/intel/jasperlake/gpio.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/src/soc/intel/jasperlake/gpio.c b/src/soc/intel/jasperlake/gpio.c index 2f13015534..18405fc01a 100644 --- a/src/soc/intel/jasperlake/gpio.c +++ b/src/soc/intel/jasperlake/gpio.c @@ -33,36 +33,33 @@ static const struct reset_mapping rst_map_com0[] = { */ static const struct pad_group jsl_community0_groups[] = { - INTEL_GPP_BASE(GPP_F0, GPP_F0, GPP_F19, 0), /* GPP_F */ - INTEL_GPP(GPP_F0, GPIO_SPI0_IO_2, GPIO_SPI0_CLK_LOOPBK), - INTEL_GPP_BASE(GPP_F0, GPP_B0, GPP_B23, 32), /* GPP_B */ - INTEL_GPP(GPP_F0, GPIO_GSPI0_CLK_LOOPBK, GPIO_GSPI1_CLK_LOOPBK), - INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_ESPI_CLK_LOOPBK, 64), /* GPP_A */ - INTEL_GPP_BASE(GPP_F0, GPP_S0, GPP_S7, 96), /* GPP_S */ - INTEL_GPP_BASE(GPP_F0, GPP_R0, GPP_R7, 128), /* GPP_R */ + INTEL_GPP_BASE(GPP_F0, GPP_F0, GPP_F19, 320), /* GPP_F */ + INTEL_GPP(GPP_F0, GPIO_SPI0_IO_2, GPIO_SPI0_CLK_LOOPBK),/* SPI0 */ + INTEL_GPP_BASE(GPP_F0, GPP_B0, GPIO_GSPI1_CLK_LOOPBK, 32),/* GPP_B */ + INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_ESPI_CLK_LOOPBK, 64),/* GPP_A */ + INTEL_GPP_BASE(GPP_F0, GPP_S0, GPP_S7, 96), /* GPP_S */ + INTEL_GPP_BASE(GPP_F0, GPP_R0, GPP_R7, 128), /* GPP_R */ }; static const struct pad_group jsl_community1_groups[] = { INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 160), /* GPP_H */ - INTEL_GPP_BASE(GPP_H0, GPP_D0, GPP_D23, 192), /* GPP_D */ - INTEL_GPP(GPP_H0, GPIO_GSPI2_CLK_LOOPBK, GPIO_SPI1_CLK_LOOPBK), + INTEL_GPP_BASE(GPP_H0, GPP_D0, GPIO_SPI1_CLK_LOOPBK, 192),/* GPP_D */ INTEL_GPP_BASE(GPP_H0, VGPIO_0, VGPIO_39, 224), /* VGPIO */ INTEL_GPP_BASE(GPP_H0, GPP_C0, GPP_C23, 256), /* GPP_C */ }; /* This community is not visible to the OS */ static const struct pad_group jsl_community2_groups[] = { - INTEL_GPP(GPD0, GPD0, GPD10), /* GPD */ - INTEL_GPP(GPD0, GPIO_INPUT3VSEL, GPIO_DRAM_RESETB), + INTEL_GPP(GPD0, GPD0, GPIO_DRAM_RESETB), /* GPD */ }; static const struct pad_group jsl_community4_groups[] = { - INTEL_GPP(GPIO_L_BKLTEN, GPIO_L_BKLTEN, GPIO_MLK_RSTB), - INTEL_GPP_BASE(GPIO_L_BKLTEN, GPP_E0, GPP_E23, 288), /* GPP_E */ + INTEL_GPP(GPIO_L_BKLTEN, GPIO_L_BKLTEN, GPIO_MLK_RSTB), /* Reserved */ + INTEL_GPP_BASE(GPIO_L_BKLTEN, GPP_E0, GPP_E23, 288), /* GPP_E */ }; static const struct pad_group jsl_community5_groups[] = { - INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 320), /* GPP_G */ + INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 0), /* GPP_G */ }; static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { From befec1e92ef3dca5e7e7cf8e5c8c465e22f68ea2 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 6 Nov 2020 00:26:03 +0100 Subject: [PATCH 149/262] soc/amd/common: add Kconfig help text to pre-family-17h-only blocks The cpu/car code only applies to pre-family-17h CPUs that still use cache as RAM (CAR) and the PI code only applies to the pre-FSP vendor code blob binaryPI interface. Change-Id: I5a13d7e202bb745255fabb46110850c36b07de7a Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47274 Reviewed-by: Marshall Dawson Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/cpu/Kconfig | 3 +++ src/soc/amd/common/block/pi/Kconfig | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 5941599df0..f6756e18f8 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -8,3 +8,6 @@ config SOC_AMD_COMMON_BLOCK_CAR it may not be appropriate for a romstage implementation without additional consideration. If this option is not used, the SOC must implement these functions separately. + This is only used for AMD CPU before family 17h. From family 17h on + the RAM is already initialized by the PSP before the x86 cores are + released from reset. diff --git a/src/soc/amd/common/block/pi/Kconfig b/src/soc/amd/common/block/pi/Kconfig index f0917bb767..cf8c79ae50 100644 --- a/src/soc/amd/common/block/pi/Kconfig +++ b/src/soc/amd/common/block/pi/Kconfig @@ -3,7 +3,8 @@ config SOC_AMD_COMMON_BLOCK_PI select HAVE_DEBUG_RAM_SETUP default n help - This option builds functions that interface AMD's AGESA. + This option builds functions that interface AMD's AGESA reference + code packaged in the binaryPI form. if SOC_AMD_COMMON_BLOCK_PI From 12985c1dd78b4a641ea7bd1ff34f1d7d4361d309 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 6 Nov 2020 11:45:41 +0100 Subject: [PATCH 150/262] soc/intel/xeon_sp: Look up the IIO_HOB only once The HOB does not move, place its location in .bss. Change-Id: I2c6dbe4d64138e45fa1dfe7580ffa70d0441bd88 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47294 Reviewed-by: Marc Jones Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/util.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index feacca497e..75f8a8a10a 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -105,9 +105,12 @@ int get_platform_thread_count(void) const IIO_UDS *get_iio_uds(void) { size_t hob_size; - const IIO_UDS *hob; + static const IIO_UDS *hob; const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + if (hob != NULL) + return hob; + hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); assert(hob != NULL && hob_size != 0); return hob; From 0ee920bf6439d5f404a77971a5f7e3fa04339924 Mon Sep 17 00:00:00 2001 From: Bryant Ou Date: Mon, 14 Sep 2020 23:41:41 -0700 Subject: [PATCH 151/262] console: Override uart base address Add a new CONFIG_OVERRIDE_UART_FOR_CONSOLE token to override the index of uart port, platform use a get_uart_for_console routine to decide what index value should be used for console. Signed-off-by: Bryant Ou Change-Id: I2079bd1e5ffa209553383b6aafe3b8724849ba2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45405 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones Reviewed-by: Jonathan Zhang --- src/console/Kconfig | 10 ++++++++++ src/include/console/uart.h | 18 +++++++++++++++--- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 283488c27b..548b701d9f 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -58,6 +58,14 @@ if CONSOLE_SERIAL comment "device-specific UART" depends on HAVE_UART_SPECIAL +config OVERRIDE_UART_FOR_CONSOLE + bool + help + Set to "y" when the platform overrides the index of uart port by providing + a get_uart_for_console routine. + +if !OVERRIDE_UART_FOR_CONSOLE + config UART_FOR_CONSOLE int prompt "Index for UART port to use for console" if !FIXED_UART_FOR_CONSOLE @@ -87,6 +95,8 @@ depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 2 comment "Serial port base address = 0x2e8" depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 3 +endif + config UART_OVERRIDE_BAUDRATE bool help diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 6126a89d57..2e23d43a4e 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -20,6 +20,18 @@ static inline unsigned int get_uart_baudrate(void) } #endif +#if CONFIG(OVERRIDE_UART_FOR_CONSOLE) +/* Return the index of uart port, define this in your platform + * when need to use variables to override the index. + */ +unsigned int get_uart_for_console(void); +#else +static inline unsigned int get_uart_for_console(void) +{ + return CONFIG_UART_FOR_CONSOLE; +} +#endif + /* Returns the divisor value for a given baudrate. * The formula to satisfy is: * refclk / divisor = baudrate * oversample @@ -56,15 +68,15 @@ void oxford_remap(unsigned int new_base); #if __CONSOLE_SERIAL_ENABLE__ static inline void __uart_init(void) { - uart_init(CONFIG_UART_FOR_CONSOLE); + uart_init(get_uart_for_console()); } static inline void __uart_tx_byte(u8 data) { - uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); + uart_tx_byte(get_uart_for_console(), data); } static inline void __uart_tx_flush(void) { - uart_tx_flush(CONFIG_UART_FOR_CONSOLE); + uart_tx_flush(get_uart_for_console()); } #else static inline void __uart_init(void) {} From 4d4256e499e850a724d228d2e676c0f32af67093 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 4 Nov 2020 14:50:40 -0600 Subject: [PATCH 152/262] mb/purism/librem_mini: Adjust GPIO pad config per schematics MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - set pads GPP_B6/B8 for PCIe CLK_REQ lines - set pad GPP_B14 to speaker output - adjust comment for GPP_C22 / USB3_P1_PWREN - set pad GPP_E4 to NF1 / SATA_DEVSLP0 - set pads GPP_E9/E10 to USB2_OC0#/USB2_OC1# Change-Id: I8bf8af620370ec2d4c864e513db5d710a9c65d27 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47220 Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../librem_cnl/variants/librem_mini/gpio.c | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index b35ee4c64d..8fa4ac57ec 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -99,14 +99,14 @@ static const struct pad_config gpio_table[] = { /* GPP_B5 - NC */ PAD_NC(GPP_B5, NONE), - /* GPP_B6 - NC */ - PAD_NC(GPP_B6, NONE), + /* GPP_B6 - SRCCLKREQ1# / SSD_CLK_REQ# */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* GPP_B7 - NC */ PAD_NC(GPP_B7, NONE), - /* GPP_B8 - NC */ - PAD_NC(GPP_B8, NONE), + /* GPP_B8 - SRCCLKREQ3# / LAN2_CLK_REQ# */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* GPP_B9 - NC */ PAD_NC(GPP_B9, NONE), @@ -123,8 +123,8 @@ static const struct pad_config gpio_table[] = { /* GPP_B13 - PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - /* GPP_B14 - GPIO */ - PAD_CFG_GPO(GPP_B14, 1, PLTRST), + /* GPP_B14 - SPKR */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* GPP_B15 - NC */ PAD_NC(GPP_B15, NONE), @@ -507,7 +507,7 @@ static const struct pad_config gpio_table[] = { /* GPP_C21 - NC */ PAD_NC(GPP_C21, NONE), - /* GPP_C22 - GPIO */ + /* GPP_C22 - USB3_P1_PWREN */ PAD_CFG_GPO(GPP_C22, 1, PLTRST), /* GPP_C23 - NC */ @@ -527,8 +527,8 @@ static const struct pad_config gpio_table[] = { /* GPP_E3 - NC */ PAD_NC(GPP_E3, UP_20K), - /* GPP_E4 - GPIO */ - PAD_CFG_GPO(GPP_E4, 1, PLTRST), + /* GPP_E4 - SATA_DEVSLP0 */ + PAD_CFG_NF(GPP_E4, NONE, PLTRST, NF1), /* GPP_E5 - NC */ PAD_NC(GPP_E5, UP_20K), @@ -542,11 +542,11 @@ static const struct pad_config gpio_table[] = { /* GPP_E8 - SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), - /* GPP_E9 - RESERVED */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF5), + /* GPP_E9 - USB2_OC0# */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* GPP_E10 - RESERVED */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF5), + /* GPP_E10 - USB2_OC1# */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* GPP_E11 - USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), From e9523926152490d3f1c70ff8773b87ee54084e55 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 4 Nov 2020 15:04:06 -0600 Subject: [PATCH 153/262] mb/purism/librem_mini: Fix PCIe clock source mapping in devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Correct PCIe clock source mapping in devicetree now that the GPIO config has been fixed. Move ClkSrcUsage/ClkSrcClkReq registers under their associated PCIe root ports. Change-Id: Ibdaba51d971a39a6da6df82652b7420d7324dee5 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47221 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- .../variants/librem_mini/devicetree.cb | 22 +++++-------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 918fa0ef0e..becb9468c7 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -19,22 +19,6 @@ chip soc/intel/cannonlake # FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # All SRCCLKREQ pins mapped directly - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - - # Set all SRCCLKREQ pins as free-use - register "PcieClkSrcUsage[0]" = "0x80" - register "PcieClkSrcUsage[1]" = "0x80" - register "PcieClkSrcUsage[2]" = "0x80" - register "PcieClkSrcUsage[3]" = "0x80" - register "PcieClkSrcUsage[4]" = "0x80" - register "PcieClkSrcUsage[5]" = "0x80" - # Misc register "AcousticNoiseMitigation" = "1" @@ -211,6 +195,8 @@ chip soc/intel/cannonlake register "PcieRpSlotImplemented[7]" = "1" register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" + # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC + register "PcieClkSrcUsage[2]" = "0x80" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" end device pci 1d.0 off end # PCI Express Port 9 @@ -218,6 +204,8 @@ chip soc/intel/cannonlake device pci 00.0 on end # x1 (LAN) register "PcieRpSlotImplemented[9]" = "1" register "PcieRpEnable[9]" = "1" + register "PcieClkSrcUsage[3]" = "9" + register "PcieClkSrcClkReq[3]" = "3" end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 @@ -226,6 +214,8 @@ chip soc/intel/cannonlake register "PcieRpSlotImplemented[12]" = "1" register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[1]" = "12" + register "PcieClkSrcClkReq[1]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device pci 1d.5 off end # PCI Express Port 14 From 0e4f37f7a7c7812bf15b83fd841f22b497c41e9c Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 5 Nov 2020 11:34:50 -0600 Subject: [PATCH 154/262] mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add strings for M.2 keying and number of PCIe lanes. Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47251 Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../purism/librem_cnl/variants/librem_mini/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index becb9468c7..e2135b7fa9 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -197,7 +197,7 @@ chip soc/intel/cannonlake register "PcieRpLtrEnable[7]" = "1" # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC register "PcieClkSrcUsage[2]" = "0x80" - smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" end device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 on # PCI Express Port 10 From de10d8d6099a589ed60844fb28d1020577f64783 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 5 Nov 2020 11:36:13 -0600 Subject: [PATCH 155/262] mb/purism/librem_mini: drop PcieRpSlotImplemented from LAN PCIe MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The LAN NIC is onboard, not installed in a slot. Change-Id: I77ee7ee8c944b7942ca78d35cd881277c4030ab9 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47252 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons --- .../purism/librem_cnl/variants/librem_mini/devicetree.cb | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index e2135b7fa9..e8cc1e4f84 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -202,7 +202,6 @@ chip soc/intel/cannonlake device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 on # PCI Express Port 10 device pci 00.0 on end # x1 (LAN) - register "PcieRpSlotImplemented[9]" = "1" register "PcieRpEnable[9]" = "1" register "PcieClkSrcUsage[3]" = "9" register "PcieClkSrcClkReq[3]" = "3" From 22f028a3c7271b01e831b65f8118c205b23fe9a4 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 4 Nov 2020 15:32:18 -0600 Subject: [PATCH 156/262] mb/purism/librem_mini: Fix USB_OC mapping in devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Correct USB over-current mappings in devicetree now that the GPIO config has been fixed per schematics. Change-Id: I564630231933c7c17a2c0a2a403fdcca9189b92e Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47222 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- .../librem_cnl/variants/librem_mini/devicetree.cb | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index e8cc1e4f84..c39bccf249 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -146,16 +146,16 @@ chip soc/intel/cannonlake end end end - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-A front left upper + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A front left lower register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A front right lower + register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A front right upper register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left upper + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left lower register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper From 12d515dcc56230cba10884d425d8e07ed4562e0c Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 2 Nov 2020 17:19:53 -0600 Subject: [PATCH 157/262] mb/purism/librem_cnl: Add new variant 'Librem Mini v2' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Kconfig entries, and update existing documentation to accomodate both v1/v2 versions of the board. Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/46984 Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- Documentation/mainboard/purism/librem_mini.md | 40 +++++++++++-------- src/mainboard/purism/librem_cnl/Kconfig | 7 +++- src/mainboard/purism/librem_cnl/Kconfig.name | 5 +++ 3 files changed, 33 insertions(+), 19 deletions(-) diff --git a/Documentation/mainboard/purism/librem_mini.md b/Documentation/mainboard/purism/librem_mini.md index e098a24778..f8ee00d6d5 100644 --- a/Documentation/mainboard/purism/librem_mini.md +++ b/Documentation/mainboard/purism/librem_mini.md @@ -1,16 +1,19 @@ -# Purism Librem Mini +# Purism Librem Mini (v1, v2) This page describes how to run coreboot on the [Purism Librem Mini]. ```eval_rst +------------------+--------------------------------------------------+ -| CPU | Intel Core i7-8565U/8665U | +| CPU | Intel Core i7-8565U/8665U (v1) | +| | Intel Core i7-10510U (v2) | +------------------+--------------------------------------------------+ -| PCH | Whiskey Lake / Cannon Point LP | +| PCH | Whiskey Lake / Cannon Point LP (v1) | +| | Comet Lake LP Premium (Comet Lake-U) (v2) | +------------------+--------------------------------------------------+ | Super I/O, EC | ITE IT8528E | +------------------+--------------------------------------------------+ -| Coprocessor | Intel Management Engine (CSME 12.x) | +| Coprocessor | Intel Management Engine (CSME 12.x) (v1) | +| | Intel Management Engine (CSME 14.x) (v2) | +------------------+--------------------------------------------------+ ``` @@ -34,9 +37,9 @@ only the BIOS region is being modified). +-----------------+---------------------------------+---------------------+ ``` -FSP-M and FSP-S are obtained after splitting the Coffee Lake FSP binary (done -automatically by the coreboot build system and included into the image) from -the `3rdparty/fsp` submodule. +FSP-M and FSP-S are obtained after splitting the FSP binary (done automatically +by the coreboot build system and included into the image; Coffee Lake for v1, +Comet Lake for v2) from the `3rdparty/fsp` submodule. Microcode updates are automatically included into the coreboot image by the build system from the `3rdparty/intel-microcode` submodule. Official Purism release @@ -50,12 +53,14 @@ the [purism-blobs] repository. ## Intel Management Engine -The Librem Mini uses version 12.x of the Intel Management Engine (ME) / -Converged Security Engine (CSE). The ME/CSE is disabled using the High -Assurance Platform (HAP) bit, which puts the ME into a disabled state +The Librem Mini uses version 12.x (v1) or 14.x (v2) of the Intel Management +Engine (ME) / Converged Security Engine (CSE). The ME/CSE is disabled using +the High Assurance Platform (HAP) bit, which puts the ME into a disabled state after platform bring-up (BUP) and disables all PCI/HECI interfaces. This can be verified via the coreboot cbmem utility: -`sudo ./cbmem -1 | grep 'ME:'` + + `sudo ./cbmem -1 | grep 'ME:'` + provided coreboot has been modified to output the ME status even when the PCI device is not visible/active (as it is in Purism's release builds). @@ -64,8 +69,9 @@ the PCI device is not visible/active (as it is in Purism's release builds). ### Internal programming The main SPI flash can be accessed using [flashrom]. The first version -supporting the chipset is flashrom v1.2. Firmware an be easily flashed -with internal programmer (either BIOS region or full image). +supporting the chipset is flashrom v1.2 (v1.2-107-gb1f858f or later needed +for the Mini v2). Firmware an be easily flashed with internal programmer +(either BIOS region or full image). ### External programming @@ -100,17 +106,17 @@ desoldering it from the mainboard. ## Working * External displays via HDMI/DisplayPort with VGA option ROM or FSP/GOP init - (no libgfxinit support yet) - * SeaBIOS (1.13.x), Tianocore (CorebootPayloadpkg), Heads (Purism downstream) payloads + (no libgfxinit support yet) + * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), Heads (Purism downstream) payloads * Ethernet, m.2 2230 Wi-Fi * System firmware updates via flashrom * PCIe NVMe * m.2 and SATA III * Audio via front 3.5mm jack, HDMI, and DisplayPort * SMBus (reading SPD from DIMMs) - * Initialization with CFL FSP 2.0 + * Initialization with FSP 2.0 (CFL for v1, CML for v2) * S3 Suspend/Resume - * Booting PureOS 9.x, Debian 10.x, Qubes 4.0.3, Linux Mint 19.3, Windows 10 2004 + * Booting PureOS 10.x, Debian 11.x, Qubes 4.1.0-alpha1, Linux Mint 20, Windows 10 2004 ## Not working / untested diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig index 464350ce8c..39d57e6da4 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -20,15 +20,16 @@ config MAINBOARD_DIR config MAINBOARD_FAMILY string - default "Librem Mini" if BOARD_PURISM_LIBREM_MINI + default "Librem Mini" if BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2 config MAINBOARD_PART_NUMBER string default "Librem Mini" if BOARD_PURISM_LIBREM_MINI + default "Librem Mini v2" if BOARD_PURISM_LIBREM_MINI_V2 config VARIANT_DIR string - default "librem_mini" if BOARD_PURISM_LIBREM_MINI + default "librem_mini" if BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2 config DEVICETREE string @@ -37,6 +38,7 @@ config DEVICETREE config CBFS_SIZE hex default 0x800000 if BOARD_PURISM_LIBREM_MINI + default 0xA00000 if BOARD_PURISM_LIBREM_MINI_V2 config MAX_CPUS int @@ -53,6 +55,7 @@ config DIMM_SPD_SIZE config VGA_BIOS_ID string default "8086,3ea0" if BOARD_PURISM_LIBREM_MINI + default "8086,9b41" if BOARD_PURISM_LIBREM_MINI_V2 config PXE_ROM_ID string diff --git a/src/mainboard/purism/librem_cnl/Kconfig.name b/src/mainboard/purism/librem_cnl/Kconfig.name index 83f1495ab1..1d10e791f1 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig.name +++ b/src/mainboard/purism/librem_cnl/Kconfig.name @@ -2,3 +2,8 @@ config BOARD_PURISM_LIBREM_MINI bool "Librem Mini" select BOARD_PURISM_BASEBOARD_LIBREM_CNL select SOC_INTEL_WHISKEYLAKE + +config BOARD_PURISM_LIBREM_MINI_V2 + bool "Librem Mini v2" + select BOARD_PURISM_BASEBOARD_LIBREM_CNL + select SOC_INTEL_COMETLAKE_1 From 5851f9dae5e94cfae9e027da8302f80c65e5b647 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 2 Nov 2020 15:30:10 -0700 Subject: [PATCH 158/262] soc/intel/xeon_sp: Move set_bios_init_completion() Move set_bios_init_completion() and helper functions from skx and cpx soc_util.c to xeon common util.c. There are some slight differences between skx and cpx, so used the more correct cpx functions. Both cpx and skx platforms boot as expected. Change-Id: Ie416b3a43ccdd14a0eb542786593c2eb4d37450f Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/47172 Reviewed-by: Stefan Reinauer Reviewed-by: Jay Talbott Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/chip.c | 1 + .../intel/xeon_sp/cpx/include/soc/soc_util.h | 3 +- src/soc/intel/xeon_sp/cpx/soc_util.c | 129 +----------------- src/soc/intel/xeon_sp/include/soc/util.h | 1 + .../intel/xeon_sp/skx/include/soc/soc_util.h | 3 +- src/soc/intel/xeon_sp/skx/soc_util.c | 124 +---------------- src/soc/intel/xeon_sp/util.c | 129 ++++++++++++++++++ 7 files changed, 137 insertions(+), 253 deletions(-) diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 0049616223..3daff1372b 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -12,6 +12,7 @@ #include #include #include +#include /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 8c454bb29e..649e6b5004 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -15,7 +15,8 @@ uint8_t get_iiostack_info(struct iiostack_resource *info); const struct SystemMemoryMapHob *get_system_memory_map(void); -void set_bios_init_completion(void); +uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); + int soc_get_stack_for_port(int port); #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 149f2c01eb..973d2588c5 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -11,7 +10,6 @@ #include #include #include -#include const struct SystemMemoryMapHob *get_system_memory_map(void) { @@ -54,50 +52,7 @@ uint8_t get_iiostack_info(struct iiostack_resource *info) return hob->PlatformData.Pci64BitResourceAllocation; } -/* return true if command timed out else false */ -static bool wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask, - uint32_t target) -{ - const uint32_t max_delay = 5000; /* 5 seconds max */ - const uint32_t step_delay = 50; /* 50 us */ - struct stopwatch sw; - - stopwatch_init_msecs_expire(&sw, max_delay); - while ((pci_s_read_config32(dev, reg) & mask) != target) { - udelay(step_delay); - if (stopwatch_expired(&sw)) { - printk(BIOS_ERR, "%s timed out for dev: %x, reg: 0x%x, " - "mask: 0x%x, target: 0x%x\n", __func__, dev, reg, mask, target); - return true; /* timedout */ - } - } - return false; /* successful */ -} - -/* return true if command timed out else false */ -static bool write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data) -{ - /* verify bios is not in busy state */ - if (wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0)) - return true; /* timed out */ - - /* write data to data register */ - printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%x\n", __func__, - PCU_CR1_BIOS_MB_DATA_REG, data); - pci_s_write_config32(dev, PCU_CR1_BIOS_MB_DATA_REG, data); - - /* write the command */ - printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%lx\n", __func__, - PCU_CR1_BIOS_MB_INTERFACE_REG, command | BIOS_MB_RUN_BUSY_MASK); - pci_s_write_config32(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, - command | BIOS_MB_RUN_BUSY_MASK); - - /* wait for completion or time out*/ - return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, - BIOS_MB_RUN_BUSY_MASK, 0); -} - -static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) +uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) { const IIO_UDS *hob = get_iio_uds(); @@ -106,88 +61,6 @@ static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) return hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; } -/* return true if command timed out else false */ -static bool set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask, - uint32_t pcode_init_mask, uint32_t val) -{ - const uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); - const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); - - uint32_t reg = pci_s_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG); - reg &= (uint32_t) ~rst_cpl_mask; - reg |= val; - - /* update BIOS RESET completion bit */ - pci_s_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg); - - /* wait for PCU ack */ - return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask, - pcode_init_mask); -} - -static void set_bios_init_completion_for_package(uint32_t socket) -{ - uint32_t data; - bool timedout; - const uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); - const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); - - /* read PCU config */ - timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); - if (timedout) { - /* 2nd try */ - timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); - if (timedout) - die("BIOS PCU Misc Config Read timed out.\n"); - - /* Since the 1st try failed, we need to make sure PCU is in stable state */ - data = pci_s_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG); - printk(BIOS_SPEW, "%s - pci_s_read_config32 reg: 0x%x, data: 0x%x\n", - __func__, PCU_CR1_BIOS_MB_DATA_REG, data); - timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data); - if (timedout) - die("BIOS PCU Misc Config Write timed out.\n"); - } - - /* update RST_CPL3, PCODE_INIT_DONE3 */ - timedout = set_bios_reset_cpl_for_package(socket, RST_CPL3_MASK, - PCODE_INIT_DONE3_MASK, RST_CPL3_MASK); - if (timedout) - die("BIOS RESET CPL3 timed out.\n"); - - /* update RST_CPL4, PCODE_INIT_DONE4 */ - timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK, - PCODE_INIT_DONE4_MASK, RST_CPL4_MASK); - if (timedout) - die("BIOS RESET CPL4 timed out.\n"); - - /* set CSR_DESIRED_CORES_CFG2 lock bit */ - data = pci_s_read_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG); - data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK; - printk(BIOS_SPEW, "%s - pci_s_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n", - __func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data); - pci_s_write_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, data); -} - -void set_bios_init_completion(void) -{ - /* FIXME: This may need to be changed for multi-socket platforms */ - uint32_t sbsp_socket_id = 0; - - /* - * According to the BIOS Writer's Guide, the SBSP must be the last socket - * to receive the BIOS init completion message. So, we send it to all non-SBSP - * sockets first. - */ - for (uint32_t socket = 0; socket < soc_get_num_cpus(); ++socket) { - if (socket == sbsp_socket_id) - continue; - set_bios_init_completion_for_package(socket); - } - - /* And finally, take care of the SBSP */ - set_bios_init_completion_for_package(sbsp_socket_id); -} /* * EX: CPX-SP * Ports Stack Stack(HOB) IioConfigIou diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 73fc63da4c..014b238165 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -15,5 +15,6 @@ int get_platform_thread_count(void); const IIO_UDS *get_iio_uds(void); unsigned int soc_get_num_cpus(void); void xeonsp_init_cpu_config(void); +void set_bios_init_completion(void); #endif diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index fd0d4e2fbb..b42aec0976 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -17,7 +17,8 @@ void config_reset_cpl3_csrs(void); const struct SystemMemoryMapHob *get_system_memory_map(void); -void set_bios_init_completion(void); +uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); + int soc_get_stack_for_port(int port); #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 3faaed0f06..469fd60b5f 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include @@ -14,7 +13,6 @@ #include #include #include -#include /* @@ -83,51 +81,7 @@ uint8_t get_iiostack_info(struct iiostack_resource *info) return hob->PlatformData.Pci64BitResourceAllocation; } -/* return 1 if command timed out else 0 */ -static uint32_t wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask, - uint32_t target) -{ - uint32_t max_delay = 5000; /* 5 seconds max */ - uint32_t step_delay = 50; /* 50 us */ - struct stopwatch sw; - - stopwatch_init_msecs_expire(&sw, max_delay); - while ((pci_mmio_read_config32(dev, reg) & mask) != target) { - udelay(step_delay); - if (stopwatch_expired(&sw)) { - printk(BIOS_ERR, "%s timed out for dev: 0x%x, reg: 0x%x, " - "mask: 0x%x, target: 0x%x\n", __func__, dev, reg, mask, target); - return 1; /* timedout */ - } - } - return 0; /* successful */ -} - -/* return 1 if command timed out else 0 */ -static uint32_t write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data) -{ - /* verify bios is not in busy state */ - if (wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0)) - return 1; /* timed out */ - - /* write data to data register */ - printk(BIOS_SPEW, "%s - pci_mmio_write_config32 reg: 0x%x, data: 0x%x\n", __func__, - PCU_CR1_BIOS_MB_DATA_REG, data); - pci_mmio_write_config32(dev, PCU_CR1_BIOS_MB_DATA_REG, data); - - /* write the command */ - printk(BIOS_SPEW, "%s - pci_mmio_write_config32 reg: 0x%x, data: 0x%x\n", __func__, - PCU_CR1_BIOS_MB_INTERFACE_REG, - (uint32_t) (command | BIOS_MB_RUN_BUSY_MASK)); - pci_mmio_write_config32(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, - (uint32_t) (command | BIOS_MB_RUN_BUSY_MASK)); - - /* wait for completion or time out*/ - return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, - BIOS_MB_RUN_BUSY_MASK, 0); -} - -static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) +uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) { size_t hob_size; const IIO_UDS *hob; @@ -141,82 +95,6 @@ static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; } -/* return 1 if command timed out else 0 */ -static int set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask, - uint32_t pcode_init_mask, uint32_t val) -{ - uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); - pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); - - uint32_t reg = pci_mmio_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG); - reg &= (uint32_t) ~rst_cpl_mask; - reg |= rst_cpl_mask; - reg |= val; - - /* update BIOS RESET completion bit */ - pci_mmio_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg); - - /* wait for PCU ack */ - return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask, - pcode_init_mask); -} - -static void set_bios_init_completion_for_package(uint32_t socket) -{ - uint32_t data; - uint32_t timedout; - uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); - pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); - - /* read pcu config */ - timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); - if (timedout) { - /* 2nd try */ - timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); - if (timedout) - die("BIOS PCU Misc Config Read timed out.\n"); - - data = pci_mmio_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG); - printk(BIOS_SPEW, "%s - pci_mmio_read_config32 reg: 0x%x, data: 0x%x\n", - __func__, PCU_CR1_BIOS_MB_DATA_REG, data); - - /* write PCU config */ - timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data); - if (timedout) - die("BIOS PCU Misc Config Write timed out.\n"); - } - - /* update RST_CPL3, PCODE_INIT_DONE3 */ - timedout = set_bios_reset_cpl_for_package(socket, RST_CPL3_MASK, - PCODE_INIT_DONE3_MASK, RST_CPL3_MASK); - if (timedout) - die("BIOS RESET CPL3 timed out.\n"); - - /* update RST_CPL4, PCODE_INIT_DONE4 */ - timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK, - PCODE_INIT_DONE4_MASK, RST_CPL4_MASK); - if (timedout) - die("BIOS RESET CPL4 timed out.\n"); - /* set CSR_DESIRED_CORES_CFG2 lock bit */ - data = pci_mmio_read_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG); - data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK; - printk(BIOS_SPEW, "%s - pci_mmio_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n", - __func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data); - pci_mmio_write_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, data); -} - -void set_bios_init_completion(void) -{ - uint32_t sbsp_socket_id = 0; /* TODO - this needs to be configurable */ - - for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) { - if (socket == sbsp_socket_id) - continue; - set_bios_init_completion_for_package(socket); - } - set_bios_init_completion_for_package(sbsp_socket_id); -} - void config_reset_cpl3_csrs(void) { uint32_t data, plat_info, max_min_turbo_limit_ratio; diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 75f8a8a10a..310421566c 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -3,12 +3,15 @@ #include #include #include +#include #include #include #include #include #include +#include #include +#include void get_stack_busnos(uint32_t *bus) { @@ -224,4 +227,130 @@ void xeonsp_init_cpu_config(void) ++num_apics; } } + +/* return true if command timed out else false */ +static bool wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask, + uint32_t target) +{ + const uint32_t max_delay = 5000; /* 5 seconds max */ + const uint32_t step_delay = 50; /* 50 us */ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, max_delay); + while ((pci_s_read_config32(dev, reg) & mask) != target) { + udelay(step_delay); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "%s timed out for dev: %x, reg: 0x%x, " + "mask: 0x%x, target: 0x%x\n", __func__, dev, reg, mask, target); + return true; /* timedout */ + } + } + return false; /* successful */ +} + +/* return true if command timed out else false */ +static bool write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data) +{ + /* verify bios is not in busy state */ + if (wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0)) + return true; /* timed out */ + + /* write data to data register */ + printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%x\n", __func__, + PCU_CR1_BIOS_MB_DATA_REG, data); + pci_s_write_config32(dev, PCU_CR1_BIOS_MB_DATA_REG, data); + + /* write the command */ + printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%lx\n", __func__, + PCU_CR1_BIOS_MB_INTERFACE_REG, command | BIOS_MB_RUN_BUSY_MASK); + pci_s_write_config32(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, + command | BIOS_MB_RUN_BUSY_MASK); + + /* wait for completion or time out*/ + return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, + BIOS_MB_RUN_BUSY_MASK, 0); +} + +/* return true if command timed out else false */ +static bool set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask, + uint32_t pcode_init_mask, uint32_t val) +{ + const uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + + uint32_t reg = pci_s_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG); + reg &= (uint32_t) ~rst_cpl_mask; + reg |= val; + + /* update BIOS RESET completion bit */ + pci_s_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg); + + /* wait for PCU ack */ + return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask, + pcode_init_mask); +} + +static void set_bios_init_completion_for_package(uint32_t socket) +{ + uint32_t data; + bool timedout; + const uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + + /* read PCU config */ + timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); + if (timedout) { + /* 2nd try */ + timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); + if (timedout) + die("BIOS PCU Misc Config Read timed out.\n"); + + /* Since the 1st try failed, we need to make sure PCU is in stable state */ + data = pci_s_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG); + printk(BIOS_SPEW, "%s - pci_s_read_config32 reg: 0x%x, data: 0x%x\n", + __func__, PCU_CR1_BIOS_MB_DATA_REG, data); + timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data); + if (timedout) + die("BIOS PCU Misc Config Write timed out.\n"); + } + + /* update RST_CPL3, PCODE_INIT_DONE3 */ + timedout = set_bios_reset_cpl_for_package(socket, RST_CPL3_MASK, + PCODE_INIT_DONE3_MASK, RST_CPL3_MASK); + if (timedout) + die("BIOS RESET CPL3 timed out.\n"); + + /* update RST_CPL4, PCODE_INIT_DONE4 */ + timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK, + PCODE_INIT_DONE4_MASK, RST_CPL4_MASK); + if (timedout) + die("BIOS RESET CPL4 timed out.\n"); + + /* set CSR_DESIRED_CORES_CFG2 lock bit */ + data = pci_s_read_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG); + data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK; + printk(BIOS_SPEW, "%s - pci_s_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n", + __func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data); + pci_s_write_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, data); +} + +void set_bios_init_completion(void) +{ + /* FIXME: This may need to be changed for multi-socket platforms */ + uint32_t sbsp_socket_id = 0; + + /* + * According to the BIOS Writer's Guide, the SBSP must be the last socket + * to receive the BIOS init completion message. So, we send it to all non-SBSP + * sockets first. + */ + for (uint32_t socket = 0; socket < soc_get_num_cpus(); ++socket) { + if (socket == sbsp_socket_id) + continue; + set_bios_init_completion_for_package(socket); + } + + /* And finally, take care of the SBSP */ + set_bios_init_completion_for_package(sbsp_socket_id); +} #endif From 662ac546fc386c10d6302f404c77ac7f01f31628 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 2 Nov 2020 21:26:41 -0700 Subject: [PATCH 159/262] soc/intel/xeon_sp: Don't add memory resource twice The resource function is called for each device VID/DID. Only add the memory resource map from the boot CPU (bus 0) and not for each socket/CPU. This is a NUMA architecture and has a shared memory map. All the resources must match across the sockets/CPUs, so they should only be added to the map once. Change-Id: Ia336f604441ae8d30b8418300da7c34ab9907cae Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/47173 Tested-by: build bot (Jenkins) Reviewed-by: Jay Talbott Reviewed-by: Arthur Heymans --- src/soc/intel/xeon_sp/uncore.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 332b9a44a3..15a9f0ff17 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -155,6 +155,10 @@ static void mc_add_dram_resources(struct device *dev, int *res_count) struct resource *resource; int index = *res_count; + /* Only add dram resources once. */ + if (dev->bus->secondary != 0) + return; + fsp_find_reserved_memory(&fsp_mem); /* Read in the MAP registers and report their values. */ From a9a5dda093ea10b81bfd618912c74bb1842106d8 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Fri, 6 Nov 2020 14:09:01 +0530 Subject: [PATCH 160/262] mb/intel/adlrvp: Add PMC.MUX.CONx device configuration for adlrvp This patch adds the PMC MUX and CONx devices for adlrvp. Device specific method contains the port and orientation details used to configure the mux. BUG=b:170607415 TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects in SSDT tables. Change-Id: I3b5bb73991feb99577c16fea00c381dd0f855769 Signed-off-by: V Sowmya Reviewed-on: https://review.coreboot.org/c/coreboot/+/47289 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/intel/adlrvp/Kconfig | 1 + .../variants/adlrvp_p_ext_ec/overridetree.cb | 32 ++++++++++++++++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index a41c18659d..57b0524ce3 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_INTEL_PMC if BOARD_INTEL_ADLRVP_P_EXT_EC select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI select SOC_INTEL_ALDERLAKE diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb index e58e9fbdce..8033d3d1d3 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb @@ -1,4 +1,34 @@ chip soc/intel/alderlake - device domain 0 on end + device domain 0 on + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + end + end # eSPI + device pci 1f.2 hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "1" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "2" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end # PMC + end end From 06bff726d43b1ec46fcfe28797d8ef7f748ea9e8 Mon Sep 17 00:00:00 2001 From: Matt Ziegelbaum Date: Fri, 6 Nov 2020 21:42:10 -0500 Subject: [PATCH 161/262] hatch: Create genesis variant Create the genesis variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:172620124 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_GENESIS Signed-off-by: Matt Ziegelbaum Change-Id: I70886c2c5a25f5de1a4941ff235547ee812fa50d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47334 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/mainboard/google/hatch/Kconfig | 2 + src/mainboard/google/hatch/Kconfig.name | 4 + .../hatch/variants/genesis/Makefile.inc | 4 + .../google/hatch/variants/genesis/gpio.c | 115 +++++ .../variants/genesis/include/variant/ec.h | 8 + .../variants/genesis/include/variant/gpio.h | 8 + .../hatch/variants/genesis/overridetree.cb | 480 ++++++++++++++++++ 7 files changed, 621 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/genesis/Makefile.inc create mode 100644 src/mainboard/google/hatch/variants/genesis/gpio.c create mode 100644 src/mainboard/google/hatch/variants/genesis/include/variant/ec.h create mode 100644 src/mainboard/google/hatch/variants/genesis/include/variant/gpio.h create mode 100644 src/mainboard/google/hatch/variants/genesis/overridetree.cb diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index afc9de0192..1e132ed0fd 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -144,6 +144,7 @@ config MAINBOARD_PART_NUMBER default "Wyvern" if BOARD_GOOGLE_WYVERN default "Dooly" if BOARD_GOOGLE_DOOLY default "Ambassador" if BOARD_GOOGLE_AMBASSADOR + default "Genesis" if BOARD_GOOGLE_GENESIS config OVERRIDE_DEVICETREE string @@ -178,6 +179,7 @@ config VARIANT_DIR default "wyvern" if BOARD_GOOGLE_WYVERN default "dooly" if BOARD_GOOGLE_DOOLY default "ambassador" if BOARD_GOOGLE_AMBASSADOR + default "genesis" if BOARD_GOOGLE_GENESIS config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 71166d0bcf..7853c2ec31 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -101,3 +101,7 @@ config BOARD_GOOGLE_DOOLY config BOARD_GOOGLE_AMBASSADOR bool "-> Ambassador" select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_GENESIS + bool "-> Genesis" + select BOARD_GOOGLE_BASEBOARD_PUFF diff --git a/src/mainboard/google/hatch/variants/genesis/Makefile.inc b/src/mainboard/google/hatch/variants/genesis/Makefile.inc new file mode 100644 index 0000000000..3b5b7d000d --- /dev/null +++ b/src/mainboard/google/hatch/variants/genesis/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/genesis/gpio.c b/src/mainboard/google/hatch/variants/genesis/gpio.c new file mode 100644 index 0000000000..5a911fc4f9 --- /dev/null +++ b/src/mainboard/google/hatch/variants/genesis/gpio.c @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A16 : SD_OC_ODL */ + PAD_CFG_GPI(GPP_A16, NONE, DEEP), + /* A18 : LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A23 : M2_WLAN_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* B5 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + + /* C0 : SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C6: M2_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), + /* C7 : LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), + /* C10 : PCH_PCON_RST_ODL */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : PCH_PCON_PDB_ODL */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C15 : WLAN_OFF_L */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + + /* E2 : EN_PP_MST_OD */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + /* E9 : USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + + /* F11 : EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* H4: PCH_I2C_PCON_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5: PCH_I2C_PCON_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H22 : PWM_PP3300_BIOZZER */ + PAD_CFG_GPO(GPP_H22, 0, DEEP), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/genesis/include/variant/ec.h b/src/mainboard/google/hatch/variants/genesis/include/variant/ec.h new file mode 100644 index 0000000000..59fb3783c5 --- /dev/null +++ b/src/mainboard/google/hatch/variants/genesis/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/genesis/include/variant/gpio.h b/src/mainboard/google/hatch/variants/genesis/include/variant/gpio.h new file mode 100644 index 0000000000..79a141008f --- /dev/null +++ b/src/mainboard/google/hatch/variants/genesis/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/genesis/overridetree.cb b/src/mainboard/google/hatch/variants/genesis/overridetree.cb new file mode 100644 index 0000000000..adb00e485f --- /dev/null +++ b/src/mainboard/google/hatch/variants/genesis/overridetree.cb @@ -0,0 +1,480 @@ +chip soc/intel/cannonlake + # Enable heci communication + register "HeciEnabled" = "1" + + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # USB configuration + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 3 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 4 + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A port 0 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + + # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkDmic0" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + }" + + # PCIe port 7 for LAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "6" + register "PcieClkSrcClkReq[0]" = "0" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # SATA port 1 Gen3 Strength + # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB + register "sata_port[1].TxGen3DeEmphEnable" = "1" + register "sata_port[1].TxGen3DeEmph" = "0x20" + + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 85), + TEMP_PCT(85, 75), + TEMP_PCT(80, 65), + TEMP_PCT(75, 55), + TEMP_PCT(70, 45),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(50, 85), + TEMP_PCT(47, 75), + TEMP_PCT(45, 65), + TEMP_PCT(42, 55), + TEMP_PCT(39, 45),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Middle"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Left"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Middle"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""1AF80175"" + register "name" = ""PS17"" + register "desc" = ""Parade PS175"" + device i2c 4a on end + end + end # I2C #2, PCON PS175. + device pci 15.3 on + chip drivers/i2c/generic + register "hid" = ""10EC2142"" + register "name" = ""RTD2"" + register "desc" = ""Realtek RTD2142"" + device i2c 4a on end + end + end # I2C #3, Realtek RTD2142. + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1c.6 on + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW1_07" # GPP_C7 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "device_index" = "0" + device pci 00.0 on end + end + end # RTL8111H Ethernet NIC + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1e.3 off end # GSPI #1 + end + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 1004, + .dc_loadline = 1004, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 181, + .dc_loadline = 181, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + +end From c046dd02322dfed1db0c25ae310ec59630d8b492 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Fri, 30 Oct 2020 11:45:24 +0530 Subject: [PATCH 162/262] mb/intel/adlrvp: Replace if-else-if ladder with switch construct The patch replaces if-else-if ladder with switch case for readability purpose. Signed-off-by: Sridhar Siricilla Change-Id: I268db8bc63aaf64d4a91c9a44ef5282154b20a53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47054 Reviewed-by: Subrata Banik Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/intel/adlrvp/memory.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index d51caf783a..cab4ef93f3 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -72,12 +72,16 @@ const struct mb_cfg *variant_memory_params(void) { int board_id = get_board_id(); - if (board_id == ADL_P_LP4_1 || board_id == ADL_P_LP4_2) + switch (board_id) { + case ADL_P_LP4_1: + case ADL_P_LP4_2: return &lpddr4_mem_config; - else if (board_id == ADL_P_DDR4_1 || board_id == ADL_P_DDR4_2) + case ADL_P_DDR4_1: + case ADL_P_DDR4_2: return &ddr4_mem_config; - else if (board_id == ADL_P_DDR5) + case ADL_P_DDR5: return &ddr5_mem_config; - - die("unsupported board id : 0x%x\n", board_id); + default: + die("unsupported board id : 0x%x\n", board_id); + } } From 4067fa3512cc50af8bad20df63d6832176dd78e2 Mon Sep 17 00:00:00 2001 From: Jingle Hsu Date: Tue, 3 Nov 2020 20:46:41 +0800 Subject: [PATCH 163/262] util/inteltool: Add support for Intel Lewisburg SKU C621A Add support for dumping GPIOs on Intel Lewisburg SKU C621A. Tested=On OCP Delta Lake DVT, verify it executes successfully. Change-Id: I58797914aa5816aedace094c179e832150ad5e2e Signed-off-by: Jingle Hsu Reviewed-on: https://review.coreboot.org/c/coreboot/+/47163 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/inteltool/inteltool.c | 1 + util/inteltool/pcr.c | 1 + 2 files changed, 2 insertions(+) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 3fb7707a2a..5ecd8cacb8 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -277,6 +277,7 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM175, "QM175" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM238, "CM238" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C621, "C621" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C621A, "C621A" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C622, "C622" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C624, "C624" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C625, "C625" }, diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index bc78c336a5..307dc155c0 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -92,6 +92,7 @@ void pcr_init(struct pci_dev *const sb) case PCI_DEVICE_ID_INTEL_QM175: case PCI_DEVICE_ID_INTEL_CM238: case PCI_DEVICE_ID_INTEL_C621: + case PCI_DEVICE_ID_INTEL_C621A: case PCI_DEVICE_ID_INTEL_C622: case PCI_DEVICE_ID_INTEL_C624: case PCI_DEVICE_ID_INTEL_C625: From a69d2c10a906d18c9ce531c139fe6c8e37820c89 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 10 Aug 2020 15:33:04 +0200 Subject: [PATCH 164/262] cpu/x86/smm/smihandler.c: Simplify smm revision handling The ASEG smihandler bails out if an unsupported SMM save state revision is detected. Now we have code to find the SMM save state depending on the SMM save state revision so reuse this to do the same. This also increases the loglevel when bailing out of SMM due to unsupported SMM save state revision from BIOS_DEBUG to BIOS_WARNING, given that the system likely still boots but won't have a functioning smihandler. Change-Id: I57198f0c85c0f7a1fa363d3bd236c3d41b68d2f0 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/45471 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/cpu/x86/smm/smihandler.c | 54 +++--------------------------------- 1 file changed, 4 insertions(+), 50 deletions(-) diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 077fa8db8f..0d9131e429 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -14,23 +14,6 @@ #include #endif -typedef enum { - AMD64, - EM64T100, - EM64T101, - LEGACY -} save_state_type_t; - -typedef struct { - save_state_type_t type; - union { - amd64_smm_state_save_area_t *amd64_state_save; - em64t100_smm_state_save_area_t *em64t100_state_save; - em64t101_smm_state_save_area_t *em64t101_state_save; - legacy_smm_state_save_area_t *legacy_state_save; - }; -} smm_state_save_area_t; - static int do_driver_init = 1; typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; @@ -162,9 +145,6 @@ bool smm_region_overlaps_handler(const struct region *r) void smi_handler(void) { unsigned int node; - const uint32_t smm_rev = smm_revision(); - smm_state_save_area_t state_save; - u32 smm_base = SMM_BASE; /* ASEG */ /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { @@ -190,36 +170,10 @@ void smi_handler(void) printk(BIOS_SPEW, "\nSMI# #%d\n", node); - switch (smm_rev) { - case 0x00030002: - case 0x00030007: - state_save.type = LEGACY; - state_save.legacy_state_save = - smm_save_state(smm_base, - SMM_LEGACY_ARCH_OFFSET, node); - break; - case 0x00030100: - state_save.type = EM64T100; - state_save.em64t100_state_save = - smm_save_state(smm_base, - SMM_EM64T100_ARCH_OFFSET, node); - break; - case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ - state_save.type = EM64T101; - state_save.em64t101_state_save = - smm_save_state(smm_base, - SMM_EM64T101_ARCH_OFFSET, node); - break; - case 0x00020064: - case 0x00030064: - state_save.type = AMD64; - state_save.amd64_state_save = - smm_save_state(smm_base, - SMM_AMD64_ARCH_OFFSET, node); - break; - default: - printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_rev); - printk(BIOS_DEBUG, "SMI# not supported on your CPU\n"); + /* Use smm_get_save_state() to see if the smm revision is supported */ + if (smm_get_save_state(node) == NULL) { + printk(BIOS_WARNING, "smm_revision: 0x%08x\n", smm_revision()); + printk(BIOS_WARNING, "SMI# not supported on your CPU\n"); /* Don't release lock, so no further SMI will happen, * if we don't handle it anyways. */ From 7ac4722a35714bb02286a0ae0b47abaf1a35219d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 9 Aug 2020 20:21:28 +0200 Subject: [PATCH 165/262] cpu/x86/smm/smm.ld: Assert that CONFIG_MAX_CPUS <= 4 The SMM_ASEG code only supports up to 4 CPUs, so assert this at buildtime. Change-Id: I8ec803cd1b76f17f4dccd5c573179d542d54c277 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/44322 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/cpu/x86/smm/smm.ld | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld index af5968d9d5..e232028e4b 100644 --- a/src/cpu/x86/smm/smm.ld +++ b/src/cpu/x86/smm/smm.ld @@ -2,6 +2,9 @@ /* Maximum number of CPUs/cores */ CPUS = 4; + +_ = ASSERT(CPUS >= CONFIG_MAX_CPUS, "The ASEG SMM code only supports up to 4 CPUS"); + ENTRY(smm_handler_start); SECTIONS From 3967cf931b02414d4b420dcb43b4aeb5ce7d2430 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 9 Aug 2020 21:33:19 +0200 Subject: [PATCH 166/262] cpu/x86/smm: Add a common save state handling Currently coreboot has limited use for the SMM save state. Typically the only thing needed is to get or set a few registers and to know which CPU triggered the SMI (typically via an IO write). Abstracting away different SMM save states would allow to put some SMM functionality like the SMMSTORE entry in common places. To save place platforms can select different SMM save sate ops that should be implemented. For instance AMD platforms don't need Intel SMM save state handling. Some platforms can encounter CPUs with different save states, which the code then handles at runtime by comparing the SMM save state revision which is located at the same offset for all SMM save state types. Change-Id: I4a31d05c09065543424a9010ac434dde0dfb5836 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/44323 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/x86/smm/Makefile.inc | 2 + src/cpu/x86/smm/save_state.c | 77 ++++++++++++++++++++++++++++++++ src/include/cpu/x86/save_state.h | 34 ++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 src/cpu/x86/smm/save_state.c create mode 100644 src/include/cpu/x86/save_state.h diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index c2f49cf94d..eb386a69e5 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -32,6 +32,8 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual endif +smm-y += save_state.c + ifeq ($(CONFIG_SMM_TSEG),y) ramstage-y += tseg_region.c diff --git a/src/cpu/x86/smm/save_state.c b/src/cpu/x86/smm/save_state.c new file mode 100644 index 0000000000..bb08f86414 --- /dev/null +++ b/src/cpu/x86/smm/save_state.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* These are weakly linked such that platforms can link only the save state + ops they actually require. */ +const struct smm_save_state_ops *legacy_ops __weak = NULL; +const struct smm_save_state_ops *em64t100_ops __weak = NULL; +const struct smm_save_state_ops *em64t101_ops __weak = NULL; +const struct smm_save_state_ops *amd64_ops __weak = NULL; + +static const struct smm_save_state_ops *save_state; + +/* Returns -1 on failure, 0 on success */ +static int init_save_state(void) +{ + const uint32_t revision = smm_revision(); + int i; + static bool initialized = false; + const struct smm_save_state_ops *save_state_ops[] = { + legacy_ops, + em64t100_ops, + em64t101_ops, + amd64_ops, + }; + + if (initialized) + return 0; + + for (i = 0; i < ARRAY_SIZE(save_state_ops); i++) { + const struct smm_save_state_ops *ops = save_state_ops[i]; + const uint32_t *rev; + + if (ops == NULL) + continue; + + for (rev = ops->revision_table; *rev != SMM_REV_INVALID; rev++) + if (*rev == revision) { + save_state = ops; + initialized = true; + return 0; + } + } + + return -1; +} + +int get_apmc_node(u8 cmd) +{ + if (init_save_state()) + return -1; + + return save_state->apmc_node(cmd); +} + +int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length) +{ + if (init_save_state()) + return -1; + + if (node > CONFIG_MAX_CPUS) + return -1; + + return save_state->get_reg(reg, node, out, length); +} + +int set_save_state_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length) +{ + if (init_save_state()) + return -1; + + if (node > CONFIG_MAX_CPUS) + return -1; + + return save_state->set_reg(reg, node, in, length); +} diff --git a/src/include/cpu/x86/save_state.h b/src/include/cpu/x86/save_state.h new file mode 100644 index 0000000000..d6fcf63d79 --- /dev/null +++ b/src/include/cpu/x86/save_state.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __CPU_X86_SAVE_STATE_H__ +#define __CPU_X86_SAVE_STATE_H__ + +#include + +enum cpu_reg { + RAX, + RBX, + RCX, + RDX +}; + +#define SMM_REV_INVALID 0xffffffff + +struct smm_save_state_ops { + const uint32_t *revision_table; + /* Accessors for CPU registers in the SMM save state + Returns -1 on failure, 0 on success */ + int (*get_reg)(const enum cpu_reg reg, const int node, void *out, const uint8_t length); + int (*set_reg)(const enum cpu_reg reg, const int node, void *in, const uint8_t length); + /* Returns -1 on failure, the node on which the 'cmd' was send on success */ + int (*apmc_node)(u8 cmd); +}; + +/* Return -1 on failure, otherwise returns which CPU node issued an APMC IO write */ +int get_apmc_node(u8 cmd); +/* Return -1 on failure, 0 on succes. + Accessors for the SMM save state CPU registers RAX, RBX, RCX and RDX */ +int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length); +int set_save_state_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length); + +#endif /* __CPU_X86_SAVE_STATE_H__ */ From 342802726739e95105a4a9e9425b34f03ac89db4 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 29 Sep 2020 11:51:34 +0200 Subject: [PATCH 167/262] soc/amd/*/smi.h: Move the pm_acpi_smi_cmd_port function declaration This prototype will be used outside of soc/amd. Change-Id: Icc69cf8a910764b27edf64f0f527b8f6a9013121 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/45813 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/include/cpu/x86/smm.h | 3 +++ src/soc/amd/picasso/include/soc/smi.h | 1 - src/soc/amd/picasso/smi_util.c | 1 + src/soc/amd/stoneyridge/include/soc/smi.h | 1 - src/soc/amd/stoneyridge/smi_util.c | 1 + 5 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 1073d03e49..6cf6f8290e 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -197,5 +197,8 @@ void smm_list_regions(void); /* Return the SMM save state revision. The revision can be fetched from the smm savestate which is always at the same offset downward from the top of the save state. */ uint32_t smm_revision(void); +/* Returns the PM ACPI SMI port. On Intel systems this typically not configurable (APM_CNT, 0xb2). + On AMD systems it is sometimes configurable. */ +uint16_t pm_acpi_smi_cmd_port(void); #endif /* CPU_X86_SMM_H */ diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index 0529ef6877..6413c6a06d 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -214,7 +214,6 @@ struct sci_source { uint8_t level; /* Edge or Level, smi_sci_dir */ }; -uint16_t pm_acpi_smi_cmd_port(void); void configure_smi(uint8_t smi_num, uint8_t mode); void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void configure_scimap(const struct sci_source *sci); diff --git a/src/soc/amd/picasso/smi_util.c b/src/soc/amd/picasso/smi_util.c index 2c5085b5e9..2fbc8e2d6a 100644 --- a/src/soc/amd/picasso/smi_util.c +++ b/src/soc/amd/picasso/smi_util.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index f7cacea37f..15bba0fd9b 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -211,7 +211,6 @@ struct sci_source { uint8_t level; /* Edge or Level, smi_sci_dir */ }; -uint16_t pm_acpi_smi_cmd_port(void); void configure_smi(uint8_t smi_num, uint8_t mode); void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void configure_scimap(const struct sci_source *sci); diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 2c5085b5e9..2fbc8e2d6a 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include From 27ba085334d1482c08b5fd9e628a0f11a0fd9202 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 29 Sep 2020 11:52:57 +0200 Subject: [PATCH 168/262] mb/emulation/q35: Define pm_acpi_smi_cmd_port The X86 Qemu targets use the AMD64 SMM save state, but unlike most AMD CPU's the PM ACPI SMI port is not configurable and uses the Intel default APM_CNT, 0xb2 port. This will be used by the common save state handler. Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/45814 Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/emulation/qemu-q35/Makefile.inc | 2 ++ src/mainboard/emulation/qemu-q35/smi.c | 9 +++++++++ 2 files changed, 11 insertions(+) create mode 100644 src/mainboard/emulation/qemu-q35/smi.c diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index e142d4d5c1..ddcf6da062 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -14,3 +14,5 @@ ramstage-y += ../qemu-i440fx/northbridge.c verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smi.c diff --git a/src/mainboard/emulation/qemu-q35/smi.c b/src/mainboard/emulation/qemu-q35/smi.c new file mode 100644 index 0000000000..5d8d48295c --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/smi.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* The X86 qemu target uses AMD64 save states but the APM port is not configurable. */ +uint16_t pm_acpi_smi_cmd_port(void) +{ + return APM_CNT; +} From 58ce44720aac85381d2524ed520b71dce2c3f99c Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Fri, 6 Nov 2020 10:56:57 +0530 Subject: [PATCH 169/262] soc/intel/jasperlake: Enable Intel FIVR RFI settings We already have RFI UPD settings to mitigate RFI noise issues in platform. These UPDs were not getting filled via devicetree but needed to be filled from fsp_params.c Exporting these UPDs to chip.h will allow OEM/ODMs to fill it directly from devicetree and also allow us to control it based on boards instead of keeping it common across SoCs. BUG=b:171683785 BRANCH=None TEST=Compilation works and we're able to fill UPD from devicetree.Value gets reflected in FSP UPDs. Change-Id: I495cd2294368e6b3035c48b9556a83418d5632de Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/47286 Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/chip.h | 18 ++++++++++++++++++ src/soc/intel/jasperlake/fsp_params.c | 4 ++++ 2 files changed, 22 insertions(+) diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index f157f9218b..0ed42050e9 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -341,6 +341,24 @@ struct soc_intel_jasperlake_config { * - PM_CFG.SLP_LAN_MIN_ASST_WDTH */ uint8_t PchPmPwrCycDur; + + /* + * FIVR RFI Frequency + * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. + * 0: Auto. + * Range varies based on XTAL clock: + * 0-1918 (Up to 191.8HMz) for 24MHz clock; + * 0-1535 (Up to 153.5MHz) for 19MHz clock. + */ + uint16_t FivrRfiFrequency; + + /* + * FIVR RFI Spread Spectrum + * Set the Spread Spectrum Range. 0: 0%; + * FIVR RFI Spread Spectrum, in 0.1% increments. + * Range: 0.0% to 10.0% (0-100) + */ + uint8_t FivrSpreadSpectrum; }; typedef struct soc_intel_jasperlake_config config_t; diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index db27234067..92c35c62dc 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -216,6 +216,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Provide correct UART number for FSP debug logs */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + /* Configure FIVR RFI related settings */ + params->FivrRfiFrequency = config->FivrRfiFrequency; + params->FivrSpreadSpectrum = config->FivrSpreadSpectrum; + /* Apply minimum assertion width settings if non-zero */ if (config->PchPmSlpS3MinAssert) params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert; From 0d11dbfd6ad4d49b65b2104fa9de546938a3cb44 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sat, 31 Oct 2020 21:43:25 +0100 Subject: [PATCH 170/262] cpu/intel/model_206ax: Get CPU frequencies for SMBIOS type 4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Calculate the frequencies based on the appropriate MSRs and pass them to SMBIOS tables generator. Ivybridge microarchitecture does not yet implement CPUID 16H leaf used to obtain the required frequencies. TEST=Intel Core i7-3770, TianoCore UEFI payload displays the CPU frequency correctly equal 3.4GHz in Boot Manager Menu, dmidecode shows correct frequencies according to Intel ARK, 3.4GHz base and 3.9GHz turbo Signed-off-by: Michał Żygowski Change-Id: Iefbae6111d39107eacac7e61654311646c6981eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/47058 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/cpu/intel/model_206ax/model_206ax_init.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 7fb412c0ca..2afbfeecec 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -18,6 +18,7 @@ #include "chip.h" #include #include +#include /* * List of supported C-states in this processor @@ -360,6 +361,25 @@ static void set_max_ratio(void) ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); } +unsigned int smbios_cpu_get_max_speed_mhz(void) +{ + msr_t msr; + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + return (msr.lo & 0xff) * SANDYBRIDGE_BCLK; +} + +unsigned int smbios_cpu_get_current_speed_mhz(void) +{ + msr_t msr; + msr = rdmsr(MSR_PLATFORM_INFO); + return ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK; +} + +unsigned int smbios_processor_external_clock(void) +{ + return SANDYBRIDGE_BCLK; +} + static void configure_mca(void) { msr_t msr; From 4355a6715a92c2fdb83c251dde06f7ecce181c98 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 13 Oct 2020 10:37:02 +0200 Subject: [PATCH 171/262] soc/nvidia/tegra124/include/soc/clk_rst.h: Remove extra tab Change-Id: I0c606fd129c200446744f7a67ae63fec6d8e1684 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46328 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/nvidia/tegra124/include/soc/clk_rst.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/nvidia/tegra124/include/soc/clk_rst.h b/src/soc/nvidia/tegra124/include/soc/clk_rst.h index 0b0e025264..cfddd10dcf 100644 --- a/src/soc/nvidia/tegra124/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra124/include/soc/clk_rst.h @@ -257,7 +257,7 @@ struct __packed clk_rst_ctlr { u32 spare_reg0; /* _SPARE_REG0, 0x55c */ u32 _rsv32[4]; /* 0x560-0x56c */ u32 plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */ - u32 _rsv32_1[7]; /* 0x574-58c */ + u32 _rsv32_1[7]; /* 0x574-58c */ u32 plldp_base; /* _PLLDP_BASE, 0x590 */ u32 plldp_misc; /* _PLLDP_MISC, 0x594 */ u32 plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ From 136380fcac333ec28574f5bfb5b43b61a919130b Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Wed, 16 Sep 2020 22:47:57 +0800 Subject: [PATCH 172/262] Documentation: Introduce HP Sure Start and the method to bypass it Change-Id: Id198afdaa13b4c361e1b77a56d5a2436ed1c4c86 Signed-off-by: Iru Cai Reviewed-on: https://review.coreboot.org/c/coreboot/+/45577 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- Documentation/mainboard/hp/hp_sure_start.md | 60 +++++++++++++++++++++ Documentation/mainboard/index.md | 1 + 2 files changed, 61 insertions(+) create mode 100644 Documentation/mainboard/hp/hp_sure_start.md diff --git a/Documentation/mainboard/hp/hp_sure_start.md b/Documentation/mainboard/hp/hp_sure_start.md new file mode 100644 index 0000000000..a07d9d02c7 --- /dev/null +++ b/Documentation/mainboard/hp/hp_sure_start.md @@ -0,0 +1,60 @@ +# HP Sure Start + +According to the [HP Sure Start Technical Whitepaper], HP Sure Start is a chipset +and processor independent firmware intrusion detection and automatic repair system. +It is implemented in HP notebooks since 2013, and desktops since 2015. + +This document talks about some mechanism of HP Sure Start on some machines, and +the method to bypass it. + +## Laptops with SMSC MEC1322 embedded controller + +Haswell EliteBook, ZBook and ProBook 600 series use SMSC MEC1322 embedded controller. +The EC firmware implements HP Sure Start. + +A Haswell EliteBook has two flash chips. According to the strings in the EC firmware, +the 16MiB flash chip that stores the BIOS firmware is called the *system flash*, and +the 2MiB flash chip that stores part of the system flash content is called the +*private flash*. A Haswell ProBook 600 series laptop also uses MEC1322 and has similar +EC firmware, but the HP Sure Start functions are not enabled. + +The private flash is connected to the EC, and is not accessible by the OS. +It contains the following: + +- HP Sure Start policy header (starting with the string "POLI") +- A copy of the Intel Flash Descriptor +- A copy of the GbE firmware +- Machine Unique Data (MUD) +- Hashes of the IFD, GbE firmware and MUD, the hash algorithm is unknown +- A copy of the bootblock, UEFI PEI stage, and microcode + +If the IFD of the system flash does not match the hash in the private flash, for example, +modifying the IFD with ``ifdtool -u`` or ``me_cleaner -S``, the EC will recover the IFD. + +If the content of the private flash is lost, the EC firmware will still copy the IFD, +bootblock and PEI to the private flash. However, the IFD is not protected after that. + +HP Sure Start also verifies bootblock, PEI, and microcode without using the private flash. +EC firmware reads them from an absolute address of the system flash chip, which is +hardcoded in the EC firmware. It looks like this verification is done with a digital +signature. If the PEI volume is modified, EC firmware will recover it using the copy +in the private flash. If the private flash has no valid copies of the PEI volume, and +the PEI volume is modified, the machine will refuse to boot with the CapsLock LED blinking. + +## Bypassing HP Sure Start + +First search the mainboard for the flash chips. If there are two flash chips, +the smaller one may be the private flash. + +For Intel boards, try to modify the IFD with ``ifdtool -u``, power on and shut down +the machine, then read the flash again. If the IFD is not modified, it is likely to +be recovered from the private flash. Find the private flash and erase it, then the IFD +can be modified. + +To bypass the bootblock and PEI verification, we can modify the IFD to make the +BIOS region not overlap with the protected region. Since the EC firmware is usually +located at the high address of the flash chip (and in the protected region), +we can leave it untouched, and do not need to extract the EC firmware to put it in +the coreboot image. + +[HP Sure Start Technical Whitepaper]: http://h10032.www1.hp.com/ctg/Manual/c05163901 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 998de613c0..60fb89949a 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -61,6 +61,7 @@ The boards in this section are not real mainboards, but emulators. ### EliteBook series - [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md) +- [HP Sure Start](hp/hp_sure_start.md) - [EliteBook 2560p](hp/2560p.md) - [EliteBook 8760w](hp/8760w.md) From ac6565279ce30e2eed8e5fcc14f687013717c82f Mon Sep 17 00:00:00 2001 From: Benjamin Doron Date: Thu, 5 Nov 2020 22:20:52 +0000 Subject: [PATCH 173/262] soc/intel/skylake: Enable PCH thermal depending on devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hook up PCH thermal subsystem configuration to devicetree. Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Signed-off-by: Benjamin Doron Reviewed-on: https://review.coreboot.org/c/coreboot/+/47116 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Michael Niewöhner --- src/mainboard/protectli/vault_kbl/ramstage.c | 1 - src/soc/intel/skylake/chip.c | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/protectli/vault_kbl/ramstage.c b/src/mainboard/protectli/vault_kbl/ramstage.c index 962702fb5a..9518b1d721 100644 --- a/src/mainboard/protectli/vault_kbl/ramstage.c +++ b/src/mainboard/protectli/vault_kbl/ramstage.c @@ -13,7 +13,6 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->TurboMode = 1; - params->PchThermalDeviceEnable = 0; params->PchPort61hEnable = 1; params->CdClock = 3; } diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 89eaef5b56..1e13428252 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -295,6 +295,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) dev = pcidev_path_on_root(SA_DEVFN_TS); params->Device4Enable = dev && dev->enabled; + dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); + params->PchThermalDeviceEnable = dev && dev->enabled; params->EnableTcoTimer = !config->PmTimerDisabled; tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; From 2e7317568a26e0dd985672e83e5ffdc339b7a278 Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Thu, 5 Nov 2020 16:53:56 +0800 Subject: [PATCH 174/262] mb/google/puff/var/dooly: Add WEIDA touchscreen device Adds ACPI properties for WDT8762A device. Per spec v0.8 HID name WDHT2002 T14=100ms BUG=b:163561649 BRANCH=puff TEST=emerge-puff coreboot and check system dmesg and evtest can get device. Change-Id: I178e9d5aa1e1501d33b3cd4092f3f522bb6f1a74 Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/47280 Tested-by: build bot (Jenkins) Reviewed-by: Sam McNally Reviewed-by: Edward O'Callaghan --- .../google/hatch/variants/dooly/overridetree.cb | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index f4b6d63897..8ced613fde 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -311,7 +311,20 @@ chip soc/intel/cannonlake end # I2C #0 ALC1015 device pci 15.1 off end # I2C #1 device pci 15.2 on end # I2C #2 LVDS - device pci 15.3 on end # I2C #3 Touchscreen + device pci 15.3 on + chip drivers/i2c/hid + register "generic.hid" = ""WDHT2002"" + register "generic.desc" = ""WDT Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A20_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "100" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end # I2C #3 Touchscreen device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic From 43cc3c0273a165da17c50dad68c009ea557c9462 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 9 Nov 2020 08:07:10 -0800 Subject: [PATCH 175/262] drivers/wifi: Check device is of type PCI before checking vendor ID CB:46865 ("mb, soc/intel: Reorganize CNVi device entries in devicetree") reorganized the devicetree entries to make the representation of CNVi device consistent with other internal PCI devices. Since a dummy generic device is added for the CNVi device, `emit_sar_acpi_structures()` needs to first check if the device is PCI before checking the vendor ID. This ensures that SAR table generation is skipped only for PCIe devices with non-Intel vendor IDs and not for the dummy generic device. BUG=b:165105210 Change-Id: I3c8d18538b94ed1072cfcc108552f3a1ac320395 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/47364 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Duncan Laurie Reviewed-by: Dtrain Hsu --- src/drivers/wifi/generic/acpi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 1cc4bd080f..cd5af4ecfa 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -44,8 +44,11 @@ static void emit_sar_acpi_structures(const struct device *dev) struct wifi_sar_limits sar_limits; struct wifi_sar_delta_table *wgds; - /* CBFS SAR and SAR ACPI tables are currently used only by Intel WiFi devices. */ - if (dev->vendor != PCI_VENDOR_ID_INTEL) + /* + * If device type is PCI, ensure that the device has Intel vendor ID. CBFS SAR and SAR + * ACPI tables are currently used only by Intel WiFi devices. + */ + if (dev->path.type == DEVICE_PATH_PCI && dev->vendor != PCI_VENDOR_ID_INTEL) return; /* Retrieve the sar limits data */ From 85d0e7611a5cf9dcbf7d82deb54cc7e1e6fc79e8 Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Tue, 8 Sep 2020 19:50:55 +0800 Subject: [PATCH 176/262] mb/hp: Add HP EliteBook Folio 9480m The code is based on autoport, with necessary modifications. This laptop uses SMSC MEC1322 embedded controller, but the EC interface is the same as the EliteBook laptops of previous generations that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need EC firmware inserted into CBFS. We also need to leave the end of the OEM flash content untouched, so the default ROM size is set to 12MiB instead of 16MiB, and we need to modify the IFD when flashing. Thanks to persmule for providing the laptop and pointing out how to program the system flash chip of it. Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae Signed-off-by: Iru Cai Reviewed-on: https://review.coreboot.org/c/coreboot/+/45578 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- Documentation/mainboard/hp/folio_9480m.md | 156 ++++++++++++++++++ .../mainboard/hp/folio_9480m_flash.webp | Bin 0 -> 40170 bytes Documentation/mainboard/index.md | 1 + src/mainboard/hp/folio_9480m/Kconfig | 50 ++++++ src/mainboard/hp/folio_9480m/Kconfig.name | 2 + src/mainboard/hp/folio_9480m/Makefile.inc | 2 + src/mainboard/hp/folio_9480m/acpi/ec.asl | 3 + .../hp/folio_9480m/acpi/platform.asl | 14 ++ src/mainboard/hp/folio_9480m/acpi/superio.asl | 3 + src/mainboard/hp/folio_9480m/acpi_tables.c | 14 ++ src/mainboard/hp/folio_9480m/board_info.txt | 7 + src/mainboard/hp/folio_9480m/data.vbt | Bin 0 -> 4608 bytes src/mainboard/hp/folio_9480m/devicetree.cb | 88 ++++++++++ src/mainboard/hp/folio_9480m/dsdt.asl | 27 +++ .../hp/folio_9480m/gma-mainboard.ads | 18 ++ src/mainboard/hp/folio_9480m/gpio.c | 108 ++++++++++++ src/mainboard/hp/folio_9480m/hda_verb.c | 72 ++++++++ src/mainboard/hp/folio_9480m/romstage.c | 47 ++++++ 18 files changed, 612 insertions(+) create mode 100644 Documentation/mainboard/hp/folio_9480m.md create mode 100644 Documentation/mainboard/hp/folio_9480m_flash.webp create mode 100644 src/mainboard/hp/folio_9480m/Kconfig create mode 100644 src/mainboard/hp/folio_9480m/Kconfig.name create mode 100644 src/mainboard/hp/folio_9480m/Makefile.inc create mode 100644 src/mainboard/hp/folio_9480m/acpi/ec.asl create mode 100644 src/mainboard/hp/folio_9480m/acpi/platform.asl create mode 100644 src/mainboard/hp/folio_9480m/acpi/superio.asl create mode 100644 src/mainboard/hp/folio_9480m/acpi_tables.c create mode 100644 src/mainboard/hp/folio_9480m/board_info.txt create mode 100644 src/mainboard/hp/folio_9480m/data.vbt create mode 100644 src/mainboard/hp/folio_9480m/devicetree.cb create mode 100644 src/mainboard/hp/folio_9480m/dsdt.asl create mode 100644 src/mainboard/hp/folio_9480m/gma-mainboard.ads create mode 100644 src/mainboard/hp/folio_9480m/gpio.c create mode 100644 src/mainboard/hp/folio_9480m/hda_verb.c create mode 100644 src/mainboard/hp/folio_9480m/romstage.c diff --git a/Documentation/mainboard/hp/folio_9480m.md b/Documentation/mainboard/hp/folio_9480m.md new file mode 100644 index 0000000000..20eed08a66 --- /dev/null +++ b/Documentation/mainboard/hp/folio_9480m.md @@ -0,0 +1,156 @@ +# HP EliteBook Folio 9480m + +This page is about the notebook [HP EliteBook Folio 9480m]. + +## Release status + +HP EliteBook Folio 9480m was released in 2014 and is now end of life. +It can be bought from a secondhand market like Taobao or eBay. + +## Required proprietary blobs + +The following blobs are required to operate the hardware: + +1. EC firmware +2. Intel ME firmware +3. mrc.bin + +HP EliteBook Folio 9480m uses SMSC MEC1322 as its embedded controller. +The EC firmware is stored in the flash chip, but we don't need to touch it +or use it in the coreboot build process. + +Intel ME firmware is in the flash chip. It is not needed when building coreboot. + +The Haswell memory reference code binary is needed when building coreboot. +Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin). + +## Programming + +Before flashing, remove the battery and the hard drive cover according to the +[Maintenance and Service Guide] of this laptop. + +![Two flash chips of HP EliteBook Folio 9480m](folio_9480m_flash.webp) + +HP EliteBook Folio 9480m has two flash chips, a 16MiB system flash, and a 2MiB +private flash. To install coreboot, we need to program both flash chips. +Read [HP Sure Start] for detailed information. + +To access the system flash, we need to connect the AC adapter to the machine, +then clip on the flash chip with an SOIC-8 clip. An [STM32-based flash programmer] +made with an STM32 development board is tested to work. + +To access the private flash chip, we can use a ch341a based flash programmer and +flash the chip with the AC adapter disconnected. + +Before flashing coreboot, we need to do the following: + +1. Erase the private flash to disable the IFD protection +2. Modify the IFD to shrink the BIOS region, so that we'll not use or override + the protected bootblock and PEI region, as well as the EC firmware + +To erase the private flash chip, attach it with the flash programmer via the SOIC-8 clip, +then run: + + flashrom -p --erase + +To modify the IFD, we need a new flash layout. The flash layout of the OEM firmware is: + + 00000000:00000fff fd + 00001000:00002fff gbe + 00003000:005fffff me + 00600000:00ffffff bios + +The default coreboot configuration sets the flash chip size to 12MiB, so set the end of the +BIOS region to 0xbfffff in the new layout. The modified IFD is as follows (Platform Data +region pd is the region protected by HP Sure Start): + + 00000000:00000fff fd + 00001000:00002fff gbe + 00003000:005fffff me + 00600000:00bfffff bios + 00eb5000:00ffffff pd + +Write the above layout in a file, and use ifdtool to modify the IFD of a flash image. +Suppose the above layout file is ``layout.txt`` and the origin content of the system flash +is in ``factory-sys.rom``, run: + + ifdtool -n layout.txt factory-sys.rom + +Then a flash image with a new IFD will be in ``factory-sys.rom.new``. + +Flash the IFD of the system flash: + + flashrom -p --ifd -i fd -w factory-sys.rom.new + +Then flash the coreboot image: + + # first extend the 12M coreboot.rom to 16M + fallocate -l 16M build/coreboot.rom + flashrom -p --ifd -i bios -w build/coreboot.rom + +After coreboot is installed, the coreboot firmware can be updated with internal flashing: + + flashrom -p internal --ifd -i bios --noverify-all -w build/coreboot.rom + +## Debugging + +The board can be debugged with EHCI debug. The EHCI debug port is the USB port on the left. + +## Test status + +### Known issues + +- GRUB payload freezes just like previous EliteBook laptops +- Sometimes the PCIe WLAN module can not be found in the OS after booting to the system +- Sometimes all the USB devices can not be found in the OS after S3 resume + +### Untested + +- Fingerprint reader +- Smart Card reader + +### Working + +- i5-4310U CPU with 4G+4G memory +- SATA and M.2 SATA disk +- Ethernet +- WLAN +- WWAN +- SD card reader +- USB +- Keyboard and touchpad +- DisplayPort +- VGA +- Dock +- Audio output from speaker and headphone jack +- Webcam +- TPM +- EC ACPI +- S3 resume +- Arch Linux with Linux 5.8.9 +- Memory initialization with mrc.bin version 1.6.1 Build 2 +- Graphics initialization with libgfxinit +- Payload: SeaBIOS, Tianocore +- EC firmware + - KBC Revision 92.15 from OEM firmware version 01.33 + - KBC Revision 92.17 from OEM firmware version 01.50 +- Internal flashing under coreboot + +## Technology + +```eval_rst ++------------------+-----------------------------+ +| CPU | Intel Haswell-ULT | ++------------------+-----------------------------+ +| PCH | Intel Lynx Point Low Power | ++------------------+-----------------------------+ +| EC | SMSC MEC1322 | ++------------------+-----------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+-----------------------------+ +``` + +[HP EliteBook Folio 9480m]: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7089926 +[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c05228980 +[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog +[HP Sure Start]: hp_sure_start.md diff --git a/Documentation/mainboard/hp/folio_9480m_flash.webp b/Documentation/mainboard/hp/folio_9480m_flash.webp new file mode 100644 index 0000000000000000000000000000000000000000..1abc3065172ae3fd966965a4d281c8c4666cc736 GIT binary patch literal 40170 zcmV(pK=8j(Nk&HEoB#kBWRj^{z(NG)BF80o?!O>o?F^_a`O!S zx&8apPyP>M{$qb_|8Bk1f8c)N`>6i2{;Sv*`Y-yATEA4E?w|C1hX0*^t^fb)&HJ

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- [EliteBook 8760w](hp/8760w.md) +- [EliteBook Folio 9480m](hp/folio_9480m.md) ## Intel diff --git a/src/mainboard/hp/folio_9480m/Kconfig b/src/mainboard/hp/folio_9480m/Kconfig new file mode 100644 index 0000000000..545a67bae9 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/Kconfig @@ -0,0 +1,50 @@ +if BOARD_HP_FOLIO_9480M + +config BOARD_SPECIFIC_OPTIONS + def_bool y + # The board has a 16MB flash, but the end of the flash needs + # to be reserved, so we use 12MB as default + select BOARD_ROMSIZE_KB_12288 + select EC_HP_KBC1126 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select INTEL_LYNXPOINT_LP + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "hp/folio_9480m" + +config MAINBOARD_PART_NUMBER + string + default "HP EliteBook Folio 9480m" + +config VGA_BIOS_FILE + string + default "pci8086,0a16.rom" + +config VGA_BIOS_ID + string + default "8086,0a16" + +config USBDEBUG_HCD_INDEX + int + default 1 + +config EC_HP_KBC1126_ECFW_IN_CBFS + bool + default n + +config EC_HP_KBC1126_GPE + hex + default 0x6 + +endif diff --git a/src/mainboard/hp/folio_9480m/Kconfig.name b/src/mainboard/hp/folio_9480m/Kconfig.name new file mode 100644 index 0000000000..67c671d4c2 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_FOLIO_9480M + bool "EliteBook Folio 9480m" diff --git a/src/mainboard/hp/folio_9480m/Makefile.inc b/src/mainboard/hp/folio_9480m/Makefile.inc new file mode 100644 index 0000000000..ebe01aea99 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/folio_9480m/acpi/ec.asl b/src/mainboard/hp/folio_9480m/acpi/ec.asl new file mode 100644 index 0000000000..baa17a4181 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include diff --git a/src/mainboard/hp/folio_9480m/acpi/platform.asl b/src/mainboard/hp/folio_9480m/acpi/platform.asl new file mode 100644 index 0000000000..8023ae826c --- /dev/null +++ b/src/mainboard/hp/folio_9480m/acpi/platform.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 +} diff --git a/src/mainboard/hp/folio_9480m/acpi/superio.asl b/src/mainboard/hp/folio_9480m/acpi/superio.asl new file mode 100644 index 0000000000..55b1db5b11 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include diff --git a/src/mainboard/hp/folio_9480m/acpi_tables.c b/src/mainboard/hp/folio_9480m/acpi_tables.c new file mode 100644 index 0000000000..00963e10b0 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/acpi_tables.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/folio_9480m/board_info.txt b/src/mainboard/hp/folio_9480m/board_info.txt new file mode 100644 index 0000000000..fdd0d60142 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7089926 +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: n +Flashrom support: y +Release year: 2014 diff --git a/src/mainboard/hp/folio_9480m/data.vbt b/src/mainboard/hp/folio_9480m/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..1a62a07a93f2d2106c01f4161b3dca2331338edc GIT binary patch literal 4608 zcmds4Z)_Ar6o0dOfA;ovuh(sX>sjiwG;po`vv-tQn;Q47*Lqj3?X_1*CDk5q2co4d z*J5fU;n0$hXz)G|0){{hi9r%g{b2lNFfq`C1RE3a&lej%k$y15kVp)2zS-Lze`?@@ zA&PJF=Dm6Q=C?C%X5P$J4+aKk$RFF<5s6TP5}<;&_;)N+^03k4+^$9L=*O*RITldn&WPta(4nEH3_OpYc~ z+ozHV8XJ7kPZ_2x2KMh6P0*hGdv_#Lt&{DS>T0XExpmWX zvKZ`W@9mC;BmRMKZx8M5r@?T{AB%N#2O=-gXn$`g90(6|1Z8n~9PQ&1Z>IL_eszj^ z+H0s!Rn>aL^isXcw0%4^(Lnv9qqLv-Ow#`3WHR+eGSMK54C4X_CIUdrP;>~0?N1-r z1ds@XOyJSLOu-LO2@nL30Xi@u0AYX{fCxY}KplV+IGJ!JbQ9p>w9zZdB*OE0T?4%i zCb$|0r<3opb^(bg$(R9e5mzsT@>aQ*%pen-&OmhPoor{(-@vZNuq9Z@)9+hFhQFm-HbsK^Orz zhzeO-1*CWnoZ&h6m~Vk@(>#1=qwuxO3Ev|xA&*!EIBQklbL30NKO+BX72zf_Cx{>+ zmm#l1u19_rIgA`bei?Z;@;>CZkPjojk9-pOEb=GFUm$;ld>Q#W66) zNFhT;bjkBkqdtI=#dpZ4XS23AR(<$9zEZplVwMq@s<1HVN!9F^pfZhPF!mK?!y)F0 zwM^zIjoRG~oH_MihkVOr<$i=^dtUx?2dM;lFp==IZKhm@-2(8<8JUOc#OJU9aagv& zYnFN_dKYY%v>q4PSh6deiZS~cq)5xjLN}D228%oQ%G$Qlw@ONG~SgJ5Ji z0CmQJ$3|y#B)WYpIoh**Z?eG3nh+$)K=Z?T)pevfH%^yY3n%(O)zpcSoTcJi}9kpohh2g=|Ne99n0 zDCC}bJfd<>9l4{q8Ol>vU;z{Gg7pSDQu5!_SfHE_d6*Aix&;Ko7!E3PoHV z=5G~`3qL%0&nt?x^GG$vfd5vcH$_FXi=}qjYF8q5anMc=*p;Jp@r0dzX;&8P;!k!8 zlA=grxkLk!G9ZbsNOVS0j!WXKL@!Fp50dzcLm0P-p(GsQn1dd3C?7e*IS0M!P_8+|-yCx7byJ#KB+n>3;$mW|Nv^{VXD-!|R*ZRFfnl`%&LYSs~Zl~tVrxKPA^kiKi!phXc5G;Be zG|OB8eOQ^QSSHdls5EFUB$B%-2haCGh1!`h=E8-M%;;wbcBPOw9B9bQ#@!W~N{u9o zvuVoM^iia(g^a?}mY$uMTZag>tQ7zvm^1p3D$SZ_3Rn*x)XXmQ%~Yw;lWXz_JlL5o zX_i6|)LLymK9f*geYv|Q>jRI=ks&Hztu2Chmowd^Az-Mqj zB0}2QqOXSs?@g{X?b_E;uMO4TnF}6@bOcOcmWS_)8V%xUD2Y3r#jI7X5137nqyi7# zC&ulWePHQwZh)clUGsS7e=MbbvA?URTLp(ZF_>Ze&)ou1{4=g2$Ke{^Fb8lXPfv!* J7RCRE{sQgA5iS4# literal 0 HcmV?d00001 diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb new file mode 100644 index 0000000000..bd81d38197 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -0,0 +1,88 @@ +chip northbridge/intel/haswell + register "dq_pins_interleaved" = "true" + register "ec_present" = "true" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight_pwm_hz" = "200" + register "usb_xhci_on_resume" = "true" + device cpu_cluster 0 on + chip cpu/intel/haswell + register "c1_battery" = "2" + register "c2_battery" = "3" + register "c3_battery" = "9" + + register "c1_acpower" = "2" + register "c2_acpower" = "3" + register "c3_acpower" = "9" + + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x103c 0x22da inherit + device pci 00.0 on end # Host bridge + device pci 02.0 on end # Internal graphics VGA controller + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen4_dec" = "0x000402e9" + register "xhci_default" = "1" + register "sata_ahci" = "1" + register "sata_port1_gen3_dtle" = "0x6" + # SATA(1), M.2(3) + register "sata_port_map" = "0xa" + device pci 13.0 off end # Intel Smart Sound DSP + device pci 14.0 on end # xHCI Controller + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2, Realtek Card Reader + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on # PCIe Port #4, WLAN + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2 2230" "SlotDataBusWidth1X" + end + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + # This laptop uses MEC1322, but it has the same interface + # as the KBC1126 laptops + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/hp/folio_9480m/dsdt.asl b/src/mainboard/hp/folio_9480m/dsdt.asl new file mode 100644 index 0000000000..f030e72471 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } +} diff --git a/src/mainboard/hp/folio_9480m/gma-mainboard.ads b/src/mainboard/hp/folio_9480m/gma-mainboard.ads new file mode 100644 index 0000000000..85e9ded77b --- /dev/null +++ b/src/mainboard/hp/folio_9480m/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- DP1/HDMI1: DisplayPorts on board and dock + HDMI1, + DP2, -- DP2: VGA ports on board and dock + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/folio_9480m/gpio.c b/src/mainboard/hp/folio_9480m/gpio.c new file mode 100644 index 0000000000..cb32f4f733 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/gpio.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + [0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [2] = LP_GPIO_OUT_LOW, + [3] = LP_GPIO_OUT_HIGH, + [4] = LP_GPIO_OUT_HIGH, + [5] = LP_GPIO_OUT_HIGH, + [6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [8] = LP_GPIO_OUT_HIGH, + [9] = LP_GPIO_OUT_HIGH, + [10] = LP_GPIO_OUT_HIGH, + [11] = LP_GPIO_OUT_HIGH, + [12] = LP_GPIO_NATIVE, + [13] = LP_GPIO_OUT_HIGH, + [14] = LP_GPIO_OUT_HIGH, + [15] = LP_GPIO_OUT_HIGH, + [16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [18] = LP_GPIO_OUT_HIGH, + [19] = LP_GPIO_NATIVE, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = LP_GPIO_OUT_HIGH, + [23] = LP_GPIO_OUT_HIGH, + [24] = LP_GPIO_OUT_HIGH, + [25] = LP_GPIO_OUT_HIGH, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = LP_GPIO_OUT_HIGH, + [29] = LP_GPIO_OUT_HIGH, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = LP_GPIO_NATIVE, + [34] = LP_GPIO_OUT_HIGH, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [37] = LP_GPIO_NATIVE, + [38] = LP_GPIO_NATIVE, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [43] = LP_GPIO_OUT_HIGH, + [44] = LP_GPIO_OUT_LOW, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [47] = LP_GPIO_OUT_HIGH, + [48] = LP_GPIO_OUT_LOW, + [49] = LP_GPIO_OUT_HIGH, + [50] = LP_GPIO_OUT_HIGH, + [51] = LP_GPIO_OUT_HIGH, + [52] = LP_GPIO_OUT_HIGH, + [53] = LP_GPIO_OUT_HIGH, + [54] = LP_GPIO_OUT_LOW, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = LP_GPIO_OUT_HIGH, + [57] = LP_GPIO_OUT_LOW, + [58] = LP_GPIO_OUT_HIGH, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [60] = LP_GPIO_OUT_HIGH, + [61] = LP_GPIO_OUT_LOW, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = LP_GPIO_OUT_HIGH, + [65] = LP_GPIO_OUT_LOW, + [66] = LP_GPIO_OUT_HIGH, + [67] = LP_GPIO_OUT_HIGH, + [68] = LP_GPIO_OUT_HIGH, + [69] = LP_GPIO_OUT_HIGH, + [70] = LP_GPIO_OUT_LOW, + [71] = LP_GPIO_NATIVE, + [72] = LP_GPIO_NATIVE, + [73] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [80] = LP_GPIO_OUT_LOW, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_OUT_HIGH, + [83] = LP_GPIO_OUT_HIGH, + [84] = LP_GPIO_OUT_HIGH, + [85] = LP_GPIO_OUT_HIGH, + [86] = LP_GPIO_OUT_HIGH, + [87] = LP_GPIO_OUT_HIGH, + [88] = LP_GPIO_OUT_HIGH, + [89] = LP_GPIO_OUT_HIGH, + [90] = LP_GPIO_OUT_HIGH, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [94] = LP_GPIO_OUT_HIGH, + LP_GPIO_END +}; diff --git a/src/mainboard/hp/folio_9480m/hda_verb.c b/src/mainboard/hp/folio_9480m/hda_verb.c new file mode 100644 index 0000000000..9ee6de01a8 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/hda_verb.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0280, /* Codec Vendor / Device ID: Realtek */ + 0x103c22db, /* Subsystem ID */ + 57, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c22db), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0321101f), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40738105), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* The following is from the OEM firmware */ + 0x02050007, 0x0204c200, 0x02050063, 0x02044800, + 0x02050066, 0x02040809, 0x02050015, 0x02048842, + 0x0205000f, 0x0204cccc, 0x02050010, 0x0204ccdd, + 0x02050065, 0x02042000, 0x0205001c, 0x0204c900, + 0x02050018, 0x02043788, 0x02050008, 0x02048210, + 0x02050068, 0x02043022, 0x02050006, 0x02040800, + 0x02050061, 0x02040403, 0x02050061, 0x02040403, + 0x0205005f, 0x02040800, 0x02050060, 0x02040800, + 0x0205002c, 0x02044002, 0x0205002e, 0x02041ec4, + 0x0205002f, 0x02040000, 0x02050033, 0x0204c5e8, + 0x02050034, 0x02041a98, 0x02050035, 0x0204f5ad, + 0x02050036, 0x0204cbd2, 0x02050037, 0x02041605, + 0x02050038, 0x0204f5ad, 0x02050039, 0x0204ea5f, + 0x0205003a, 0x02040b42, 0x0205003b, 0x0204fb54, + 0x0205003c, 0x0204fcd9, 0x0205003d, 0x02040000, + 0x02050030, 0x02041f5c, 0x02050031, 0x02040111, + 0x02050032, 0x02041f5f, 0x0205003e, 0x02041ea9, + 0x0205002f, 0x02040000, 0x02050042, 0x0204c66e, + 0x02050043, 0x02041a29, 0x02050035, 0x0204f5ad, + 0x02050044, 0x0204ccdd, 0x02050045, 0x02041549, + 0x02050038, 0x0204f5ad, 0x02050046, 0x0204ee79, + 0x02050047, 0x020409f4, 0x0205003b, 0x0204fb54, + 0x02050048, 0x0204fa4c, 0x0205003d, 0x02040000, + 0x0205003f, 0x02041f4d, 0x02050040, 0x02040129, + 0x02050041, 0x02041f51, 0x02050049, 0x02041f61, + 0x0205002f, 0x02040000, 0x0205004d, 0x0204c2f4, + 0x0205004e, 0x02041d2e, 0x02050035, 0x0204f5ad, + 0x0205004f, 0x0204c5e8, 0x02050050, 0x02041a98, + 0x02050038, 0x0204f5ad, 0x02050051, 0x0204d30e, + 0x02050052, 0x020413e6, 0x0205003b, 0x0204fb54, + 0x02050053, 0x02040b73, 0x0205003d, 0x02040000, + 0x0205004a, 0x02041faf, 0x0205004b, 0x0204008a, + 0x0205004c, 0x02041fb0, 0x02050054, 0x02041fb0, + 0x0205002f, 0x02040000, 0x02050058, 0x0204c17a, + 0x02050059, 0x02041e8f, 0x02050035, 0x0204f5ad, + 0x0205005a, 0x0204c2f4, 0x0205005b, 0x02041d2e, + 0x02050038, 0x0204f5ad, 0x0205005c, 0x0204c899, + 0x0205005d, 0x0204195b, 0x0205003b, 0x0204fb54, + 0x0205005e, 0x02041444, 0x0205003d, 0x02040000, + 0x02050055, 0x02041fd8, 0x02050056, 0x02040045, + 0x02050057, 0x02041fd8, 0x0205002c, 0x0204ffc2, + 0x02050026, 0x02042828, 0x02050029, 0x02040250, + 0x02050004, 0x0204c09e, 0x0205000e, 0x02045001, +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c new file mode 100644 index 0000000000..7eeb7bd747 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/romstage.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQF, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQB, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQB, PIRQC, PIRQD); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +void mb_get_spd_map(uint8_t spd_map[4]) +{ + spd_map[0] = 0xa0; + spd_map[2] = 0xa4; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* dock */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* left, EHCI debug */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* right */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WLAN */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* SmartCard */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WWAN */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* Webcam */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + }; + struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + { 1, USB_OC_PIN_SKIP }, /* dock */ + { 1, USB_OC_PIN_SKIP }, /* left */ + { 1, USB_OC_PIN_SKIP }, /* right */ + { 0, USB_OC_PIN_SKIP }, + }; + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); +} From a3ac82092f0d991ad4393f0d31b689760be8338e Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Tue, 3 Nov 2020 10:03:25 +0800 Subject: [PATCH 177/262] mb/google/zork: Create Shuboz variant Create the shuboz variant of the zork reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:172021093 BRANCH=none TEST=emerge-zork coreboot Signed-off-by: Kane Chen Change-Id: I3f62625f8cbde1c9adf8ab335edeb9e811e32679 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47152 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/google/zork/Kconfig | 2 + src/mainboard/google/zork/Kconfig.name | 4 ++ .../google/zork/variants/shuboz/Makefile.inc | 3 ++ .../shuboz/include/variant/acpi/audio.asl | 3 ++ .../shuboz/include/variant/acpi/mainboard.asl | 3 ++ .../shuboz/include/variant/acpi/thermal.asl | 3 ++ .../zork/variants/shuboz/include/variant/ec.h | 3 ++ .../variants/shuboz/include/variant/gpio.h | 3 ++ .../variants/shuboz/include/variant/thermal.h | 3 ++ .../zork/variants/shuboz/overridetree.cb | 42 +++++++++++++++++++ .../zork/variants/shuboz/spd/Makefile.inc | 5 +++ .../variants/shuboz/spd/dram_id.generated.txt | 1 + .../variants/shuboz/spd/mem_parts_used.txt | 9 ++++ 13 files changed, 84 insertions(+) create mode 100644 src/mainboard/google/zork/variants/shuboz/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/shuboz/include/variant/acpi/audio.asl create mode 100644 src/mainboard/google/zork/variants/shuboz/include/variant/acpi/mainboard.asl create mode 100644 src/mainboard/google/zork/variants/shuboz/include/variant/acpi/thermal.asl create mode 100644 src/mainboard/google/zork/variants/shuboz/include/variant/ec.h create mode 100644 src/mainboard/google/zork/variants/shuboz/include/variant/gpio.h create mode 100644 src/mainboard/google/zork/variants/shuboz/include/variant/thermal.h create mode 100644 src/mainboard/google/zork/variants/shuboz/overridetree.cb create mode 100644 src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt create mode 100644 src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index eb9092a6d1..02181fba13 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -71,6 +71,7 @@ config VARIANT_DIR default "vilboz" if BOARD_GOOGLE_VILBOZ default "woomax" if BOARD_GOOGLE_WOOMAX default "dirinboz" if BOARD_GOOGLE_DIRINBOZ + default "shuboz" if BOARD_GOOGLE_SHUBOZ config MAINBOARD_PART_NUMBER string @@ -82,6 +83,7 @@ config MAINBOARD_PART_NUMBER default "Vilboz" if BOARD_GOOGLE_VILBOZ default "Woomax" if BOARD_GOOGLE_WOOMAX default "Dirinboz" if BOARD_GOOGLE_DIRINBOZ + default "Shuboz" if BOARD_GOOGLE_SHUBOZ config DEVICETREE string diff --git a/src/mainboard/google/zork/Kconfig.name b/src/mainboard/google/zork/Kconfig.name index 6f9a90c682..8ed43f0a8b 100644 --- a/src/mainboard/google/zork/Kconfig.name +++ b/src/mainboard/google/zork/Kconfig.name @@ -31,3 +31,7 @@ config BOARD_GOOGLE_WOOMAX config BOARD_GOOGLE_DIRINBOZ bool "-> Dirinboz" select BOARD_GOOGLE_BASEBOARD_DALBOZ + +config BOARD_GOOGLE_SHUBOZ + bool "-> Shuboz" + select BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/variants/shuboz/Makefile.inc b/src/mainboard/google/zork/variants/shuboz/Makefile.inc new file mode 100644 index 0000000000..295acd25c9 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/audio.asl new file mode 100644 index 0000000000..900e36f277 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..a1161edb5f --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..7a793d8102 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/ec.h b/src/mainboard/google/zork/variants/shuboz/include/variant/ec.h new file mode 100644 index 0000000000..9e61a440cf --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/gpio.h b/src/mainboard/google/zork/variants/shuboz/include/variant/gpio.h new file mode 100644 index 0000000000..dfaeec3ae1 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/shuboz/include/variant/thermal.h b/src/mainboard/google/zork/variants/shuboz/include/variant/thermal.h new file mode 100644 index 0000000000..2af647973d --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb new file mode 100644 index 0000000000..1cc2364f5e --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #56670 Chapter 5 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "1" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "2500" + register "sustained_power_limit_mW" = "4800" + + # End : OPN Performance Configuration + + # I2C2 for touchscreen and trackpad + + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + }" + + # I2C3 for H1 + + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + end # domain + + device mmio 0xfedc4000 on # APU_I2C2_BASE + end # device + +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc new file mode 100644 index 0000000000..3edeb9606c --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = ddr4-spd-empty.hex diff --git a/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt new file mode 100644 index 0000000000..fa247902ee --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt new file mode 100644 index 0000000000..106a705a36 --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt @@ -0,0 +1,9 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) From 94fe086a067ad635246f40a339748182ef7b943e Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 15 Oct 2020 13:57:52 +0200 Subject: [PATCH 178/262] sec/intel/cbnt: Stitch in ACMs in the coreboot image Actual support CBnT will be added later on. Change-Id: Icc35c5e6c74d002efee43cc05ecc8023e00631e0 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/46456 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- Makefile.inc | 12 ++++++++++++ src/cpu/intel/fit/Kconfig | 2 +- src/security/intel/Kconfig | 1 + src/security/intel/Makefile.inc | 1 + src/security/intel/cbnt/Kconfig | 27 +++++++++++++++++++++++++++ src/security/intel/cbnt/Makefile.inc | 25 +++++++++++++++++++++++++ src/security/intel/txt/Kconfig | 1 + src/security/intel/txt/Makefile.inc | 4 ++++ 8 files changed, 72 insertions(+), 1 deletion(-) create mode 100644 src/security/intel/cbnt/Kconfig create mode 100644 src/security/intel/cbnt/Makefile.inc diff --git a/Makefile.inc b/Makefile.inc index b3868a5fbb..69ac747800 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -732,6 +732,16 @@ TXTIBB := endif +ifeq ($(CONFIG_INTEL_CBNT_SUPPORT),y) + +CBNTIBB := --cbnt + +else + +CBNTIBB := + +endif # CONFIG_INTEL_CBNT_SUPPORT + ifeq ($(CONFIG_COMPRESS_BOOTBLOCK),y) $(objcbfs)/bootblock.lz4: $(objcbfs)/bootblock.elf $(objutil)/cbfstool/cbfs-compression-tool @@ -1063,6 +1073,7 @@ $(obj)/fmap.fmap: $(obj)/fmap.fmd $(FMAPTOOL) ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE) endif + ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(IFITTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc) @@ -1072,6 +1083,7 @@ ifeq ($(CONFIG_ARCH_X86),y) -n bootblock \ -t bootblock \ $(TXTIBB) \ + $(CBNTIBB) \ -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \ $(TS_OPTIONS) else # ifeq ($(CONFIG_ARCH_X86),y) diff --git a/src/cpu/intel/fit/Kconfig b/src/cpu/intel/fit/Kconfig index fa10802926..9ea867e579 100644 --- a/src/cpu/intel/fit/Kconfig +++ b/src/cpu/intel/fit/Kconfig @@ -5,7 +5,7 @@ config CPU_INTEL_FIRMWARE_INTERFACE_TABLE config CPU_INTEL_NUM_FIT_ENTRIES int - default 16 if INTEL_TXT + default 16 if INTEL_TXT || INTEL_CBNT_SUPPORT default 4 depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE help diff --git a/src/security/intel/Kconfig b/src/security/intel/Kconfig index 9cdd8a6610..0609a45684 100644 --- a/src/security/intel/Kconfig +++ b/src/security/intel/Kconfig @@ -2,3 +2,4 @@ source "src/security/intel/txt/Kconfig" source "src/security/intel/stm/Kconfig" +source "src/security/intel/cbnt/Kconfig" diff --git a/src/security/intel/Makefile.inc b/src/security/intel/Makefile.inc index e00802ad06..20aea273e0 100644 --- a/src/security/intel/Makefile.inc +++ b/src/security/intel/Makefile.inc @@ -1,2 +1,3 @@ subdirs-y += txt subdirs-y += stm +subdirs-y += cbnt diff --git a/src/security/intel/cbnt/Kconfig b/src/security/intel/cbnt/Kconfig new file mode 100644 index 0000000000..f13f6ec59c --- /dev/null +++ b/src/security/intel/cbnt/Kconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config INTEL_CBNT_SUPPORT + bool "Intel CBnT support" + default n + depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE + #depends on PLATFORM_HAS_DRAM_CLEAR + select INTEL_TXT + help + Enables Intel Converged Bootguard and Trusted Execution Technology + Support. This will enable one to add a Key Manifest (KM) and a Boot + Policy Manifest (BPM) to the filesystem. It will also wrap a FIT around + the firmware and update appropriate entries. + +if INTEL_CBNT_SUPPORT + +config INTEL_CBNT_KEY_MANIFEST_BINARY + string "KM (Key Manifest) binary location" + help + Location of the Key Manifest (KM) + +config INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY + string "BPM (Boot Policy Manifest) binary location" + help + Location of the Boot Policy Manifest (BPM) + +endif # INTEL_CBNT_SUPPORT diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc new file mode 100644 index 0000000000..f2e5c76dba --- /dev/null +++ b/src/security/intel/cbnt/Makefile.inc @@ -0,0 +1,25 @@ +ifeq ($(CONFIG_INTEL_CBNT_SUPPORT),y) + +ifneq ($(CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY),"") +cbfs-files-y += boot_policy_manifest.bin +boot_policy_manifest.bin-file := $(CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY) +boot_policy_manifest.bin-type := raw +boot_policy_manifest.bin-align := 0x10 + +INTERMEDIATE+=add_bpm_fit +add_bpm_fit: $(obj)/coreboot.pre $(IFITTOOL) + $(IFITTOOL) -r COREBOOT -a -n boot_policy_manifest.bin -t 12 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< +endif + +ifneq ($(CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY),"") +cbfs-files-y += key_manifest.bin +key_manifest.bin-file := $(CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY) +key_manifest.bin-type := raw +key_manifest.bin-align := 0x10 + +INTERMEDIATE+=add_km_fit +add_km_fit: $(obj)/coreboot.pre $(IFITTOOL) + $(IFITTOOL) -r COREBOOT -a -n key_manifest.bin -t 11 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< +endif + +endif # CONFIG_INTEL_CBNT_SUPPORT diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index 80be7c29e9..f9e4bc4bf4 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -52,6 +52,7 @@ config INTEL_TXT_LOGGING config INTEL_TXT_BIOSACM_ALIGNMENT hex + default 0x40000 if INTEL_CBNT_SUPPORT default 0x20000 # 128 KiB help Exceptions are Ivy and Sandy Bridge with 64 KiB and Purley with 256 KiB diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index eab47b95f9..77a5f69f2a 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -33,6 +33,8 @@ add_acm_fit: $(obj)/coreboot.pre $(IFITTOOL) $(IFITTOOL) -r COREBOOT -a -n $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM) -t 2 \ -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< +# CBnT does not use FIT for IBB +ifneq ($(CONFIG_INTEL_CBNT_SUPPORT),y) # Initial BootBlock files ibb-files := $(foreach file,$(cbfs-files), \ $(if $(shell echo '$(call extract_nth,7,$(file))'|grep -- --ibb), \ @@ -45,6 +47,8 @@ add_ibb_fit: $(obj)/coreboot.pre $(IFITTOOL) $(foreach file, $(ibb-files), $(shell $(IFITTOOL) -f $< -a -n $(file) -t 7 \ -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT)) true +endif # INTEL_CBNT_SUPPORT + endif # CPU_INTEL_FIRMWARE_INTERFACE_TABLE endif # INTEL_TXT From eaaa549e4a176637198f50570b81ecd3a7cf9549 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 28 Oct 2020 19:30:36 +0100 Subject: [PATCH 179/262] cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registers It is too easy to confuse those with IA32_SMRR_PHYS_x registers. Change-Id: Ice02ab6c0315a2be14ef110ede506262e3c0a4d5 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/46896 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/intel/smm/gen1/smmrelocate.c | 4 ++-- src/include/cpu/x86/mtrr.h | 7 ++++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index ae2440daab..36884a1b1c 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -59,8 +59,8 @@ static void write_smrr_alt(struct smm_relocation_params *relo_params) printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); + wrmsr(CORE2_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(CORE2_SMRR_PHYS_MASK, relo_params->smrr_mask); } static void fill_in_relocation_params(struct smm_relocation_params *params) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 3bf8301cfd..b8d15179e9 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -31,9 +31,10 @@ #define IA32_SMRR_PHYS_MASK 0x1f3 #define SMRR_PHYS_MASK_LOCK (1 << 10) -/* Specific to model_6fx and model_1067x */ -#define MSR_SMRR_PHYS_BASE 0xa0 -#define MSR_SMRR_PHYS_MASK 0xa1 +/* Specific to model_6fx and model_1067x. + These are named MSR_SMRR_PHYSBASE in the SDM. */ +#define CORE2_SMRR_PHYS_BASE 0xa0 +#define CORE2_SMRR_PHYS_MASK 0xa1 #define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg)) #define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1) From e0af9fcb2d526ffd654d0bb573dd5333d0d76269 Mon Sep 17 00:00:00 2001 From: Jakub Czapiga Date: Fri, 9 Oct 2020 16:02:46 +0200 Subject: [PATCH 180/262] tests: Add lib/edid-test test case Signed-off-by: Jakub Czapiga Change-Id: I796e660eebc4d2c3c32207bd3a6ee44aaffeb325 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46817 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg --- tests/include/lib/edid-test.h | 196 +++++ tests/lib/Makefile.inc | 6 + tests/lib/edid-test.c | 1272 +++++++++++++++++++++++++++++++++ tests/stubs/console.c | 7 + 4 files changed, 1481 insertions(+) create mode 100644 tests/include/lib/edid-test.h create mode 100644 tests/lib/edid-test.c diff --git a/tests/include/lib/edid-test.h b/tests/include/lib/edid-test.h new file mode 100644 index 0000000000..073905d5f0 --- /dev/null +++ b/tests/include/lib/edid-test.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + + +struct edid_raw { + uint8_t header[8]; + + /* Display product identification */ + uint16_t manufacturer_id; + uint16_t product_code; + uint32_t serial_number; + uint8_t manufacture_week; + uint8_t manufacture_year; + + /* EDID version information */ + uint8_t edid_version; + uint8_t edid_revision; + + /* Basic display parameters */ + uint8_t video_input_type; + uint8_t horizontal_size; /* [cm] */ + uint8_t vertical_size; /* [cm] */ + uint8_t display_gamma; + uint8_t supported_features; + + /* Color space definition */ + uint8_t color_characteristics[10]; + + /* Timing information */ + uint8_t established_supported_timings[2]; + uint8_t manufacturers_reserved_timing; + uint8_t standard_timings_supported[16]; + uint8_t descriptor_block_1[18]; + uint8_t descriptor_block_2[18]; + uint8_t descriptor_block_3[18]; + uint8_t descriptor_block_4[18]; + + /* Number of optional 128-byte extension blocks */ + uint8_t extension_flag; + + uint8_t checksum; +} __packed; + +_Static_assert(sizeof(struct edid_raw) == 128); + +#define EDID_HEADER_RAW { 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00 } +#define EDID_HEADER_INVALID_RAW { 0, 0, 0, 0, 0, 0, 0, 0 } + +#define EDID_MANUFACTURER_ID 0xcb55 +#define EDID_MANUFACTURER_NAME "UNK" +#define EDID_PRODUCT_CODE 0x1234 +#define EDID_SERIAL_NUMBER 0x56789ABC +#define EDID_MANUFACTURE_WEEK 23u +#define EDID_MANUFACTURE_NO_WEEK 0u +#define EDID_MANUFACTURE_YEAR (2015u - 1990u) + +/* Video Input Definition for Analog Video Signal Interface */ +#define EDID_ANALOG_VSI (0u << 7) +#define EDID_SIGNAL_LEVEL_0 0u +#define EDID_SIGNAL_LEVEL_1 (1u << 5) +#define EDID_SIGNAL_LEVEL_2 (2u << 5) +#define EDID_SIGNAL_LEVEL_3 (3u << 5) +#define EDID_VIDEO_SETUP_BLANK_EQ_BLACK 0u +#define EDID_VIDEO_SETUP_BLANK_TO_BLACK (1u << 4) +#define EDID_SEPARATE_SYNC_H_AND_V(v) ((v != 0 ? 0x1 : 0x0) << 3) +#define EDID_COMPOSITE_SYNC_H(v) ((v != 0 ? 0x1 : 0x0) << 2) +#define EDID_COMPOSITE_SYNC_ON_GREEN(v) ((v != 0 ? 0x1 : 0x0) << 1) +#define EDID_SERRATION_VSYNC(v) (v != 0 ? 0x1 : 0x0) + +/* Video Input Definition for Digital Video Signal Interface */ +#define EDID_DIGITAL_VSI (1u << 7) +#define EDID_COLOR_BIT_DEPTH_UNDEFINED 0u +#define EDID_COLOR_BIT_DEPTH_6B (1u << 4) +#define EDID_COLOR_BIT_DEPTH_8B (2u << 4) +#define EDID_COLOR_BIT_DEPTH_10B (3u << 4) +#define EDID_COLOR_BIT_DEPTH_12B (4u << 4) +#define EDID_COLOR_BIT_DEPTH_14B (5u << 4) +#define EDID_COLOR_BIT_DEPTH_16B (6u << 4) +#define EDID_INTERFACE_UNDEFINED 0u +#define EDID_INTERFACE_DVI 1u +#define EDID_INTERFACE_HDMI_A 2u +#define EDID_INTERFACE_HDMI_B 3u +#define EDID_INTERFACE_MDDI 4u +#define EDID_INTERFACE_DP 5u + +/* BEGIN Supported features */ +#define EDID_STANDBY_MODE(v) ((v != 0 ? 0x1 : 0x0) << 7) +#define EDID_SUSPEND_MODE(v) ((v != 0 ? 0x1 : 0x0) << 6) +#define EDID_ACTIVE_OFF(v) ((v != 0 ? 0x1 : 0x0) << 5) +/* For analog interface */ +#define EDID_COLOR_TYPE_MONO 0u +#define EDID_COLOR_TYPE_RGB (1u << 3) +#define EDID_COLOR_TYPE_NON_RGB (2u << 3) +#define EDID_COLOR_TYPE_UNDEFINED (3u << 3) +/* For digital interface */ +#define EDID_COLOR_FORMAT_RGB444 0u +#define EDID_COLOR_FORMAT_RGB444_YCRCB444 (1u << 3) +#define EDID_COLOR_FORMAT_RGB444_YCRCB422 (2u << 3) +#define EDID_COLOR_FORMAT_RGB444_YCRCB422_YCRCB422 (3u << 3) + +#define EDID_SRGB_SUPPORTED(v) (((v) == 0 ? 0u : 1u) << 2) +#define EDID_PREFERRED_TIMING_EXTENDED_INFO (1u << 1) +#define EDID_PREFERRED_TIMING_NO_EXTENDED_INFO 0u +#define EDID_DISPLAY_FREQUENCY_CONTINUOUS 1u +#define EDID_DISPLAY_FREQUENCY_NON_CONTINUOUS 0u +/* END Supported features */ + +/* Red X 0.640 */ +#define EDID_COLOR_R_X 0x25 +/* Red Y 0.330 */ +#define EDID_COLOR_R_Y 0x152 +/* Green X 0.300 */ +#define EDID_COLOR_G_X 0x13a +/* Green Y 0.600 */ +#define EDID_COLOR_G_Y 0x267 +/* Blue X 0.150 */ +#define EDID_COLOR_B_X 0x9a +/* Blue Y 0.060 */ +#define EDID_COLOR_B_Y 0x3e +/* White X 0.3125 */ +#define EDID_COLOR_W_X 0xa +/* White Y 0.3291 */ +#define EDID_COLOR_W_Y 0x22a + +/* 1 and 0 bits of each color */ +#define EDID_COLOR_R_X10_Y10 (((EDID_COLOR_R_X & 0x3) << 2) | (EDID_COLOR_R_Y & 0x3)) +#define EDID_COLOR_G_X10_Y10 (((EDID_COLOR_G_X & 0x3) << 2) | (EDID_COLOR_G_Y & 0x3)) +#define EDID_COLOR_B_X10_Y10 (((EDID_COLOR_B_X & 0x3) << 2) | (EDID_COLOR_B_Y & 0x3)) +#define EDID_COLOR_W_X10_Y10 (((EDID_COLOR_W_X & 0x3) << 2) | (EDID_COLOR_W_Y & 0x3)) + +/* Concatenated 0 and 1 bits of each color. To be put + * as first and second byte of color characteristic. */ +#define EDID_COLOR_RG_XY ((EDID_COLOR_R_X10_Y10 << 4) | EDID_COLOR_G_X10_Y10) +#define EDID_COLOR_BW_XY ((EDID_COLOR_B_X10_Y10 << 4) | EDID_COLOR_W_X10_Y10) + +/* Bits 9 through 2 of each color */ +#define EDID_COLOR_R_X92 (EDID_COLOR_R_X >> 2) +#define EDID_COLOR_R_Y92 (EDID_COLOR_R_Y >> 2) +#define EDID_COLOR_G_X92 (EDID_COLOR_G_X >> 2) +#define EDID_COLOR_G_Y92 (EDID_COLOR_G_Y >> 2) +#define EDID_COLOR_B_X92 (EDID_COLOR_B_X >> 2) +#define EDID_COLOR_B_Y92 (EDID_COLOR_B_Y >> 2) +#define EDID_COLOR_W_X92 (EDID_COLOR_W_X >> 2) +#define EDID_COLOR_W_Y92 (EDID_COLOR_W_Y >> 2) + +#define EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz 1u +#define EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz (1u << 1) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz (1u << 2) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz (1u << 3) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz (1u << 4) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz (1u << 5) +#define EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz (1u << 6) +#define EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz (1u << 7) + +#define EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz 1u +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz (1u << 1) +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz (1u << 2) +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz (1u << 3) +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_80HzI (1u << 4) +#define EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz (1u << 5) +#define EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz (1u << 6) +#define EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz (1u << 7) + +#define EDID_MANUFACTURERS_TIMINGS_1152x870_75Hz (1u << 7) + +#define EDID_HORIZONTAL_ACCESSIBLE_PIXELS(px) (((px) / 8 - 31) & 0xFF) +#define EDID_ASPECT_RATIO_16_10 0u +#define EDID_ASPECT_RATIO_4_3 (1u << 6) +#define EDID_ASPECT_RATIO_5_4 (2u << 6) +#define EDID_ASPECT_RATIO_16_9 (3u << 6) +#define EDID_FIELD_REFRESH_RATE(hz) (((hz) - 60) & 0x1f) + +#define EDID_PIXEL_CLOCK(v) (((v) / 10000) & 0xFFFF) + +#define EDID_RAW_DEFAULT_PARAMS .header = EDID_HEADER_RAW, \ + .edid_version = 1, \ + .edid_revision = 4, \ + .manufacturer_id = EDID_MANUFACTURER_ID, \ + .product_code = EDID_PRODUCT_CODE, \ + .serial_number = EDID_SERIAL_NUMBER, \ + .manufacture_week = EDID_MANUFACTURE_NO_WEEK, \ + .manufacture_year = EDID_MANUFACTURE_YEAR, \ + .color_characteristics = { \ + EDID_COLOR_RG_XY, \ + EDID_COLOR_BW_XY, \ + EDID_COLOR_R_X92, \ + EDID_COLOR_R_Y92, \ + EDID_COLOR_G_X92, \ + EDID_COLOR_G_Y92, \ + EDID_COLOR_B_X92, \ + EDID_COLOR_B_Y92, \ + EDID_COLOR_W_X92, \ + EDID_COLOR_W_Y92, \ + } diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 27773b7f39..219f7e7634 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -5,6 +5,7 @@ tests-y += b64_decode-test tests-y += hexstrtobin-test tests-y += imd-test tests-y += timestamp-test +tests-y += edid-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -24,3 +25,8 @@ timestamp-test-srcs += tests/lib/timestamp-test.c timestamp-test-srcs += tests/stubs/timestamp.c timestamp-test-srcs += tests/stubs/console.c timestamp-test-stage := romstage + +edid-test-srcs += tests/lib/edid-test.c +edid-test-srcs += src/lib/edid.c +edid-test-srcs += tests/stubs/console.c + diff --git a/tests/lib/edid-test.c b/tests/lib/edid-test.c new file mode 100644 index 0000000000..0da7c61853 --- /dev/null +++ b/tests/lib/edid-test.c @@ -0,0 +1,1272 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +struct test_state { + int data_size; + void *data; +}; + +static uint8_t get_raw_edid_checksum(const unsigned char *x) +{ + unsigned char sum = 0; + int i; + for (i = 0; i < 127; ++i) + sum += x[i]; + + return 256 - sum; +} + +static void edid_raw_calc_checksum(struct edid_raw *raw) +{ + raw->checksum = get_raw_edid_checksum((const unsigned char *)raw); +} + +static void test_decode_edid_no_edid(void **state) +{ + assert_int_equal(EDID_ABSENT, decode_edid(NULL, 0, NULL)); +} + +static void test_decode_edid_invalid_header(void **state) +{ + struct edid_raw raw = { + .header = EDID_HEADER_INVALID_RAW + }; + raw.checksum = get_raw_edid_checksum((const unsigned char *)&raw); + + assert_int_equal(EDID_ABSENT, decode_edid((unsigned char *)&raw, sizeof(raw), NULL)); +} + +/* Frame is modified example of an LCD Desktop IT display + * from VESA E-EDID Standard Release A2. + */ +static int setup_decode_edid_basic_frame(void **state) +{ + struct edid_raw raw = { + EDID_RAW_DEFAULT_PARAMS, + .video_input_type = EDID_ANALOG_VSI + | EDID_SIGNAL_LEVEL_0 + | EDID_VIDEO_SETUP_BLANK_EQ_BLACK + | EDID_SEPARATE_SYNC_H_AND_V(1) + | EDID_COMPOSITE_SYNC_H(1) + | EDID_COMPOSITE_SYNC_ON_GREEN(1) + | EDID_SERRATION_VSYNC(1), + .horizontal_size = 43, /* [cm] */ + .vertical_size = 32, /* [cm] */ + .display_gamma = 120, /* 220% */ + .supported_features = EDID_STANDBY_MODE(0) + | EDID_SUSPEND_MODE(0) + | EDID_ACTIVE_OFF(1) + | EDID_COLOR_FORMAT_RGB444 + | EDID_SRGB_SUPPORTED(0) + | EDID_PREFERRED_TIMING_EXTENDED_INFO + | EDID_DISPLAY_FREQUENCY_CONTINUOUS, + .established_supported_timings = { + [0] = EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz + | EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz + | EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz + | EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz, + [1] = EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz + | EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz + | EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_80HzI + | EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz + | EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz, + }, + .manufacturers_reserved_timing = EDID_MANUFACTURERS_TIMINGS_1152x870_75Hz, + .standard_timings_supported = { + [0] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600), + [1] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85), + + [2] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600), + [3] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(75), + + [4] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600), + [5] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(70), + + [6] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600), + [7] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(65), + + [8] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [9] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(85), + + [10] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [11] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(60), + + [12] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1024), + [13] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85), + + [14] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(800), + [15] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85), + }, + .descriptor_block_1 = { + [0] = EDID_PIXEL_CLOCK(162000000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(162000000u) >> 8) & 0xFF, + + /* + * Horizontal Addressable Video is 1600px + * Horizontal Blanking is 560px + */ + [2] = 0x40, [3] = 0x30, [4] = 0x62, + + /* + * Vertical Addressable Video is 1200 lines + * Vertical Blanking is 50 lines + */ + [5] = 0xB0, [6] = 0x32, [7] = 0x40, + + [8] = 64u, /* Horizontal Front Porch in pixels */ + [9] = 192u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 0x13, /* Vertical Front Porch is 1 line */ + [11] = 0x00, /* Vertical Sync Pulse Width is 3 lines */ + + /* + * Horizontal Addressable Image Size is 427mm + * Vertical Addressable Image Size is 320mm + */ + [12] = 0xAB, [13] = 0x40, [14] = 0x11, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* + * Timing is Non-Interlaced Video, + * Stereo Video is not supported, + * Digital separate syncs are requires. + * */ + [17] = 0x1E, + }, + .descriptor_block_2 = { + /* Display Range Limits Block Tag */ + [0] = 0, [1] = 0, [2] = 0, [3] = 0xFD, + + [4] = 0, /* Horizontal and Vertical Rate Offsets are zero */ + [5] = 50u, /* Minimum Vertical Freq is 50Hz */ + [6] = 90u, /* Maximum Vertical Freq is 90Hz */ + + [7] = 30u, /* Minimum Horizontal Freq is 30kHz */ + [8] = 110u, /* Maximum Horizontal Freq is 110kHz */ + [9] = 23u, /* Maximum Pixel Clock Freq i 230MHz */ + [10] = 0x4, /* Begin CVT Support Info */ + [11] = 0x11, /* Compatible with CVT Version 1.1 */ + [12] = 0, /* Maimum Pixel Clock Freq remains at 230MHz */ + [13] = 200, /* Maximum Active Pixels per Pile is 1600 */ + [14] = 0x90, /* Supported aspect ratios: 4:3, 5:4 */ + + /* Preferred Aspect Ratio is 4:3, Standard CVT Blanking is supported */ + [15] = 0, + [16] = 0x50, /* H. & V. Stretch are supported and Shrinks are not */ + [17] = 60u, /* Preferred Refresh Rate is 60Hz */ + }, + .descriptor_block_3 = { + /* Established Timings III Block Tag */ + [0] = 0, [1] = 0, [2] = 0, [3] = 0xF7, [4] = 0, + + [5] = 10u, /* VESA DMT Standard Version #10 */ + /* + * 640x350@85Hz, + * 640x400@85Hz, + * 720x400@85Hz, + * 640x480@85Hz, + * 800x600@85Hz, + * 1024x768@85Hz, + * 1152x864@75Hz + */ + [6] = 0x7F, + + /* + * 1280x960@60Hz, + * 1280x960@85Hz, + * 1280x1024@60Hz, + * 1280x1024@85Hz + */ + [7] = 0x0F, + + /* + * 1400x1050@60Hz (Normal Blanking), + * 1400x1050@75Hz are supported. + */ + [8] = 0x03, + + /* + * 1400x1050@85Hz, + * 1600x1200@60Hz, + * 1600x1200@65Hz, + * 1600x1200@70Hz are supported. + */ + [9] = 0x87, + + /* + * 1600x1200@75Hz, + * 1600x1200@85Hz are supported. + */ + [10] = 0xC0, + + /* 1920 timings not supported */ + [11] = 0x0, + + [12 ... 17] = 0, + }, + .descriptor_block_4 = { + /* Display Product Name Block Tag */ + [0] = 0, [1] = 0, [2] = 0, [3] = 0xFC, [4] = 0, + + /* Product name */ + [5] = 'A', + [6] = 'B', + [7] = 'C', + [8] = ' ', + [9] = 'L', + [10] = 'C', + [11] = 'D', + [12] = '2', + [13] = '1', + [14] = '\n', + [15] = ' ', + [16] = ' ', + [17] = ' ', + }, + .extension_flag = 0x0, /* No extensions */ + }; + + edid_raw_calc_checksum(&raw); + + *state = malloc(sizeof(struct test_state)); + + struct test_state ts = { + .data_size = sizeof(struct edid_raw), + .data = malloc(sizeof(struct edid_raw)) + }; + + memcpy(ts.data, &raw, sizeof(raw)); + memcpy(*state, &ts, sizeof(ts)); + + return 0; +} + +/* Test decoding of EDID frame without extensions. + */ +static void test_decode_edid_basic_frame(void **state) +{ + struct edid out; + struct test_state *ts = *state; + + /* In real-life situations frames often are not 100% conformant, + * but are at least correct when it comes to key data fields. + */ + assert_int_equal(EDID_CONFORMANT, + decode_edid((unsigned char *)ts->data, ts->data_size, &out)); + + assert_int_equal(32, out.framebuffer_bits_per_pixel); + assert_int_equal(0, out.panel_bits_per_color); + assert_int_equal(0, out.panel_bits_per_pixel); + assert_int_equal(0, out.link_clock); + assert_int_equal(1600, out.x_resolution); + assert_int_equal(1200, out.y_resolution); + assert_int_equal(6400, out.bytes_per_line); + assert_int_equal(0, out.hdmi_monitor_detected); + assert_int_equal(0, strnlen(out.ascii_string, ARRAY_SIZE(out.ascii_string))); + assert_string_equal(out.manufacturer_name, EDID_MANUFACTURER_NAME); + + /* Mode */ + assert_null(out.mode.name); + assert_int_equal(162000, out.mode.pixel_clock); + assert_int_equal(1, out.mode.lvds_dual_channel); + assert_int_equal(0, out.mode.refresh); + assert_int_equal(1600, out.mode.ha); + assert_int_equal(560, out.mode.hbl); + assert_int_equal(64, out.mode.hso); + assert_int_equal(192, out.mode.hspw); + assert_int_equal(0, out.mode.hborder); + assert_int_equal(1200, out.mode.va); + assert_int_equal(50, out.mode.vbl); + assert_int_equal(1, out.mode.vso); + assert_int_equal(0, out.mode.vborder); + assert_int_equal(43, out.mode.phsync); + assert_int_equal(43, out.mode.pvsync); + assert_int_equal(0, out.mode.x_mm); + assert_int_equal(0, out.mode.y_mm); + + assert_int_equal(1, out.mode_is_supported[EDID_MODE_640x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_720x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1280x720_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1920x1080_60Hz]); +} + +/* Frame is modified example of base EDID frame with CEA861 extension + * for DTV Display from VESA E-EDID Standard Release A2. + */ +static int setup_decode_edid_dtv_frame_with_extension(void **state) +{ + struct edid_raw raw = { + EDID_RAW_DEFAULT_PARAMS, + .video_input_type = EDID_DIGITAL_VSI + | EDID_INTERFACE_HDMI_A + | EDID_COLOR_BIT_DEPTH_8B, + .horizontal_size = 16, /* Aspect ratio 16:9 in landscape */ + .vertical_size = 0, /* Landscape flag */ + .display_gamma = 120, /* 220% */ + .supported_features = EDID_STANDBY_MODE(0) + | EDID_SUSPEND_MODE(0) + | EDID_ACTIVE_OFF(0) + | EDID_COLOR_FORMAT_RGB444_YCRCB422_YCRCB422 + | EDID_SRGB_SUPPORTED(1) + | EDID_PREFERRED_TIMING_EXTENDED_INFO + | EDID_DISPLAY_FREQUENCY_NON_CONTINUOUS, + + .established_supported_timings = { + [0] = EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz, + [1] = 0, + }, + .manufacturers_reserved_timing = 0, + .standard_timings_supported = { [0 ... 15] = 0, }, + .descriptor_block_1 = { + [0] = EDID_PIXEL_CLOCK(148500000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(148500000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1920px + * Horizontal Blanking is 280px + */ + [2] = 0x80, [3] = 0x18, [4] = 0x71, + + /* Vertical Addressable Video is 1080 lines + * Vertical Blanking is 45 lines + */ + [5] = 0x38, [6] = 0x2D, [7] = 0x40, + + [8] = 88u, /* Horizontal Front Porch in pixels */ + [9] = 44u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 4u, /* Vertical Front Porch is 4 lines */ + [11] = 5u, /* Vertical Sync Pulse Width is 5 lines */ + + /* Horizontal Addressable Image Size is 1039mm + * Vertical Addressable Image Size is 584mm + */ + [12] = 0x0F, [13] = 0x48, [14] = 0x42, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* Timing is Non-Interlaced Video, + * Stereo Video is not supported, + * Digital separate and syncs are requires. + */ + [17] = 0x1E, + }, + .descriptor_block_2 = { + [0] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1920px + * Horizontal Blanking is 280px + */ + [2] = 0x80, [3] = 0x18, [4] = 0x71, + + /* Vertical Addressable Video is 540 lines + * Vertical Blanking is 22 lines + */ + [5] = 0x1C, [6] = 0x16, [7] = 0x20, + + [8] = 88u, /* Horizontal Front Porch in pixels */ + [9] = 44u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 0x25, /* Vertical Front Porch is 2 lines */ + [11] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + + /* Horizontal Addressable Image Size is 1039mm + * Vertical Addressable Image Size is 584mm + */ + [12] = 0x0F, [13] = 0x48, [14] = 0x42, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* Timing is Interlaced Video, + * Stereo Video is not supported, + * Digital separate and syncs are requires. + */ + [17] = 0x9E, + }, + .descriptor_block_3 = { + [0] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1280px + * Horizontal Blanking is 370px + */ + [2] = 0x00, [3] = 0x72, [4] = 0x51, + + /* Vertical Addressable Video is 720 lines + * Vertical Blanking is 30 lines + */ + [5] = 0xD0, [6] = 0x1E, [7] = 0x20, + + [8] = 110u, /* Horizontal Front Porch in pixels */ + [9] = 40u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 0x55u, /* Vertical Front Porch is 5 lines */ + [11] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + + /* Horizontal Addressable Image Size is 1039mm + * Vertical Addressable Image Size is 584mm + */ + [12] = 0x0F, [13] = 0x48, [14] = 0x42, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* Timing is Non-Interlaced Video, + * Stereo Video is not supported, + * Digital separate syncs are requires. + */ + [17] = 0x1E, + }, + .descriptor_block_4 = { + /* Display Product Name Block Tag */ + [0] = 0, [1] = 0, [2] = 0, [3] = 0xFC, [4] = 0, + + /* Product name */ + [5] = 'A', + [6] = 'B', + [7] = 'C', + [8] = ' ', + [9] = 'L', + [10] = 'C', + [11] = 'D', + [12] = '4', + [13] = '7', + [14] = 'w', + [15] = '\n', + [16] = ' ', + [17] = ' ', + }, + .extension_flag = 0x0, /* No extensions */ + }; + + edid_raw_calc_checksum(&raw); + + unsigned char ext[128] = { + [0] = 0x02, /* CEA 861 Extension Block Tag Code */ + [1] = 0x03, /* CEA 861 Block Version */ + + [2] = 0x18, /* Detail Timing Descriptors start 0x18 bytes from here */ + + /* Underscan is not supported + * Basic Audio is supported + * YCbCr 4:4:4 & YCbCr 4:2:2 are supported + * Number of native formats: 2 + */ + [3] = 0x72, + + /* Video Data Block Tag Code is 2 + * Number of Short Video Descriptor Bytes i 7 + */ + [4] = 0x47, + + /* 1920x1080p 59.94/60 Hz 16 : 9 AR (CEA Format #16) + * is a supported Native Format. */ + [5] = 0x90, + + /* 1920x1080i 59.94/60 Hz 16 : 9 AR (CEA Format #5) + * is a supported Native Format. */ + [6] = 0x85, + + /* 1280x720p 59.94/60 Hz 16 : 9 AR (CEA Format #4) is a supported format. */ + [7] = 0x04, + + /* 720x480p 59.94/60 Hz 16 : 9 AR (CEA Format #3) is a supported format. */ + [8] = 0x03, + + /* 720x480p 59.94/60 Hz 4 : 3 AR (CEA Format #2) is a supported format. */ + [9] = 0x02, + + /* 720x480i 59.94/60 Hz 16 : 9 AR (CEA Format #7) is a supported format. */ + [10] = 0x07, + + /* 720x480i 59.94/60 Hz 4 : 3 AR (CEA Format #6) is a supported format. */ + [11] = 0x06, + + /* Audio Data Block Tag Code is 1. + * Number of Short Audio Descriptor Bytes is 3. + */ + [12] = 0x23, + + /* Audio Format Tag Code is 1 --- LPCM is supported. + * Maximum number of audio channels is 2 + */ + [13] = 0x09, + + /* Supported Sampling Frequencies include: 48kHz; 44.1kHz & 32kHz. */ + [14] = 0x07, + + /* Supported Sampling Bit Rates include: 24 bit; 20 bit & 16 bit. */ + [15] = 0x07, + + /* Speaker Allocation Block Tag Code is 4. + * Number of Speaker Allocation + * Descriptor Bytes is 3. + */ + [16] = 0x83, + + /* Speaker Allocation is Front-Left & Front-Right */ + [17] = 0x01, + + /* Reserved */ + [18 ... 19] = 0, + + /* Vendor Specific Data Block Tag Code is 3. + * Number of Vendor Specific Data Bytes is 5. + */ + [20] = 0x65, + + /* 24bit IEEE registration Identifier is 0x000C03 */ + [21] = 0x03, [22] = 0x0C, [23] = 0x00, + + /* Vendor Specific Data is 0x10000 */ + [24] = 0x01, [25] = 0x00, + + /* Descriptor Block 5 [18 Bytes] */ + + [26] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, + [27] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 720px. + * Horizontal Blanking is 138 px. + */ + [28] = 0xD0, [29] = 0x8A, [30] = 0x20, + + /* Vertical Addressable Video is 480 lines. + * Vertical Blanking is 45 lines. + */ + [31] = 0xE0, [32] = 0x2D, [33] = 0x10, + + [34] = 16u, /* Horizontal Front Porch in pixels */ + [35] = 62u, /* Horizontal Sync Pulse Width in pixels */ + [36] = 0x96, /* Vertical Front Porch is 9 lines */ + [37] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + + /* Displayed Image Aspect Ratio is 16:9 */ + [38] = 16u, [39] = 9u, [40] = 0u, + + /* Horizontal and Vertical Border Size is 0 px */ + [41] = 0u, [42] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [43] = 0x18, + + /* Descriptor Block 6 [18 Bytes] */ + + [44] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, + [45] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 720px. + * Horizontal Blanking is 138 px. + */ + [46] = 0xD0, [47] = 0x8A, [48] = 0x20, + + /* Vertical Addressable Video is 480 lines. + * Vertical Blanking is 45 lines. + */ + [49] = 0xE0, [50] = 0x2D, [51] = 0x10, + + [52] = 16u, /* Horizontal Front Porch in pixels */ + [53] = 62u, /* Horizontal Sync Pulse Width in pixels */ + [54] = 0x96, /* Vertical Front Porch is 9 lines */ + [55] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + + /* Displayed Image Aspect Ratio is 4:3 */ + [56] = 4u, [57] = 3u, [58] = 0u, + + /* Horizontal and Vertical Border Size is 0 px */ + [59] = 0u, [60] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [61] = 0x18, + + /* Descriptor Block 7 [18 Bytes] */ + + [62] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, + [63] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1440px. + * Horizontal Blanking is 276 px. + */ + [64] = 0xA0, [65] = 0x14, [66] = 0x51, + + /* Vertical Addressable Video is 240 lines. + * Vertical Blanking is 23 lines. + */ + [67] = 0xF0, [68] = 0x16, [69] = 0x00, + + [70] = 38u, /* Horizontal Front Porch in pixels */ + [71] = 124u, /* Horizontal Sync Pulse Width in pixels */ + [72] = 0x43, /* Vertical Front Porch is 9 lines */ + [73] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + + /* Displayed Image Aspect Ratio is 16:9 */ + [74] = 16u, [75] = 9u, [76] = 0u, + + /* Horizontal and Vertical Border Size is 0 px */ + [77] = 0u, [78] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [79] = 0x98, + + /* Descriptor Block 8 [18 Bytes] */ + + [80] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, + [81] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1440px. + * Horizontal Blanking is 276 px. + */ + [82] = 0xA0, [83] = 0x14, [84] = 0x51, + + /* Vertical Addressable Video is 240 lines. + * Vertical Blanking is 23 lines. + */ + [85] = 0xF0, [86] = 0x16, [87] = 0x00, + + [88] = 38u, /* Horizontal Front Porch in pixels */ + [89] = 124u, /* Horizontal Sync Pulse Width in pixels */ + [90] = 0x43, /* Vertical Front Porch is 9 lines */ + [91] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + + /* Displayed Image Aspect Ratio is 4:3 */ + [92] = 4u, [93] = 3u, [94] = 0u, + + /* Horizontal and Vertical Border Size is 0 px */ + [95] = 0u, [96] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [97] = 0x98, + + [99 ... 126] = 0 + }; + + ext[127] = get_raw_edid_checksum(ext); + + *state = malloc(sizeof(struct test_state)); + + struct test_state ts = { + .data_size = sizeof(raw) + sizeof(ext), + .data = malloc(sizeof(raw) + sizeof(ext)) + }; + + memcpy(ts.data, &raw, sizeof(raw)); + memcpy(ts.data + sizeof(raw), &ext[0], sizeof(ext)); + + memcpy(*state, &ts, sizeof(ts)); + + return 0; +} + +/* Test decoding of EDID frame with one extension. + */ +static void test_decode_edid_dtv_frame_with_extension(void **state) +{ + struct edid out; + struct test_state *ts = *state; + + /* In real-life situations frames often are not 100% conformant, + * but are at least correct when it comes to key data fields. + */ + assert_int_equal(EDID_CONFORMANT, + decode_edid((unsigned char *)ts->data, ts->data_size, &out)); + + assert_int_equal(32, out.framebuffer_bits_per_pixel); + assert_int_equal(8, out.panel_bits_per_color); + assert_int_equal(24, out.panel_bits_per_pixel); + assert_int_equal(0, out.link_clock); + assert_int_equal(1920, out.x_resolution); + assert_int_equal(1080, out.y_resolution); + assert_int_equal(7680, out.bytes_per_line); + assert_int_equal(1, out.hdmi_monitor_detected); + assert_int_equal(0, strnlen(out.ascii_string, ARRAY_SIZE(out.ascii_string))); + assert_string_equal(out.manufacturer_name, EDID_MANUFACTURER_NAME); + + /* Mode */ + assert_null(out.mode.name); + assert_int_equal(148500, out.mode.pixel_clock); + assert_int_equal(1, out.mode.lvds_dual_channel); + assert_int_equal(0, out.mode.refresh); + assert_int_equal(1920, out.mode.ha); + assert_int_equal(280, out.mode.hbl); + assert_int_equal(88, out.mode.hso); + assert_int_equal(44, out.mode.hspw); + assert_int_equal(0, out.mode.hborder); + assert_int_equal(1080, out.mode.va); + assert_int_equal(45, out.mode.vbl); + assert_int_equal(16, out.mode.vso); + assert_int_equal(0, out.mode.vborder); + assert_int_equal(43, out.mode.phsync); + assert_int_equal(43, out.mode.pvsync); + assert_int_equal(0, out.mode.x_mm); + assert_int_equal(0, out.mode.y_mm); + + assert_int_equal(1, out.mode_is_supported[EDID_MODE_640x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_720x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1280x720_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1920x1080_60Hz]); +} + + +/* Test decoding of EDID frame with one extension. Tested frame is modified + * example of base EDID frame with CEA861 extension for IT/DTV Display from + * VESA E-EDID Standard Release A2. + */ +static int setup_decode_edid_it_dtv_frame_with_extension(void **state) +{ + struct edid_raw raw = { + EDID_RAW_DEFAULT_PARAMS, + .video_input_type = EDID_DIGITAL_VSI + | EDID_INTERFACE_HDMI_A + | EDID_COLOR_BIT_DEPTH_8B, + .horizontal_size = 121, /* Aspect ratio 16:9 in landscape */ + .vertical_size = 68, /* Landscape flag */ + .display_gamma = 120, /* 220% */ + .supported_features = EDID_STANDBY_MODE(0) + | EDID_SUSPEND_MODE(0) + | EDID_ACTIVE_OFF(0) + | EDID_COLOR_FORMAT_RGB444_YCRCB422_YCRCB422 + | EDID_SRGB_SUPPORTED(1) + | EDID_PREFERRED_TIMING_EXTENDED_INFO + | EDID_DISPLAY_FREQUENCY_NON_CONTINUOUS, + .established_supported_timings = { + [0] = EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz + | EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz + | EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz + | EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz, + [1] = EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz + | EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz + | EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz + | EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz, + }, + .manufacturers_reserved_timing = EDID_MANUFACTURERS_TIMINGS_1152x870_75Hz, + .standard_timings_supported = { + [0] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [1] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(85), + + [2] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [3] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(60), + + [4] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [5] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85), + + [6] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [7] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(60), + + [8] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1024), + [9] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85), + + [10] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(848), + [11] = EDID_ASPECT_RATIO_16_9 | EDID_FIELD_REFRESH_RATE(60), + + [12] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(800), + [13] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(60), + + [14] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(640), + [15] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(60), + }, + .descriptor_block_1 = { + [0] = EDID_PIXEL_CLOCK(85500000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(85500000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1360px + * Horizontal Blanking is 432px + */ + [2] = 0x50, [3] = 0xB0, [4] = 0x51, + + /* Vertical Addressable Video is 768 lines + * Vertical Blanking is 27 lines + */ + [5] = 0x00, [6] = 0x1B, [7] = 0x30, + + [8] = 64u, /* Horizontal Front Porch in pixels */ + [9] = 112u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 0x36, /* Vertical Front Porch is 3 lines */ + [11] = 0u, /* Vertical Sync Pulse Width is 6 lines */ + + /* Horizontal Addressable Image Size is 1214mm + * Vertical Addressable Image Size is 683mm + */ + [12] = 0xBE, [13] = 0xAB, [14] = 0x42, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* Timing is Non-Interlaced Video, + * Stereo Video is not supported, + * Digital separate and syncs are requires. + */ + [17] = 0x1E, + }, + .descriptor_block_2 = { + [0] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1280px + * Horizontal Blanking is 370px + */ + [2] = 0x00, [3] = 0x72, [4] = 0x51, + + /* Vertical Addressable Video is 720 lines + * Vertical Blanking is 30 lines + */ + [5] = 0xD0, [6] = 0x1E, [7] = 0x20, + + [8] = 110u, /* Horizontal Front Porch in pixels */ + [9] = 40u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 0x55, /* Vertical Front Porch is 5 lines */ + [11] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + + /* Horizontal Addressable Image Size is 1214mm + * Vertical Addressable Image Size is 683mm + */ + [12] = 0xBE, [13] = 0xAB, [14] = 0x42, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* Timing is Non-Interlaced Video, + * Stereo Video is not supported, + * Digital separate and syncs are requires. + */ + [17] = 0x1E, + }, + .descriptor_block_3 = { + /* Established timings III Block Tag */ + [0 ... 2] = 0u, [3] = 0xF7, [4] = 0u, + + /* + * VESA DMT Standard Version #10 + */ + [5] = 10u, + + /* 640x350@85Hz, + * 640x400@85Hz, + * 720x400@85Hz, + * 640x480@85Hz, + * 800x600@85Hz, + * 1024x768@85Hz, + * 1152x864@75Hz are supported. + */ + [6] = 0x7F, + + /* 1280x960@60Hz, + * 1280x960@85Hz, + * 1280x1024@60Hz, + * 1280x1024@85Hz + */ + [7] = 0x0F, + + /* 1400x1050@60Hz (Normal Blanking), + * 1400x1050@75Hz are supported. + */ + [8] = 0x03, + + /* 1400x1050@85Hz, + * 1600x1200@60Hz, + * 1600x1200@65Hz, + * 1600x1200@70Hz are supported. + */ + [9] = 0x87, + + /* 1600x1200@75Hz, + * 1600x1200@85Hz are supported. + */ + [10] = 0xC0, + + /* 1920 PC Timings are not supported. */ + [11] = 0u, + + /* Reserved */ + [12 ... 17] = 0, + }, + .descriptor_block_4 = { + /* Display Product Name Block Tag */ + [0] = 0, [1] = 0, [2] = 0, [3] = 0xFC, [4] = 0, + + /* Product name */ + [5] = 'A', + [6] = 'B', + [7] = 'C', + [8] = ' ', + [9] = 'P', + [10] = 'L', + [11] = 'A', + [12] = '5', + [13] = '5', + [14] = '\n', + [15] = ' ', + [16] = ' ', + [17] = ' ', + }, + .extension_flag = 0x0, /* No extensions */ + }; + + edid_raw_calc_checksum(&raw); + + unsigned char ext[128] = { + [0] = 0x02, /* CEA 861 Extension Block Tag Code */ + [1] = 0x03, /* CEA 861 Block Version */ + [2] = 0x17, /* Detail Timing Descriptors start 0x17 bytesfrom here */ + + /* Underscan is supported + * Basic Audio is supported + * YCbCr 4:4:4 & YCbCr 4:2:2 are supported + * Number of native formats: 0 + */ + [3] = 0xF0, + + /* Video Data Block Tag Code is 2 + * Number of Short Video Descriptor Bytes i 6 + */ + [4] = 0x46, + + /* 1920x1080i 59.94/60 Hz 16 : 9 AR (CEA Format #5) is a supported format. */ + [5] = 0x05, + + /* 1280x720p 59.94/60 Hz 16 : 9 AR (CEA Format #4) is a supported format. */ + [6] = 0x04, + + /* 720x480p 59.94/60 Hz 16 : 9 AR (CEA Format #3) is a supported format. */ + [7] = 0x03, + + /* 720x480p 59.94/60 Hz 4 : 3 AR (CEA Format #2) is a supported format. */ + [8] = 0x02, + + /* 720x480i 59.94/60 Hz 16 : 9 AR (CEA Format #7) is a supported format. */ + [9] = 0x07, + + /* 720x480i 59.94/60 Hz 4 : 3 AR (CEA Format #6) is a supported format. */ + [10] = 0x06, + + /* Audio Data Block Tag Code is 1. + * Number of Short Audio Descriptor Bytes is 3. + */ + [11] = 0x23, + + /* Audio Format Tag Code is 1 --- LPCM is supported. + * Maximum number of audio channels is 2 + */ + [12] = 0x09, + + /* Supported Sampling Frequencies include: 48kHz; 44.1kHz & 32kHz. */ + [13] = 0x07, + + /* Supported Sampling Bit Rates include: 24 bit; 20 bit & 16 bit. */ + [14] = 0x07, + + /* Speaker Allocation Block Tag Code is 4. + * Number of Speaker Allocation + * Descriptor Bytes is 3. + */ + [15] = 0x83, + + /* Speaker Allocation is Front-Left & Front-Right */ + [16] = 0x01, + + /* Reserved */ + [17 ... 18] = 0, + + /* Vendor Specific Data Block Tag Code is 3. + * Number of Vendor Specific Data Bytes is 5. + */ + [19] = 0x65, + + /* 24bit IEEE registration Identifier is 0x000C03 */ + [20] = 0x03, [21] = 0x0C, [22] = 0x00, + + /* Vendor Specific Data is 0x10000 */ + [23] = 0x01, [24] = 0x00, + + /* Descriptor Block 5 [18 Bytes] */ + + [25] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, + [26] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1920px. + * Horizontal Blanking is 280px. + */ + [27] = 0x80, [28] = 0x18, [29] = 0x71, + + /* Vertical Addressable Video is 540 lines. + * Vertical Blanking is 22 lines. + */ + [30] = 0x1C, [31] = 0x16, [32] = 0x20, + + [33] = 88u, /* Horizontal Front Porch in pixels */ + [34] = 44u, /* Horizontal Sync Pulse Width in pixels */ + [35] = 0x25, /* Vertical Front Porch is 2 lines */ + [36] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + + /* Image size: 1039mm x 584mm */ + [37] = 0x0F, [38] = 0x48, [39] = 0x42, + + /* Horizontal and Vertical Border Size is 0 px */ + [40] = 0u, [41] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [42] = 0x9E, + + /* Descriptor Block 6 [18 Bytes] */ + + [43] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, + [44] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1280px. + * Horizontal Blanking is 370 px. + */ + [45] = 0x00, [46] = 0x72, [47] = 0x51, + + /* Vertical Addressable Video is 720 lines. + * Vertical Blanking is 30 lines. + */ + [48] = 0xD0, [49] = 0x1E, [50] = 0x20, + + [51] = 110u, /* Horizontal Front Porch in pixels */ + [52] = 40u, /* Horizontal Sync Pulse Width in pixels */ + [53] = 0x55, /* Vertical Front Porch is 5 lines */ + [54] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + + /* Image size: 1039mm x 584mm */ + [55] = 0x0F, [56] = 0x48, [57] = 0x42, + + /* Horizontal and Vertical Border Size is 0 px */ + [58] = 0u, [59] = 0u, + + /* Timing is Non-Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [60] = 0x1E, + + /* Descriptor Block 7 [18 Bytes] */ + + [61] = EDID_PIXEL_CLOCK(27000000u) & 0xFF, + [62] = (EDID_PIXEL_CLOCK(27000000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1440px. + * Horizontal Blanking is 276 px. + */ + [63] = 0xA0, [64] = 0x14, [65] = 0x51, + + /* Vertical Addressable Video is 240 lines. + * Vertical Blanking is 23 lines. + */ + [66] = 0xF0, [67] = 0x16, [68] = 0x00, + + [69] = 38u, /* Horizontal Front Porch in pixels */ + [70] = 124u, /* Horizontal Sync Pulse Width in pixels */ + [71] = 0x43, /* Vertical Front Porch is 4 lines */ + [72] = 0x00, /* Vertical Sync Pulse Width is 3 lines */ + + /* Image size: 1039mm x 584mm */ + [73] = 0x0F, [74] = 0x48, [75] = 0x42, + + /* Horizontal and Vertical Border Size is 0 px */ + [76] = 0u, [77] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [78] = 0x18, + + /* Descriptor Block 8 [18 Bytes] */ + + [79] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, + [80] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1440px. + * Horizontal Blanking is 276 px. + */ + [81] = 0xA0, [82] = 0x14, [83] = 0x51, + + /* Vertical Addressable Video is 240 lines. + * Vertical Blanking is 23 lines. + */ + [84] = 0xF0, [85] = 0x16, [86] = 0x00, + + [87] = 38u, /* Horizontal Front Porch in pixels */ + [88] = 124u, /* Horizontal Sync Pulse Width in pixels */ + [89] = 0x43, /* Vertical Front Porch is 4 lines */ + [90] = 0x00, /* Vertical Sync Pulse Width is 3 lines */ + + /* Image size: 1039mm x 584mm */ + [91] = 0x0F, [92] = 0x48, [93] = 0x42, + + /* Horizontal and Vertical Border Size is 0 px */ + [94] = 0u, [95] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [96] = 0x98, + + [97 ... 126] = 0, + }; + + ext[127] = get_raw_edid_checksum(ext); + + *state = malloc(sizeof(struct test_state)); + + struct test_state ts = { + .data_size = sizeof(raw) + sizeof(ext), + .data = malloc(sizeof(raw) + sizeof(ext)) + }; + + memcpy(ts.data, &raw, sizeof(raw)); + memcpy(ts.data + sizeof(raw), &ext[0], sizeof(ext)); + + memcpy(*state, &ts, sizeof(ts)); + + return 0; +} + +static void test_decode_edid_it_dtv_frame_with_extension(void **state) +{ + struct edid out; + struct test_state *ts = *state; + + /* In real-life situations frames often are not 100% conformant, + * but are at least correct when it comes to key data fields. + */ + assert_int_equal(EDID_CONFORMANT, + decode_edid((unsigned char *)ts->data, ts->data_size, &out)); + + assert_int_equal(32, out.framebuffer_bits_per_pixel); + assert_int_equal(8, out.panel_bits_per_color); + assert_int_equal(24, out.panel_bits_per_pixel); + assert_int_equal(0, out.link_clock); + assert_int_equal(1360, out.x_resolution); + assert_int_equal(768, out.y_resolution); + assert_int_equal(5440, out.bytes_per_line); + assert_int_equal(1, out.hdmi_monitor_detected); + assert_int_equal(0, strnlen(out.ascii_string, ARRAY_SIZE(out.ascii_string))); + assert_string_equal(out.manufacturer_name, EDID_MANUFACTURER_NAME); + + /* Mode */ + assert_null(out.mode.name); + assert_int_equal(85500, out.mode.pixel_clock); + assert_int_equal(0, out.mode.lvds_dual_channel); + assert_int_equal(0, out.mode.refresh); + assert_int_equal(1360, out.mode.ha); + assert_int_equal(432, out.mode.hbl); + assert_int_equal(64, out.mode.hso); + assert_int_equal(112, out.mode.hspw); + assert_int_equal(0, out.mode.hborder); + assert_int_equal(768, out.mode.va); + assert_int_equal(27, out.mode.vbl); + assert_int_equal(3, out.mode.vso); + assert_int_equal(0, out.mode.vborder); + assert_int_equal(43, out.mode.phsync); + assert_int_equal(43, out.mode.pvsync); + assert_int_equal(0, out.mode.x_mm); + assert_int_equal(0, out.mode.y_mm); + + assert_int_equal(1, out.mode_is_supported[EDID_MODE_640x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_720x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1280x720_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1920x1080_60Hz]); +} + +static int teardown_edid_test(void **state) +{ + struct test_state *ts; + + if (*state == NULL) + return 0; + + ts = (struct test_state *)*state; + + free(ts->data); + free(ts); + + return 0; +} + +static void test_edid_set_framebuffer_bits_per_pixel(void **state) +{ + struct edid out; + struct test_state *ts = *state; + + decode_edid((unsigned char *)ts->data, ts->data_size, &out); + + edid_set_framebuffer_bits_per_pixel(&out, 16, 2); + + assert_int_equal(16, out.framebuffer_bits_per_pixel); + assert_int_equal(out.mode.ha * 2, out.bytes_per_line); + assert_int_equal(out.bytes_per_line / (16 / 8), out.x_resolution); + assert_int_equal(out.mode.va, out.y_resolution); + + edid_set_framebuffer_bits_per_pixel(&out, 24, 4); + + assert_int_equal(24, out.framebuffer_bits_per_pixel); + assert_int_equal(out.mode.ha * 3, out.bytes_per_line); + assert_int_equal(out.bytes_per_line / (24 / 8), out.x_resolution); + assert_int_equal(out.mode.va, out.y_resolution); + + edid_set_framebuffer_bits_per_pixel(&out, 32, 4); + + assert_int_equal(32, out.framebuffer_bits_per_pixel); + assert_int_equal(out.mode.ha * 4, out.bytes_per_line); + assert_int_equal(out.bytes_per_line / (32 / 8), out.x_resolution); + assert_int_equal(out.mode.va, out.y_resolution); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_decode_edid_no_edid), + cmocka_unit_test(test_decode_edid_invalid_header), + cmocka_unit_test_setup_teardown(test_decode_edid_basic_frame, + setup_decode_edid_basic_frame, + teardown_edid_test), + cmocka_unit_test_setup_teardown(test_decode_edid_dtv_frame_with_extension, + setup_decode_edid_dtv_frame_with_extension, + teardown_edid_test), + cmocka_unit_test_setup_teardown(test_decode_edid_it_dtv_frame_with_extension, + setup_decode_edid_it_dtv_frame_with_extension, + teardown_edid_test), + cmocka_unit_test_setup_teardown(test_edid_set_framebuffer_bits_per_pixel, + setup_decode_edid_basic_frame, + teardown_edid_test), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} + diff --git a/tests/stubs/console.c b/tests/stubs/console.c index b6a75831b5..0f1dc24725 100644 --- a/tests/stubs/console.c +++ b/tests/stubs/console.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include int do_printk(int msg_level, const char *fmt, ...) { @@ -11,3 +13,8 @@ int do_vprintk(int msg_level, const char *fmt, va_list args) { return 0; } + +int console_log_level(int msg_level) +{ + return 0; +} From af0d516bfa5497e84d18bdafbdec5f98ce4999a0 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 4 Nov 2020 17:05:35 -0700 Subject: [PATCH 181/262] soc/intel/jasperlake: Log PM event from an internal device Add support to check for the Power Management (PM) Status bit for various internal devices like USB, CNVi etc. and log them into the event log for debugging purposes. BUG=b:172279037 TEST=Build and boot to OS in Drawlat. Ensure that the wake up event is logged into the event log for one of the internal devices eg. USB bluetooth. 8 | 2020-11-05 15:04:16 | S0ix Enter 9 | 2020-11-05 15:04:29 | S0ix Exit 10 | 2020-11-05 15:04:29 | Wake Source | PME - XHCI (USB 2.0 port) | 8 11 | 2020-11-05 15:04:29 | Wake Source | GPE # | 109 12 | 2020-11-05 15:05:08 | S0ix Enter 13 | 2020-11-05 15:05:14 | S0ix Exit 14 | 2020-11-05 15:05:14 | Wake Source | PME - XHCI (USB 2.0 port) | 8 15 | 2020-11-05 15:05:14 | Wake Source | GPE # | 109 Change-Id: I9f43675b698bf310f6b98b5e775d1259607abbcd Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47226 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/Kconfig | 1 + src/soc/intel/jasperlake/Makefile.inc | 2 + src/soc/intel/jasperlake/elog.c | 67 ++++++++++++++++++++++++--- src/soc/intel/jasperlake/xhci.c | 20 ++++++++ 4 files changed, 84 insertions(+), 6 deletions(-) create mode 100644 src/soc/intel/jasperlake/xhci.c diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index e84add0644..294f19f87b 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -52,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 209d8a2661..677b5f3c52 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += sd.c ramstage-y += me.c +ramstage-y += xhci.c smm-y += gpio.c smm-y += p2sb.c @@ -52,6 +53,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c smm-y += elog.c +smm-y += xhci.c verstage-y += gpio.c diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index 0546bb0215..5d3c69e3fe 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -5,11 +5,17 @@ #include #include #include +#include #include #include #include #include +struct pme_map { + pci_devfn_t devfn; + unsigned int wake_source; +}; + static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -25,10 +31,6 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) static void pch_log_rp_wake_source(void) { size_t i; - struct pme_map { - pci_devfn_t devfn; - unsigned int wake_source; - }; const struct pme_map pme_map[] = { { PCH_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 }, @@ -55,6 +57,59 @@ static void pch_log_rp_wake_source(void) } } +static void pch_log_add_elog_event(const struct pme_map *ipme_map) +{ + /* + * If wake source is XHCI, check for detailed wake source events on + * USB2/3 ports. + */ + if ((ipme_map->devfn == PCH_DEVFN_XHCI) && + pch_xhci_update_wake_event(soc_get_xhci_usb_info())) + return; + + elog_add_event_wake(ipme_map->wake_source, 0); +} + +static void pch_log_pme_internal_wake_source(void) +{ + size_t i; + bool dev_found = false; + + const struct pme_map ipme_map[] = { + { PCH_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA }, + { PCH_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE }, + { PCH_DEVFN_SATA, ELOG_WAKE_SOURCE_PME_SATA }, + { PCH_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE }, + { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCH_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI }, + { PCH_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI }, + }; + + for (i = 0; i < ARRAY_SIZE(ipme_map); i++) { + const struct device *dev = pcidev_path_on_root(ipme_map[i].devfn); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) { + pch_log_add_elog_event(&ipme_map[i]); + dev_found = true; + } + } + + /* + * If device is still not found, but the wake source is internal PME, + * try probing XHCI ports to see if any of the USB2/3 ports indicate + * that it was the wake source. This path would be taken in case of GSMI + * logging with S0ix where the pci_pm_resume_noirq runs and clears the + * PME_STS_BIT in controller register. + */ + if (!dev_found) + dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info()); + + if (!dev_found) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -73,9 +128,9 @@ static void pch_log_wake_source(struct chipset_power_state *ps) if (ps->gpe0_sts[GPE_STD] & PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); - /* Internal PME (TODO: determine wake device) */ + /* Internal PME */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + pch_log_pme_internal_wake_source(); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) diff --git a/src/soc/intel/jasperlake/xhci.c b/src/soc/intel/jasperlake/xhci.c new file mode 100644 index 0000000000..424751e9d8 --- /dev/null +++ b/src/soc/intel/jasperlake/xhci.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x500 +#define XHCI_USB2_PORT_NUM 8 +#define XHCI_USB3_PORT_NUM 6 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} From fa9e8f9cfc10a5f95d6b74a88e93cbd89c9faa77 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 4 Nov 2020 22:22:46 -0700 Subject: [PATCH 182/262] soc/intel/tigerlake: Log PM event from an internal device Add support to check for the Power Management (PM) Status bit for various internal devices like USB, CNVi etc. and log them into the event log for debugging purposes. BUG=b:172279037 BRANCH=volteer Change-Id: Ib3d0bf33d780444f8240f749a3319212c985950d Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47227 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/tigerlake/Kconfig | 1 + src/soc/intel/tigerlake/Makefile.inc | 2 + src/soc/intel/tigerlake/elog.c | 67 +++++++++++++++++++++++++--- src/soc/intel/tigerlake/xhci.c | 20 +++++++++ 4 files changed, 84 insertions(+), 6 deletions(-) create mode 100644 src/soc/intel/tigerlake/xhci.c diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index b9a5b60e17..79a4c6495b 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -55,6 +55,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_BLOCK_USB4_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index a25d0a4ee0..3103d60d3b 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += smmrelocate.c ramstage-y += soundwire.c ramstage-y += systemagent.c ramstage-y += me.c +ramstage-y += xhci.c smm-y += gpio.c smm-y += p2sb.c @@ -51,6 +52,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c smm-y += elog.c +smm-y += xhci.c verstage-y += gpio.c diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index a46afbb24c..88324d63cf 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -5,11 +5,17 @@ #include #include #include +#include #include #include #include #include +struct pme_map { + pci_devfn_t devfn; + unsigned int wake_source; +}; + static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -25,10 +31,6 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) static void pch_log_rp_wake_source(void) { size_t i; - struct pme_map { - pci_devfn_t devfn; - unsigned int wake_source; - }; const struct pme_map pme_map[] = { { PCH_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 }, @@ -55,6 +57,59 @@ static void pch_log_rp_wake_source(void) } } +static void pch_log_add_elog_event(const struct pme_map *ipme_map) +{ + /* + * If wake source is XHCI, check for detailed wake source events on + * USB2/3 ports. + */ + if ((ipme_map->devfn == PCH_DEVFN_XHCI) && + pch_xhci_update_wake_event(soc_get_xhci_usb_info())) + return; + + elog_add_event_wake(ipme_map->wake_source, 0); +} + +static void pch_log_pme_internal_wake_source(void) +{ + size_t i; + bool dev_found = false; + + const struct pme_map ipme_map[] = { + { PCH_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA }, + { PCH_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE }, + { PCH_DEVFN_SATA, ELOG_WAKE_SOURCE_PME_SATA }, + { PCH_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE }, + { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCH_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI }, + { PCH_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI }, + }; + + for (i = 0; i < ARRAY_SIZE(ipme_map); i++) { + const struct device *dev = pcidev_path_on_root(ipme_map[i].devfn); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) { + pch_log_add_elog_event(&ipme_map[i]); + dev_found = true; + } + } + + /* + * If device is still not found, but the wake source is internal PME, + * try probing XHCI ports to see if any of the USB2/3 ports indicate + * that it was the wake source. This path would be taken in case of GSMI + * logging with S0ix where the pci_pm_resume_noirq runs and clears the + * PME_STS_BIT in controller register. + */ + if (!dev_found) + dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info()); + + if (!dev_found) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -73,9 +128,9 @@ static void pch_log_wake_source(struct chipset_power_state *ps) if (ps->gpe0_sts[GPE_STD] & PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); - /* Internal PME (TODO: determine wake device) */ + /* Internal PME */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + pch_log_pme_internal_wake_source(); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) diff --git a/src/soc/intel/tigerlake/xhci.c b/src/soc/intel/tigerlake/xhci.c new file mode 100644 index 0000000000..18bb129983 --- /dev/null +++ b/src/soc/intel/tigerlake/xhci.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x520 +#define XHCI_USB2_PORT_NUM 10 +#define XHCI_USB3_PORT_NUM 4 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} From b92df578b48911893a475b6f47ddfc574f63eac7 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Mon, 9 Nov 2020 14:51:17 +0100 Subject: [PATCH 183/262] mb/asus/f2a85-m: Disable `HUDSON_LEGACY_FREE` for working serial console The Asus F2A85-M, F2A85-M LE and F2A85-M PRO all have a Super I/O, and therefore have legacy devices like a serial console. Selecting `HUDSON_LEGACY_FREE` currently disable the serial console during bootup in romstage, which is undesired. So, deselect the symbol by default. TEST=Boot Asus F2A85-M PRO and verify serial console is *not* disabled during romstage. Change-Id: Ia6588c0d4b2c24c7cb9da04805d13274c8ae295e Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/47363 Reviewed-by: Felix Held Reviewed-by: Mike Banon Tested-by: build bot (Jenkins) --- src/mainboard/asus/f2a85-m/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index 27d5517b9f..326fedd9b6 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -84,7 +84,7 @@ config VGA_BIOS_ID config HUDSON_LEGACY_FREE bool - default y + default n config POST_IO bool From 8084b3856852f3fb3905e0fe4957b08518095d38 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 30 Oct 2020 10:56:31 +0100 Subject: [PATCH 184/262] sb/intel/lynxpoint/sata: Always use AHCI mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The other two modes are not used by any mainboard, and the code seems to be copied from older southbridges. As the code looks incorrect, drop it. Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47022 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/mainboard/asrock/b85m_pro4/devicetree.cb | 1 - src/mainboard/asrock/h81m-hds/devicetree.cb | 1 - src/mainboard/google/beltino/devicetree.cb | 2 - src/mainboard/google/slippy/devicetree.cb | 2 - .../intel/baskingridge/devicetree.cb | 2 - src/mainboard/lenovo/t440p/devicetree.cb | 1 - .../supermicro/x10slm-f/devicetree.cb | 1 - src/southbridge/intel/lynxpoint/chip.h | 4 +- src/southbridge/intel/lynxpoint/sata.c | 242 ++++++------------ 9 files changed, 79 insertions(+), 177 deletions(-) diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index d257f18bc6..024d1f0e1f 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -27,7 +27,6 @@ chip northbridge/intel/haswell chip southbridge/intel/lynxpoint register "gen1_dec" = "0x000c0291" # Super I/O HWM - register "sata_ahci" = "1" register "sata_port_map" = "0x3f" device pci 14.0 on end # xHCI controller diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 8f368961de..45119f9476 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -35,7 +35,6 @@ chip northbridge/intel/haswell end chip southbridge/intel/lynxpoint - register "sata_ahci" = "1" register "sata_port_map" = "0x33" register "gen1_dec" = "0x00000295" # Super I/O HWM diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 8fdfbd79a0..176fced5ed 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -45,8 +45,6 @@ chip northbridge/intel/haswell register "gpe0_en_3" = "0x00000000" register "gpe0_en_4" = "0x00000000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sata_devslp_disable" = "0x1" diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 200721b8ef..a6fab83a5b 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -52,8 +52,6 @@ chip northbridge/intel/haswell register "gpe0_en_3" = "0x00000000" register "gpe0_en_4" = "0x00000000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sio_acpi_mode" = "1" diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 6345090c7a..784c926d5f 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -41,8 +41,6 @@ chip northbridge/intel/haswell register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x4000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" # SuperIO range is 0x700-0x73f diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 8c356816ab..9359bb4e5d 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -37,7 +37,6 @@ chip northbridge/intel/haswell register "gen4_dec" = "0x000c06a1" register "gpi13_routing" = "2" register "gpi1_routing" = "2" - register "sata_ahci" = "1" # 0(HDD), 1(M.2), 5(ODD) register "sata_port_map" = "0x23" device pci 14.0 on end # xHCI Controller diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index ffcc56d15c..6d64a90221 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -26,7 +26,6 @@ chip northbridge/intel/haswell device pci 03.0 off end # Mini-HD audio chip southbridge/intel/lynxpoint - register "sata_ahci" = "1" register "sata_port_map" = "0x3f" register "gen1_dec" = "0x00000295" # Super I/O HWM diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index 40d0460419..89bbb1ce0c 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -38,9 +38,7 @@ struct southbridge_intel_lynxpoint_config { uint32_t gpe0_en_4; uint32_t alt_gp_smi_en; - /* IDE configuration */ - uint32_t ide_legacy_combined; - uint32_t sata_ahci; + /* SATA configuration */ uint8_t sata_port_map; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx; diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index e1a2fa5a57..c9c7f2cadb 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -29,6 +29,9 @@ static void sata_init(struct device *dev) { u32 reg32; u16 reg16; + + u32 *abar; + /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -44,170 +47,87 @@ static void sata_init(struct device *dev) /* Enable memory space decoding for ABAR */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); + printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0); + /* Set Interrupt Line */ + /* Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, INTR_LN, 0x0a); - /* And without AHCI BAR no memory decoding */ - pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | + IDE_PPE0 | IDE_IE0 | IDE_TIME0); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config8(dev, 0x09, 0x80); + /* Sync DMA */ + pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); + pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); + /* Set IDE I/O Configuration */ + reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + pci_write_config32(dev, IDE_CONFIG, reg32); - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); + /* for AHCI, Port Enable is managed in memory mapped space */ + reg16 = pci_read_config16(dev, 0x92); + reg16 &= ~0x3f; + reg16 |= 0x8000 | config->sata_port_map; + pci_write_config16(dev, 0x92, reg16); + udelay(2); - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); - } else if (config->sata_ahci) { - u32 *abar; - - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); - - /* Set Interrupt Line */ - /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0x0a); - - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* for AHCI, Port Enable is managed in memory mapped space */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= 0x8000 | config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - udelay(2); - - /* Setup register 98h */ - reg32 = pci_read_config16(dev, 0x98); - reg32 |= 1 << 19; /* BWG step 6 */ - reg32 |= 1 << 22; /* BWG step 5 */ - reg32 &= ~(0x3f << 7); - reg32 |= 0x04 << 7; /* BWG step 7 */ - reg32 |= 1 << 20; /* BWG step 8 */ - reg32 &= ~(0x03 << 5); - reg32 |= 1 << 5; /* BWG step 9 */ - reg32 |= 1 << 18; /* BWG step 10 */ - reg32 |= 1 << 29; /* BWG step 11 */ - if (pch_is_lp()) { - reg32 &= ~((1 << 31) | (1 << 30)); - reg32 |= 1 << 23; - reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ - } - pci_write_config32(dev, 0x98, reg32); - - /* Setup register 9Ch: Disable alternate ID and BWG step 12 */ - pci_write_config16(dev, 0x9c, 1 << 5); - - /* SATA Initialization register */ - reg32 = 0x183; - reg32 |= (config->sata_port_map ^ 0x3f) << 24; - reg32 |= (config->sata_devslp_mux & 1) << 15; - pci_write_config32(dev, 0x94, reg32); - - /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS - if (pch_is_lp()) - reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x03, config->sata_port_map); - (void)read32(abar + 0x03); /* Read back 1 */ - (void)read32(abar + 0x03); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended)*/ - reg32 = read32(abar + 0x09); - /* Enable DEVSLP */ - if (pch_is_lp()) { - if (config->sata_devslp_disable) - reg32 &= ~(1 << 3); - else - reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); - } else { - reg32 &= ~0x00000002; - } - write32(abar + 0x09, reg32); - } else { - printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); - - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0); - - /* And without AHCI BAR no memory decoding */ - pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); - - /* - * Native mode capable on both primary and secondary (0xa) - * or'ed with enabled (0x50) = 0xf - * - * FIXME: Does not match the code. - */ - pci_write_config8(dev, 0x09, 0x8f); - - /* Set Interrupt Line */ - /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0xff); - - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_SITRE | IDE_ISP_3_CLOCKS | - IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + /* Setup register 98h */ + reg32 = pci_read_config16(dev, 0x98); + reg32 |= 1 << 19; /* BWG step 6 */ + reg32 |= 1 << 22; /* BWG step 5 */ + reg32 &= ~(0x3f << 7); + reg32 |= 0x04 << 7; /* BWG step 7 */ + reg32 |= 1 << 20; /* BWG step 8 */ + reg32 &= ~(0x03 << 5); + reg32 |= 1 << 5; /* BWG step 9 */ + reg32 |= 1 << 18; /* BWG step 10 */ + reg32 |= 1 << 29; /* BWG step 11 */ + if (pch_is_lp()) { + reg32 &= ~((1 << 31) | (1 << 30)); + reg32 |= 1 << 23; + reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ } + pci_write_config32(dev, 0x98, reg32); + + /* Setup register 9Ch: Disable alternate ID and BWG step 12 */ + pci_write_config16(dev, 0x9c, 1 << 5); + + /* SATA Initialization register */ + reg32 = 0x183; + reg32 |= (config->sata_port_map ^ 0x3f) << 24; + reg32 |= (config->sata_devslp_mux & 1) << 15; + pci_write_config32(dev, 0x94, reg32); + + /* Initialize AHCI memory-mapped space */ + abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "ABAR: %p\n", abar); + /* CAP (HBA Capabilities) : enable power management */ + reg32 = read32(abar + 0x00); + reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS + reg32 &= ~0x00020060; // clear SXS+EMS+PMS + if (pch_is_lp()) + reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY + write32(abar + 0x00, reg32); + /* PI (Ports implemented) */ + write32(abar + 0x03, config->sata_port_map); + (void)read32(abar + 0x03); /* Read back 1 */ + (void)read32(abar + 0x03); /* Read back 2 */ + /* CAP2 (HBA Capabilities Extended)*/ + reg32 = read32(abar + 0x09); + /* Enable DEVSLP */ + if (pch_is_lp()) { + if (config->sata_devslp_disable) + reg32 &= ~(1 << 3); + else + reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); + } else { + reg32 &= ~0x00000002; + } + write32(abar + 0x09, reg32); /* Set Gen3 Transmitter settings if needed */ if (config->sata_port0_gen3_tx) @@ -290,7 +210,6 @@ static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; - u16 map = 0; if (!config) return; @@ -299,12 +218,7 @@ static void sata_enable(struct device *dev) * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) - map = 0x0060; - - map |= (config->sata_port_map ^ 0x3f) << 8; - - pci_write_config16(dev, 0x90, map); + pci_write_config16(dev, 0x90, 0x0060 | (config->sata_port_map ^ 0x3f) << 8); } static struct device_operations sata_ops = { From 2f572dd964db1ca475af38d4b8592001dd22ed9e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 11 Nov 2020 00:24:40 +0100 Subject: [PATCH 185/262] mb/hp/folio_9480m: Drop `sata_ahci` from devtree Commit 8084b38568 (sb/intel/lynxpoint/sata: Always use AHCI mode) dropped the devtree option, but missed this recently-added mainboard. Change-Id: I6ab3a763c0bcd7431193c48e473639589b1a1e1a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47426 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Stefan Reinauer Reviewed-by: Paul Menzel --- src/mainboard/hp/folio_9480m/devicetree.cb | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb index bd81d38197..140aa844f5 100644 --- a/src/mainboard/hp/folio_9480m/devicetree.cb +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -36,7 +36,6 @@ chip northbridge/intel/haswell register "gen2_dec" = "0x000c0101" register "gen4_dec" = "0x000402e9" register "xhci_default" = "1" - register "sata_ahci" = "1" register "sata_port1_gen3_dtle" = "0x6" # SATA(1), M.2(3) register "sata_port_map" = "0xa" From d00af4fbacfafaed18be571719c06f1f84b61599 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 30 Oct 2020 12:56:02 +0100 Subject: [PATCH 186/262] sb/intel/lynxpoint/sata: Simplify RMW operations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce the `sir_unset_and_set_mask` helper and update the one PCI read-modify-write operation that is somehow not reproducible. Change-Id: I30ad6ef8ad97ee0a8dc2297fba5bbbfe24f00f1c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47030 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner --- src/southbridge/intel/lynxpoint/sata.c | 31 +++++++++++--------------- 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index c9c7f2cadb..d8eb2a814b 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -25,10 +25,17 @@ static inline void sir_write(struct device *dev, int idx, u32 value) pci_write_config32(dev, SATA_SIRD, value); } +static inline void sir_unset_and_set_mask(struct device *dev, int idx, u32 unset, u32 set) +{ + pci_write_config32(dev, SATA_SIRI, idx); + + const u32 value = pci_read_config32(dev, SATA_SIRD) & ~unset; + pci_write_config32(dev, SATA_SIRD, value | set); +} + static void sata_init(struct device *dev) { u32 reg32; - u16 reg16; u32 *abar; @@ -69,10 +76,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, IDE_CONFIG, reg32); /* for AHCI, Port Enable is managed in memory mapped space */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= 0x8000 | config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); + pci_update_config16(dev, 0x92, ~0x3f, 0x8000 | config->sata_port_map); udelay(2); /* Setup register 98h */ @@ -173,25 +177,16 @@ static void sata_init(struct device *dev) sir_write(dev, 0x64, 0x883c9001); /* Step 2: SIR 68h[15:0] = 880Ah */ - reg32 = sir_read(dev, 0x68); - reg32 &= 0xffff0000; - reg32 |= 0x880a; - sir_write(dev, 0x68, reg32); + sir_unset_and_set_mask(dev, 0x68, 0xffff, 0x880a); /* Step 3: SIR 60h[3] = 1 */ - reg32 = sir_read(dev, 0x60); - reg32 |= (1 << 3); - sir_write(dev, 0x60, reg32); + sir_unset_and_set_mask(dev, 0x60, 0, 1 << 3); /* Step 4: SIR 60h[0] = 1 */ - reg32 = sir_read(dev, 0x60); - reg32 |= (1 << 0); - sir_write(dev, 0x60, reg32); + sir_unset_and_set_mask(dev, 0x60, 0, 1 << 0); /* Step 5: SIR 60h[1] = 1 */ - reg32 = sir_read(dev, 0x60); - reg32 |= (1 << 1); - sir_write(dev, 0x60, reg32); + sir_unset_and_set_mask(dev, 0x60, 0, 1 << 1); /* Clock Gating */ sir_write(dev, 0x70, 0x3f00bf1f); From 678e401eb8f3fc8124a99fe0d6dbe4e0e5ddfd21 Mon Sep 17 00:00:00 2001 From: Harshit Sharma Date: Fri, 4 Sep 2020 20:12:27 -0700 Subject: [PATCH 187/262] Documentation/releases: Add ASan to 4.13 relnotes Change-Id: I2953729c69dfcfa8b34192b3e1623fdfad87ca3a Signed-off-by: Harshit Sharma Reviewed-on: https://review.coreboot.org/c/coreboot/+/45118 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- Documentation/releases/coreboot-4.13-relnotes.md | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index 8d19067c70..ddbea81c2c 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -49,6 +49,15 @@ the 64K segment to accomodate additional CPUs and in theory allows as many CPU threads as possible limited only by SMRAM space and not by 64K. By default this loader version is disabled. Please see cpu/x86/Kconfig for more info. +### Address Sanitizer + +coreboot now has an in-built Address Sanitizer, a runtime memory debugger +designed to find out-of-bounds access and use-after-scope bugs. It is made +available on all x86 platforms in ramstage and on QEMU i440fx, Intel Apollo +Lake, and Haswell in romstage. Further, it can be enabled in romstage on other +x86 platforms as well. Refer [ASan documentation](../technotes/asan.md) for +more info. + ### Initial support for x86_64 The x86_64 code support has been revived and enabled for qemu. While it started From b0630464d971d37804f674419be5b15c9ab75467 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 9 Sep 2020 19:41:07 +0200 Subject: [PATCH 188/262] util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-LP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I86c7159d9f48560c41efdfe49f162aef00499d13 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45200 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/inteltool/gpio_names/cannonlake_lp.h | 152 +++++++++++----------- 1 file changed, 76 insertions(+), 76 deletions(-) diff --git a/util/inteltool/gpio_names/cannonlake_lp.h b/util/inteltool/gpio_names/cannonlake_lp.h index 0aa69b0101..9d9c66ba47 100644 --- a/util/inteltool/gpio_names/cannonlake_lp.h +++ b/util/inteltool/gpio_names/cannonlake_lp.h @@ -4,31 +4,31 @@ #include "gpio_groups.h" const char *const cannonlake_pch_lp_group_a_names[] = { - "GPP_A0", "RCIN#", "TIME_SYNC1", "n/a", - "GPP_A1", "LAD0", "ESPI_IO0", "n/a", - "GPP_A2", "LAD1", "ESPI_IO1", "n/a", - "GPP_A3", "LAD2", "ESPI_IO2", "n/a", - "GPP_A4", "LAD3", "ESPI_IO3", "n/a", - "GPP_A5", "LFRAME#", "ESPI_CS0#", "n/a", - "GPP_A6", "SERIRQ", "n/a", "n/a", - "GPP_A7", "PIRQA#", "GSPI0_CS1#", "n/a", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "ESPI_CLK", "n/a", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "GSPI1_CS1#", "SD_VDD2_PWR_EN#", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "ESPI_RESET#", "n/a", - "GPP_A15", "SUSACK#", "n/a", "n/a", - "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", - "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", - "GPIO_RSVD_0", "n/a", "n/a", "n/a", + "GPP_A0", "RCIN#", "TIME_SYNC1", "n/a", + "GPP_A1", "LAD0", "ESPI_IO0", "n/a", + "GPP_A2", "LAD1", "ESPI_IO1", "n/a", + "GPP_A3", "LAD2", "ESPI_IO2", "n/a", + "GPP_A4", "LAD3", "ESPI_IO3", "n/a", + "GPP_A5", "LFRAME#", "ESPI_CS0#", "n/a", + "GPP_A6", "SERIRQ", "n/a", "n/a", + "GPP_A7", "PIRQA#", "GSPI0_CS1#", "n/a", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "ESPI_CLK", "n/a", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "GSPI1_CS1#", "SD_VDD2_PWR_EN#", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "ESPI_RESET#", "n/a", + "GPP_A15", "SUSACK#", "n/a", "n/a", + "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", + "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", + "ESPI_CLK_LOOPBK", "ESPI_CLK_LOOPBK", "n/a", "n/a", }; const struct gpio_group cannonlake_pch_lp_group_a = { @@ -39,32 +39,32 @@ const struct gpio_group cannonlake_pch_lp_group_a = { }; const char *const cannonlake_pch_lp_group_b_names[] = { - "GPP_B0", "Reserved", "n/a", - "GPP_B1", "Reserved", "n/a", - "GPP_B2", "VRALERT#", "n/a", - "GPP_B3", "CPU_GP2", "n/a", - "GPP_B4", "CPU_GP3", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", - "GPP_B11", "EXT_PWR_GATE#", "n/a", - "GPP_B12", "SLP_S0#", "n/a", - "GPP_B13", "PLTRST#", "n/a", - "GPP_B14", "SPKR", "n/a", - "GPP_B15", "GSPI0_CS0#", "n/a", - "GPP_B16", "GSPI0_CLK", "n/a", - "GPP_B17", "GSPI0_MISO", "n/a", - "GPP_B18", "GSPI0_MOSI", "n/a", - "GPP_B19", "GSPI1_CS0#", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", - "GPIO_RSVD_1", "n/a", "n/a", - "GPIO_RSVD_2", "n/a", "n/a", + "GPP_B0", "CORE_VID0", "n/a", + "GPP_B1", "CORE_VID1", "n/a", + "GPP_B2", "VRALERT#", "n/a", + "GPP_B3", "CPU_GP2", "n/a", + "GPP_B4", "CPU_GP3", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", + "GPP_B11", "EXT_PWR_GATE#", "n/a", + "GPP_B12", "SLP_S0#", "n/a", + "GPP_B13", "PLTRST#", "n/a", + "GPP_B14", "SPKR", "n/a", + "GPP_B15", "GSPI0_CS0#", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", + "GPP_B19", "GSPI1_CS0#", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", + "GSPI0_CLK_LOOPBK", "GSPI0_CLK_LOOPBK", "n/a", + "GSPI1_CLK_LOOPBK", "GSPI1_CLK_LOOPBK", "n/a", }; const struct gpio_group cannonlake_pch_lp_group_b = { @@ -109,31 +109,31 @@ const struct gpio_group cannonlake_pch_lp_group_c = { }; const char *const cannonlake_pch_lp_group_d_names[] = { - "GPP_D0", "SPI1_CS#", "BK0", "SBK0", - "GPP_D1", "SPI1_CLK", "BK1", "SBK1", - "GPP_D2", "SPI1_MISO", "BK2", "SBK2", - "GPP_D3", "SPI1_MOSI", "BK3", "SBK3", - "GPP_D4", "IMGCLKOUT0", "BK4", "SBK4", - "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", - "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", - "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", - "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", - "GPP_D9", "ISH_SPI_CS#", "n/a", "GSPI2_CS0#", - "GPP_D10", "ISH_SPI_CLK", "n/a", "GSPI2_CLK", - "GPP_D11", "ISH_SPI_MISO", "n/a", "GSPI2_MISO", - "GPP_D12", "ISH_SPI_MOSI", "n/a", "GSPI2_MOSI", - "GPP_D13", "ISH_UART0_RXD", "SML0BDATA", "I2C4B_SDA", - "GPP_D14", "ISH_UART0_TXD", "SML0BCLK", "I2C4B_SCL", - "GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "n/a", - "GPP_D16", "ISH_UART0_CTS#", "SML0BALERT", "n/a", - "GPP_D17", "DMIC_CLK1", "SNDW3_CLK", "n/a", - "GPP_D18", "DMIC_DATA1", "SNDW3_DATA", "n/a", - "GPP_D19", "DMIC_CLK0", "SNDW4_CLK", "n/a", - "GPP_D20", "DMIC_DATA0", "SNDW4_DATA", "n/a", - "GPP_D21", "SPI1_IO2", "n/a", "n/a", - "GPP_D22", "SPI1_IO3", "n/a", "n/a", - "GPP_D23", "I2S_MCLK", "n/a", "n/a", - "GPIO_RSVD_12", "n/a", "n/a", "n/a", + "GPP_D0", "SPI1_CS#", "BK0", "SBK0", + "GPP_D1", "SPI1_CLK", "BK1", "SBK1", + "GPP_D2", "SPI1_MISO", "BK2", "SBK2", + "GPP_D3", "SPI1_MOSI", "BK3", "SBK3", + "GPP_D4", "IMGCLKOUT0", "BK4", "SBK4", + "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_D9", "ISH_SPI_CS#", "n/a", "GSPI2_CS0#", + "GPP_D10", "ISH_SPI_CLK", "n/a", "GSPI2_CLK", + "GPP_D11", "ISH_SPI_MISO", "n/a", "GSPI2_MISO", + "GPP_D12", "ISH_SPI_MOSI", "n/a", "GSPI2_MOSI", + "GPP_D13", "ISH_UART0_RXD", "SML0BDATA", "I2C4B_SDA", + "GPP_D14", "ISH_UART0_TXD", "SML0BCLK", "I2C4B_SCL", + "GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "SML0BALERT", "n/a", + "GPP_D17", "DMIC_CLK1", "SNDW3_CLK", "n/a", + "GPP_D18", "DMIC_DATA1", "SNDW3_DATA", "n/a", + "GPP_D19", "DMIC_CLK0", "SNDW4_CLK", "n/a", + "GPP_D20", "DMIC_DATA0", "SNDW4_DATA", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", + "GPP_D23", "I2S_MCLK", "n/a", "n/a", + "GSPI2_CLK_LOOPBK", "GSPI2_CLK_LOOPBK", "n/a", "n/a", }; const struct gpio_group cannonlake_pch_lp_group_d = { From f0c5d87a0ee6a8c4d819408c9b33288b0002c31a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 9 Sep 2020 19:55:36 +0200 Subject: [PATCH 189/262] util/inteltool: add missing native functions of special pads for CNL-LP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the missing native functions for special gpio pads for CNL-LP, which are documented in the PCH EDS and other places. Also, see soc/intel/tigerlake for reference. Change-Id: Iedb726aa3afdbbbedafb67f6b7668bf591c2b9b4 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45305 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/inteltool/gpio_names/cannonlake_lp.h | 52 +++++++++++------------ 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/util/inteltool/gpio_names/cannonlake_lp.h b/util/inteltool/gpio_names/cannonlake_lp.h index 9d9c66ba47..27d820cc03 100644 --- a/util/inteltool/gpio_names/cannonlake_lp.h +++ b/util/inteltool/gpio_names/cannonlake_lp.h @@ -75,36 +75,36 @@ const struct gpio_group cannonlake_pch_lp_group_b = { }; const char *const cannonlake_pch_lp_group_c_names[] = { - "GPP_C0", "SMBCLK", "n/a", - "GPP_C1", "SMBDATA", "n/a", - "GPP_C2", "SMBALERT#", "n/a", - "GPP_C3", "SML0CLK", "n/a", - "GPP_C4", "SML0DATA", "n/a", - "GPP_C5", "SML0ALERT#", "n/a", - "GPP_C6", "SML1CLK", "n/a", - "GPP_C7", "SML1DATA", "n/a", - "GPP_C8", "UART0_RXD", "n/a", - "GPP_C9", "UART0_TXD", "n/a", - "GPP_C10", "UART0_RTS#", "n/a", - "GPP_C11", "UART0_CTS#", "n/a", - "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", - "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", - "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", - "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", - "GPP_C16", "I2C0_SDA", "n/a", - "GPP_C17", "I2C0_SCL", "n/a", - "GPP_C18", "I2C1_SDA", "n/a", - "GPP_C19", "I2C1_SCL", "n/a", - "GPP_C20", "UART2_RXD", "n/a", - "GPP_C21", "UART2_TXD", "n/a", - "GPP_C22", "UART2_RTS#", "n/a", - "GPP_C23", "UART2_CTS#", "n/a", + "GPP_C0", "SMBCLK", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", + "GPP_C3", "SML0CLK", "n/a", "n/a", + "GPP_C4", "SML0DATA", "n/a", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", "n/a", + "GPP_C6", "SML1CLK", "n/a", "n/a", + "GPP_C7", "SML1DATA", "n/a", "n/a", + "GPP_C8", "UART0_RXD", "n/a", "n/a", + "GPP_C9", "UART0_TXD", "n/a", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "CNV_MFUART1_RXD", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "CNV_MFUART1_TXD", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "CNV_MFUART1_RTS", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "CNV_MFUART1_CTS", + "GPP_C16", "I2C0_SDA", "n/a", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", "n/a", + "GPP_C20", "UART2_RXD", "n/a", "n/a", + "GPP_C21", "UART2_TXD", "n/a", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", "n/a", }; const struct gpio_group cannonlake_pch_lp_group_c = { .display = "------- GPIO Group GPP_C -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_c_names) / 3, - .func_count = 3, + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_c_names) / 4, + .func_count = 4, .pad_names = cannonlake_pch_lp_group_c_names, }; From 1617521f57d2cd1f05784128a6a1cbf7ff73c8e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 9 Sep 2020 19:41:07 +0200 Subject: [PATCH 190/262] util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-H MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: Ifd6cabb646000c8dff695c5c4f7196b2779f1430 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45202 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/inteltool/gpio_names/cannonlake.h | 150 ++++++++++++------------- 1 file changed, 75 insertions(+), 75 deletions(-) diff --git a/util/inteltool/gpio_names/cannonlake.h b/util/inteltool/gpio_names/cannonlake.h index 305a1c38c6..074393608a 100644 --- a/util/inteltool/gpio_names/cannonlake.h +++ b/util/inteltool/gpio_names/cannonlake.h @@ -4,60 +4,60 @@ #include "gpio_groups.h" static const char *const cannonlake_pch_h_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", - "GPP_A3", "LAD2", "n/a", "ESPI_IO2", - "GPP_A4", "LAD3", "n/a", "ESPI_IO3", - "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", - "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", - "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "SD_VDD2_PWR_EN#", "n/a", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", - "GPP_A15", "SUSACK#", "n/a", "n/a", - "GPP_A16", "CLKOUT_48", "n/a", "n/a", - "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", - "GPIO_RSVD_0", "n/a", "n/a", "n/a", + "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", + "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", + "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "SD_VDD2_PWR_EN#", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUSACK#", "n/a", "n/a", + "GPP_A16", "CLKOUT_48", "n/a", "n/a", + "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", + "ESPI_CLK_LOOPBK", "ESPI_CLK_LOOPBK", "n/a", "n/a", }; static const char *const cannonlake_pch_h_group_b_names[] = { - "GPP_B0", "GSPI0_CS1#", "n/a", - "GPP_B1", "GSPI1_CS1#", "TIME_SYNC1", - "GPP_B2", "VRALERT#", "n/a", - "GPP_B3", "CPU_GP2", "n/a", - "GPP_B4", "CPU_GP3", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", - "GPP_B11", "I2S_MCLK", "n/a", - "GPP_B12", "SLP_S0#", "n/a", - "GPP_B13", "PLTRST#", "n/a", - "GPP_B14", "SPKR", "n/a", - "GPP_B15", "GSPI0_CS0#", "n/a", - "GPP_B16", "GSPI0_CLK", "n/a", - "GPP_B17", "GSPI0_MISO", "n/a", - "GPP_B18", "GSPI0_MOSI", "n/a", - "GPP_B19", "GSPI1_CS0#", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", - "GPIO_RSVD_1", "n/a", "n/a", - "GPIO_RSVD_2", "n/a", "n/a", + "GPP_B0", "GSPI0_CS1#", "n/a", + "GPP_B1", "GSPI1_CS1#", "TIME_SYNC1", + "GPP_B2", "VRALERT#", "n/a", + "GPP_B3", "CPU_GP2", "n/a", + "GPP_B4", "CPU_GP3", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", + "GPP_B11", "I2S_MCLK", "n/a", + "GPP_B12", "SLP_S0#", "n/a", + "GPP_B13", "PLTRST#", "n/a", + "GPP_B14", "SPKR", "n/a", + "GPP_B15", "GSPI0_CS0#", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", + "GPP_B19", "GSPI1_CS0#", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", + "GSPI0_CLK_LOOPBK", "GSPI0_CLK_LOOPBK", "n/a", + "GSPI1_CLK_LOOPBK", "GSPI1_CLK_LOOPBK", "n/a", }; static const char *const cannonlake_pch_h_group_c_names[] = { @@ -158,15 +158,15 @@ static const char *const cannonlake_pch_h_group_f_names[] = { }; static const char *const cannonlake_pch_h_group_spi_names[] = { - "GPIO_RSVD_11", - "GPIO_RSVD_12", - "GPIO_RSVD_13", - "GPIO_RSVD_14", - "GPIO_RSVD_15", - "GPIO_RSVD_16", - "GPIO_RSVD_17", - "GPIO_RSVD_18", - "GPIO_RSVD_19", + "SPI0_IO_2", + "SPI0_IO_3", + "SPI0_MISO", + "SPI0_MOSI", + "SPI0_CS2_B", + "SPI0_CS0_B", + "SPI0_CS1_B", + "SPI0_CLK", + "SPI0_CLK_LOOPBK", }; static const char *const cannonlake_pch_h_group_g_names[] = { @@ -181,14 +181,14 @@ static const char *const cannonlake_pch_h_group_g_names[] = { }; static const char *const cannonlake_pch_h_group_aza_names[] = { - "GPIO_RSVD_3", - "GPIO_RSVD_4", - "GPIO_RSVD_5", - "GPIO_RSVD_6", - "GPIO_RSVD_7", - "GPIO_RSVD_8", - "GPIO_RSVD_9", - "GPIO_RSVD_10", + "HDA_BCLK", + "HDA_RST_B", + "HDA_SYNC", + "HDA_SDO", + "HDA_SDI_0", + "HDA_SDI_1", + "I2S1_SFRM", + "I2S1_TXD", }; static const char *const cannonlake_pch_h_group_vgpio_0_names[] = { @@ -196,8 +196,8 @@ static const char *const cannonlake_pch_h_group_vgpio_0_names[] = { "CNV_GNEN", "CNV_WFEN", "CNV_WCEN", - "CNV_BT_HOST_WAKEB", - "vCNV_GNSS_HOST_WAKEB", + "CNV_BT_HOST_WAKE_B", + "vCNV_GNSS_HOST_WAKE_B", "vSD3_CD_B", "CNV_BT_IF_SELECT", "vCNV_BT_UART_TXD", @@ -215,11 +215,11 @@ static const char *const cannonlake_pch_h_group_vgpio_0_names[] = { "vUART0_TXD", "vUART0_RXD", "vUART0_CTS_B", - "vUART0_RTSB", + "vUART0_RTS_B", "vISH_UART0_TXD", "vISH_UART0_RXD", "vISH_UART0_CTS_B", - "vISH_UART0_RTSB", + "vISH_UART0_RTS_B", "vISH_UART1_TXD", "vISH_UART1_RXD", "vISH_UART1_CTS_B", @@ -280,9 +280,9 @@ static const char *const cannonlake_pch_h_group_i_names[] = { "GPP_I12", "M2_SKT2_CFG1", "n/a", "GPP_I13", "M2_SKT2_CFG2", "n/a", "GPP_I14", "M2_SKT2_CFG3", "n/a", - "GPIO_RSVD_40", "n/a", "n/a", - "GPIO_RSVD_41", "n/a", "n/a", - "GPIO_RSVD_42", "n/a", "n/a", + "SYS_PWROK", "n/a", "n/a", + "SYS_RESET_B", "n/a", "n/a", + "CL_RST_B", "n/a", "n/a", }; static const char *const cannonlake_pch_h_group_j_names[] = { From 33a047da6862f72eae85cda0cf85e8c6af61af85 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 9 Sep 2020 19:55:36 +0200 Subject: [PATCH 191/262] util/inteltool: add missing native functions of special pads for CNL-H MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the missing native functions for special gpio pads for CNL-H, which are documented in the PCH EDS and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I71339d66362d29806c91375c214e9fb84c989201 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45203 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/inteltool/gpio_names/cannonlake.h | 136 ++++++++++++------------- 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/util/inteltool/gpio_names/cannonlake.h b/util/inteltool/gpio_names/cannonlake.h index 074393608a..47672d5673 100644 --- a/util/inteltool/gpio_names/cannonlake.h +++ b/util/inteltool/gpio_names/cannonlake.h @@ -158,15 +158,15 @@ static const char *const cannonlake_pch_h_group_f_names[] = { }; static const char *const cannonlake_pch_h_group_spi_names[] = { - "SPI0_IO_2", - "SPI0_IO_3", - "SPI0_MISO", - "SPI0_MOSI", - "SPI0_CS2_B", - "SPI0_CS0_B", - "SPI0_CS1_B", - "SPI0_CLK", - "SPI0_CLK_LOOPBK", + "SPI0_IO_2", "SPI0_IO_2", + "SPI0_IO_3", "SPI0_IO_3", + "SPI0_MISO", "SPI0_MISO", + "SPI0_MOSI", "SPI0_MOSI", + "SPI0_CS2_B", "SPI0_CS2#", + "SPI0_CS0_B", "SPI0_CS0#", + "SPI0_CS1_B", "SPI0_CS1#", + "SPI0_CLK", "SPI0_CLK", + "SPI0_CLK_LOOPBK", "SPI0_CLK_LOOPBK", }; static const char *const cannonlake_pch_h_group_g_names[] = { @@ -181,60 +181,60 @@ static const char *const cannonlake_pch_h_group_g_names[] = { }; static const char *const cannonlake_pch_h_group_aza_names[] = { - "HDA_BCLK", - "HDA_RST_B", - "HDA_SYNC", - "HDA_SDO", - "HDA_SDI_0", - "HDA_SDI_1", - "I2S1_SFRM", - "I2S1_TXD", + "HDA_BCLK", "HDA_BCLK", "I2S0_SCLK", "n/a", + "HDA_RST_B", "HDA_RST#", "I2S1_SCLK", "SNDW1_CLK", + "HDA_SYNC", "HDA_SYNC", "I2S0_SFRM", "n/a", + "HDA_SDO", "HDA_SDO", "I2S0_TXD", "n/a", + "HDA_SDI0", "HDA_SDI0", "I2S0_RXD", "n/a", + "HDA_SDI1", "HDA_SDI1", "I2S1_RXD", "SNDW1_DATA", + "I2S1_SFRM", "I2S1_SFRM", "SNDW2_CLK", "n/a", + "I2S1_TXD", "I2S1_TXD", "SNDW2_DATA", "n/a", }; static const char *const cannonlake_pch_h_group_vgpio_0_names[] = { - "CNV_BTEN", - "CNV_GNEN", - "CNV_WFEN", - "CNV_WCEN", - "CNV_BT_HOST_WAKE_B", - "vCNV_GNSS_HOST_WAKE_B", - "vSD3_CD_B", - "CNV_BT_IF_SELECT", - "vCNV_BT_UART_TXD", - "vCNV_BT_UART_RXD", - "vCNV_BT_UART_CTS_B", - "vCNV_BT_UART_RTS_B", - "vCNV_MFUART1_TXD", - "vCNV_MFUART1_RXD", - "vCNV_MFUART1_CTS_B", - "vCNV_MFUART1_RTS_B", - "vCNV_GNSS_UART_TXD", - "vCNV_GNSS_UART_RXD", - "vCNV_GNSS_UART_CTS_B", - "vCNV_GNSS_UART_RTS_B", - "vUART0_TXD", - "vUART0_RXD", - "vUART0_CTS_B", - "vUART0_RTS_B", - "vISH_UART0_TXD", - "vISH_UART0_RXD", - "vISH_UART0_CTS_B", - "vISH_UART0_RTS_B", - "vISH_UART1_TXD", - "vISH_UART1_RXD", - "vISH_UART1_CTS_B", - "vISH_UART1_RTS_B", + "CNV_BTEN", "n/a", "n/a", "n/a", + "CNV_GNEN", "n/a", "n/a", "n/a", + "CNV_WFEN", "n/a", "n/a", "n/a", + "CNV_WCEN", "n/a", "n/a", "n/a", + "vCNV_GNSS_HOST_WAKE_B", "n/a", "n/a", "n/a", + "vSD3_CD_B", "n/a", "n/a", "n/a", + "CNV_BT_HOST_WAKE_B", "n/a", "n/a", "n/a", + "CNV_BT_IF_SELECT", "n/a", "n/a", "n/a", + "vCNV_BT_UART_TXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_RXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_CTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_RTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_TXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_RXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_CTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_RTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_GNSS_UART_TXD", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_RXD", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_CTS_B", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_RTS_B", "n/a", "n/a", "n/a", + "vUART0_TXD", "mapped", "n/a", "n/a", + "vUART0_RXD", "mapped", "n/a", "n/a", + "vUART0_CTS_B", "mapped", "n/a", "n/a", + "vUART0_RTS_B", "mapped", "n/a", "n/a", + "vISH_UART0_TXD", "mapped", "n/a", "n/a", + "vISH_UART0_RXD", "mapped", "n/a", "n/a", + "vISH_UART0_CTS_B", "mapped", "n/a", "n/a", + "vISH_UART0_RTS_B", "mapped", "n/a", "n/a", + "vISH_UART1_TXD", "mapped", "n/a", "n/a", + "vISH_UART1_RXD", "mapped", "n/a", "n/a", + "vISH_UART1_CTS_B", "mapped", "n/a", "n/a", + "vISH_UART1_RTS_B", "mapped", "n/a", "n/a", }; static const char *const cannonlake_pch_h_group_vgpio_1_names[] = { - "vCNV_BT_I2S_BCLK", - "vCNV_BT_I2S_WS_SYNC", - "vCNV_BT_I2S_SDO", - "vCNV_BT_I2S_SDI", - "vSSP2_SCLK", - "vSSP2_SFRM", - "vSSP2_TXD", - "vSSP2_RXD", + "vCNV_BT_I2S_BCLK", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_WS_SYNC", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_SDO", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_SDI", "SSP0", "SSP1", "SSP2", + "vSSP2_SCLK", "mapped", "n/a", "n/a", + "vSSP2_SFRM", "mapped", "n/a", "n/a", + "vSSP2_TXD", "mapped", "n/a", "n/a", + "vSSP2_RXD", "n/a", "n/a", "n/a", }; static const char *const cannonlake_pch_h_group_h_names[] = { @@ -280,9 +280,9 @@ static const char *const cannonlake_pch_h_group_i_names[] = { "GPP_I12", "M2_SKT2_CFG1", "n/a", "GPP_I13", "M2_SKT2_CFG2", "n/a", "GPP_I14", "M2_SKT2_CFG3", "n/a", - "SYS_PWROK", "n/a", "n/a", - "SYS_RESET_B", "n/a", "n/a", - "CL_RST_B", "n/a", "n/a", + "SYS_PWROK", "SYS_PWROK", "n/a", + "SYS_RESET_B", "SYS_RESET#", "n/a", + "CL_RST_B", "CL_RST#", "n/a", }; static const char *const cannonlake_pch_h_group_j_names[] = { @@ -386,8 +386,8 @@ static const struct gpio_group cannonlake_pch_h_group_f = { static const struct gpio_group cannonlake_pch_h_group_spi = { .display = "------- GPIO Group SPI -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_spi_names) / 1, - .func_count = 1, + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_spi_names) / 2, + .func_count = 2, .pad_names = cannonlake_pch_h_group_spi_names, }; @@ -400,22 +400,22 @@ static const struct gpio_group cannonlake_pch_h_group_g = { static const struct gpio_group cannonlake_pch_h_group_aza = { .display = "------- GPIO Group AZA -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_aza_names) / 1, - .func_count = 1, + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_aza_names) / 4, + .func_count = 4, .pad_names = cannonlake_pch_h_group_aza_names, }; static const struct gpio_group cannonlake_pch_h_group_vgpio_0 = { .display = "------- GPIO Group VGPIO_0 -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_0_names) / 1, - .func_count = 1, + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_0_names) / 4, + .func_count = 4, .pad_names = cannonlake_pch_h_group_vgpio_0_names, }; static const struct gpio_group cannonlake_pch_h_group_vgpio_1 = { .display = "------- GPIO Group VGPIO_1 -------", - .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_1_names) / 1, - .func_count = 1, + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_1_names) / 4, + .func_count = 4, .pad_names = cannonlake_pch_h_group_vgpio_1_names, }; From 85c8a51577abfa366f1b3e126d8a76407c6336b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 9 Sep 2020 19:57:57 +0200 Subject: [PATCH 192/262] util/inteltool: add missing special function pads for CNL-H MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the missing special function gpio pad groups for CNL-H. The groups and names are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: Ib83aeef9f4b6aa174e61ccbd87fb7b6450ed773b Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45204 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/inteltool/gpio_names/cannonlake.h | 46 ++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/util/inteltool/gpio_names/cannonlake.h b/util/inteltool/gpio_names/cannonlake.h index 47672d5673..694b1588de 100644 --- a/util/inteltool/gpio_names/cannonlake.h +++ b/util/inteltool/gpio_names/cannonlake.h @@ -264,6 +264,32 @@ static const char *const cannonlake_pch_h_group_h_names[] = { "GPP_H23", "TIME_SYNC0", }; +const char *const cannonlake_pch_h_group_cpu_names[] = { + "HDACPU_SDI", "HDACPU_SDI", + "HDACPU_SDO", "HDACPU_SDO", + "HDACPU_SCLK", "HDACPU_SCLK", + "PM_SYNC", "PM_SYNC", + "PECI", "PECI", + "CPUPWRGD", "CPUPWRG#", + "THRMTRIP_B", "THRMTRIP#", + "PLTRST_CPU_B", "PLTRST_CPU#", + "PM_DOWN", "PM_DOWN", + "TRIGGER_IN", "TRIGGER_IN", + "TRIGGER_OUT", "TRIGGER_OUT", +}; + +const char *const cannonlake_pch_h_group_jtag_names[] = { + "PCH_TDO", "PCH_TDO", + "PCH_JTAGX", "PCH_JTAGX", + "PROC_PRDY_B", "PROC_RDY#", + "PROC_PREQ_B", "PROC_REQ#", + "CPU_TRST_B", "CPU_TRST#", + "PCH_TDI", "PCH_TDI", + "PCH_TMS", "PCH_TMS", + "PCH_TCK", "PCH_TCK", + "ITP_PMODE", "ITP_PMODE", +}; + static const char *const cannonlake_pch_h_group_i_names[] = { "GPP_I0", "DDPB_HPD0", "DISP_MISC0", "GPP_I1", "DDPB_HPD1", "DISP_MISC1", @@ -340,6 +366,10 @@ static const char *const cannonlake_pch_h_group_gpd_names[] = { "GPD9", "SLP_WLAN#", "GPD10", "SLP_S5#", "GPD11", "LANPHYPC", + "SLP_LAN_B", "SLP_LAN#", + "SLP_SUS_B", "SLP_SUS#", + "WAKE_B", "WAKE#", + "DRAM_RESET_B", "DRAM_RESET#", }; static const struct gpio_group cannonlake_pch_h_group_a = { @@ -426,6 +456,20 @@ static const struct gpio_group cannonlake_pch_h_group_h = { .pad_names = cannonlake_pch_h_group_h_names, }; +static const struct gpio_group cannonlake_pch_h_group_cpu = { + .display = "------- GPIO Group CPU -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_cpu_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_h_group_cpu_names, +}; + +static const struct gpio_group cannonlake_pch_h_group_jtag = { + .display = "------- GPIO Group JTAG -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_jtag_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_h_group_jtag_names, +}; + static const struct gpio_group cannonlake_pch_h_group_i = { .display = "------- GPIO Group GPP_I -------", .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_i_names) / 3, @@ -505,6 +549,8 @@ static const struct gpio_community cannonlake_pch_h_community_3 = { }; static const struct gpio_group *const cannonlake_pch_h_community_4_groups[] = { + &cannonlake_pch_h_group_cpu, + &cannonlake_pch_h_group_jtag, &cannonlake_pch_h_group_i, &cannonlake_pch_h_group_j, }; From 2a5fe1d64b012553d91355fe82b3b6b49f8812dc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 9 Sep 2020 19:47:14 +0200 Subject: [PATCH 193/262] util/inteltool: add missing special function pads for CNL-LP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the missing special function gpio pad groups for CNL-LP. The groups and names are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I0509552da6ffad395c2b89df1676e1903c783695 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45201 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/inteltool/gpio_names/cannonlake_lp.h | 166 ++++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/util/inteltool/gpio_names/cannonlake_lp.h b/util/inteltool/gpio_names/cannonlake_lp.h index 27d820cc03..af14c1fb1f 100644 --- a/util/inteltool/gpio_names/cannonlake_lp.h +++ b/util/inteltool/gpio_names/cannonlake_lp.h @@ -276,7 +276,12 @@ const char *const cannonlake_pch_lp_group_gpd_names[] = { "GPD9", "SLP_WLAN#", "GPD10", "SLP_S5#", "GPD11", "LANPHYPC", + "SLP_LAN_B", "SLP_LAN#", + "SLP_SUS_B", "SLP_SUS#", + "WAKE_B", "WAKE#", + "DRAM_RESET_B", "DRAM_RESET#", }; + const struct gpio_group cannonlake_pch_lp_group_gpd = { .display = "------- GPIO Group GPD -------", .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_gpd_names) / 2, @@ -284,11 +289,156 @@ const struct gpio_group cannonlake_pch_lp_group_gpd = { .pad_names = cannonlake_pch_lp_group_gpd_names, }; +const char *const cannonlake_pch_lp_group_vgpio_names[] = { + "CNV_BTEN", "n/a", "n/a", "n/a", + "CNV_GNEN", "n/a", "n/a", "n/a", + "CNV_WFEN", "n/a", "n/a", "n/a", + "CNV_WCEN", "n/a", "n/a", "n/a", + "CNV_BT_HOST_WAKE_B", "n/a", "n/a", "n/a", + "CNV_BT_IF_SELECT", "n/a", "n/a", "n/a", + "vCNV_BT_UART_TXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_RXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_CTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_BT_UART_RTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_TXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_RXD", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_CTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_MFUART1_RTS_B", "ISH UART0", "SIo UART2", "n/a", + "vCNV_GNSS_UART_TXD", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_RXD", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_CTS_B", "n/a", "n/a", "n/a", + "vCNV_GNSS_UART_RTS_B", "n/a", "n/a", "n/a", + "vUART0_TXD", "mapped", "n/a", "n/a", + "vUART0_RXD", "mapped", "n/a", "n/a", + "vUART0_CTS_B", "mapped", "n/a", "n/a", + "vUART0_RTS_B", "mapped", "n/a", "n/a", + "vISH_UART0_TXD", "mapped", "n/a", "n/a", + "vISH_UART0_RXD", "mapped", "n/a", "n/a", + "vISH_UART0_CTS_B", "mapped", "n/a", "n/a", + "vISH_UART0_RTS_B", "mapped", "n/a", "n/a", + "vISH_UART1_TXD", "mapped", "n/a", "n/a", + "vISH_UART1_RXD", "mapped", "n/a", "n/a", + "vISH_UART1_CTS_B", "mapped", "n/a", "n/a", + "vISH_UART1_RTS_B", "mapped", "n/a", "n/a", + "vCNV_BT_I2S_BCLK", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_WS_SYNC", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_SDO", "SSP0", "SSP1", "SSP2", + "vCNV_BT_I2S_SDI", "SSP0", "SSP1", "SSP2", + "vSSP2_SCLK", "mapped", "n/a", "n/a", + "vSSP2_SFRM", "mapped", "n/a", "n/a", + "vSSP2_TXD", "mapped", "n/a", "n/a", + "vSSP2_RXD", "n/a", "n/a", "n/a", + "vCNV_GNSS_HOST_WAKE_B", "n/a", "n/a", "n/a", + "vSD3_CD_B", "n/a", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_vgpio = { + .display = "------- GPIO Group VGPIO -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_vgpio_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_vgpio_names, +}; + +const char *const cannonlake_pch_lp_group_spi_names[] = { + "SPI0_IO_2", "SPI0_IO_2", + "SPI0_IO_3", "SPI0_IO_3", + "SPI0_MISO", "SPI0_MISO", + "SPI0_MOSI", "SPI0_MOSI", + "SPI0_CS2_B", "SPI0_CS2#", + "SPI0_CS0_B", "SPI0_CS0#", + "SPI0_CS1_B", "SPI0_CS1#", + "SPI0_CLK", "SPI0_CLK", + "SPI0_CLK_LOOPBK", "SPI0_CLK_LOOPBK", +}; + +const struct gpio_group cannonlake_pch_lp_group_spi = { + .display = "------- GPIO Group SPI -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_spi_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_spi_names, +}; + +const char *const cannonlake_pch_lp_group_aza_names[] = { + "HDA_BCLK", "HDA_BCLK", "I2S0_SCLK", "n/a", + "HDA_RST_B", "HDA_RST#", "I2S1_SCLK", "SNDW1_CLK", + "HDA_SYNC", "HDA_SYNC", "I2S0_SFRM", "n/a", + "HDA_SDO", "HDA_SDO", "I2S0_TXD", "n/a", + "HDA_SDI0", "HDA_SDI0", "I2S0_RXD", "n/a", + "HDA_SDI1", "HDA_SDI1", "I2S1_RXD", "SNDW1_DATA", + "I2S1_SFRM", "I2S1_SFRM", "SNDW2_CLK", "n/a", + "I2S1_TXD", "I2S1_TXD", "SNDW2_DATA", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_aza = { + .display = "------- GPIO Group AZA -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_aza_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_aza_names, +}; + +const char *const cannonlake_pch_lp_group_cpu_names[] = { + "HDACPU_SDI", "HDACPU_SDI", + "HDACPU_SDO", "HDACPU_SDO", + "HDACPU_SCLK", "HDACPU_SCLK", + "PM_SYNC", "PM_SYNC", + "PECI", "PECI", + "CPUPWRGD", "CPUPWRGD", + "THRMTRIP_B", "THRMTRIP#", + "PLTRST_CPU_B", "PLTRST_CPU#", + "PM_DOWN", "PM_DOWN", + "TRIGGER_IN", "TRIGGER_IN", + "TRIGGER_OUT", "TRIGGER_OUT", +}; + +const struct gpio_group cannonlake_pch_lp_group_cpu = { + .display = "------- GPIO Group CPU -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_cpu_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_cpu_names, +}; + +const char *const cannonlake_pch_lp_group_jtag_names[] = { + "PCH_TDO", "PCH_TDO", + "PCH_JTAGX", "PCH_JTAGX", + "PROC_PRDY_B", "PROC_PRDY#", + "PROC_PREQ_B", "PROC_PREQ#", + "CPU_TRST_B", "CPU_TRST#", + "PCH_TDI", "PCH_TDI", + "PCH_TMS", "PCH_TMS", + "PCH_TCK", "PCH_TCK", + "ITP_PMODE", "ITP_PMODE", +}; + +const struct gpio_group cannonlake_pch_lp_group_jtag = { + .display = "------- GPIO Group JTAG -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_jtag_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_jtag_names, +}; + +const char *const cannonlake_pch_lp_group_hvmos_names[] = { + "EDP_VDDEN", "EDP_VDDEN", + "EDP_BKLTEN", "EDP_BKLTEN", + "EDP_BKLTCTL", "EDP_BKLTCTL", + "SYS_PWROK", "SYS_PWROK", + "SYS_RESET_B", "SYS_RESET#", + "CL_RST_B", "CL_RST#", +}; + +const struct gpio_group cannonlake_pch_lp_group_hvmos = { + .display = "------- GPIO Group HVMOS -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_hvmos_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_hvmos_names, +}; + const struct gpio_group *const cannonlake_pch_lp_community_0_groups[] = { &cannonlake_pch_lp_group_a, &cannonlake_pch_lp_group_b, &cannonlake_pch_lp_group_g, + &cannonlake_pch_lp_group_spi, }; + const struct gpio_community cannonlake_pch_lp_community_0 = { .name = "------- GPIO Community 0 -------", .pcr_port_id = 0x6e, @@ -300,6 +450,7 @@ const struct gpio_group *const cannonlake_pch_lp_community_1_groups[] = { &cannonlake_pch_lp_group_d, &cannonlake_pch_lp_group_f, &cannonlake_pch_lp_group_h, + &cannonlake_pch_lp_group_vgpio, }; const struct gpio_community cannonlake_pch_lp_community_1 = { .name = "------- GPIO Community 1 -------", @@ -319,9 +470,23 @@ const struct gpio_community cannonlake_pch_lp_community_2 = { .groups = cannonlake_pch_lp_community_2_groups, }; +const struct gpio_group *const cannonlake_pch_lp_community_3_groups[] = { + &cannonlake_pch_lp_group_aza, + &cannonlake_pch_lp_group_cpu, +}; + +const struct gpio_community cannonlake_pch_lp_community_3 = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0x6b, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_3_groups), + .groups = cannonlake_pch_lp_community_3_groups, +}; + const struct gpio_group *const cannonlake_pch_lp_community_4_groups[] = { &cannonlake_pch_lp_group_c, &cannonlake_pch_lp_group_e, + &cannonlake_pch_lp_group_jtag, + &cannonlake_pch_lp_group_hvmos, }; const struct gpio_community cannonlake_pch_lp_community_4 = { @@ -335,6 +500,7 @@ const struct gpio_community *const cannonlake_pch_lp_communities[] = { &cannonlake_pch_lp_community_0, &cannonlake_pch_lp_community_1, &cannonlake_pch_lp_community_2, + &cannonlake_pch_lp_community_3, &cannonlake_pch_lp_community_4, }; From ed820a0e21510c748363ac2ed6bce1242277fbc7 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 11 Nov 2020 14:50:01 +0100 Subject: [PATCH 194/262] util/futility: Don't refresh the binary all the time Due to the phony dependency to check for openssl, vboot-futility was always rebuilt, and because it was newer than coreboot-futility, it was always copied over. Do that in parallel often enough and you run into race conditions, as we did on our builders. Mark check-openssl-presence as order-only dependency so that it's executed (and can bail out) but doesn't force regeneration of vboot-futility. Change-Id: Ib7fb798096d423d6b6cba5d199e12fe5917c3b41 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/47453 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Martin Roth Reviewed-by: Stefan Reinauer --- util/futility/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/futility/Makefile.inc b/util/futility/Makefile.inc index ed185ce0d5..9890339d46 100644 --- a/util/futility/Makefile.inc +++ b/util/futility/Makefile.inc @@ -4,7 +4,7 @@ VBOOT_FUTILITY = $(VBOOT_HOST_BUILD)/futility/futility HOSTPKGCONFIG ?= pkg-config -$(VBOOT_FUTILITY): check-openssl-presence +$(VBOOT_FUTILITY): | check-openssl-presence @printf " MAKE $(subst $(objutil)/,,$(@))\n" unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$(VBOOT_HOST_BUILD) \ From 0c32182dbacf5bbb454019cf8ed1a1192b52a225 Mon Sep 17 00:00:00 2001 From: Shreesh Chhabbi Date: Thu, 5 Nov 2020 12:22:13 -0800 Subject: [PATCH 195/262] soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode This change switches the selection of CAR mode so that INTEL_CAR_NEM_ENHANCED_V2 is the default unless mainboard selects INTEL_CAR_NEM. INTEL_CAR_NEM is selected only by mainboards using older silicon (ES1 or ES2) that did not support NEM enhanced mode. This enables NEM Enhanced Mode for TGL-U/Y RVPs. Bug=b:171601324 BRANCH=volteer Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache. Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5 Signed-off-by: Shreesh Chhabbi Reviewed-on: https://review.coreboot.org/c/coreboot/+/47259 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/volteer/Kconfig.name | 15 +++++++-------- src/soc/intel/tigerlake/Kconfig | 2 +- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 7aaaea77a2..b651430ddd 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -4,58 +4,60 @@ config BOARD_GOOGLE_DELBIN bool "-> Delbin" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU - select USE_CAR_NEM_ENHANCED_V2 select DRIVERS_GENESYSLOGIC_GL9755 config BOARD_GOOGLE_ELDRID bool "-> Eldrid" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU - select USE_CAR_NEM_ENHANCED_V2 config BOARD_GOOGLE_HALVOR bool "-> Halvor" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + select INTEL_CAR_NEM config BOARD_GOOGLE_LINDAR bool "-> Lindar" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + select INTEL_CAR_NEM config BOARD_GOOGLE_MALEFOR bool "-> Malefor" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + select INTEL_CAR_NEM config BOARD_GOOGLE_TERRADOR bool "-> Terrador" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU - select USE_CAR_NEM_ENHANCED_V2 config BOARD_GOOGLE_TODOR bool "-> Todor" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + select INTEL_CAR_NEM config BOARD_GOOGLE_TRONDO bool "-> Trondo" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + select INTEL_CAR_NEM config BOARD_GOOGLE_VOLTEER bool "-> Volteer" select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA select SOC_INTEL_CSE_LITE_SKU + select INTEL_CAR_NEM config BOARD_GOOGLE_VOLTEER2 bool "-> Volteer2" select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA select SOC_INTEL_CSE_LITE_SKU - select USE_CAR_NEM_ENHANCED_V2 select DRIVERS_GENESYSLOGIC_GL9755 # Reworked Volteer2 prototype, Haven chip replaced with Dauntless demo board @@ -64,27 +66,24 @@ config BOARD_GOOGLE_VOLTEER2_TI50 select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA select SOC_INTEL_CSE_LITE_SKU - select USE_CAR_NEM_ENHANCED_V2 select DRIVERS_GENESYSLOGIC_GL9755 config BOARD_GOOGLE_VOXEL bool "-> Voxel" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU - select USE_CAR_NEM_ENHANCED_V2 config BOARD_GOOGLE_BOLDAR bool "-> Boldar" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_CAR_NEM config BOARD_GOOGLE_ELEMI bool "-> Elemi" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU - select USE_CAR_NEM_ENHANCED_V2 config BOARD_GOOGLE_VOEMA bool "-> Voema" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU - select USE_CAR_NEM_ENHANCED_V2 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 79a4c6495b..b276fb905f 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -23,7 +23,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select INTEL_CAR_NEM + select USE_CAR_NEM_ENHANCED_V2 if !INTEL_CAR_NEM select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC From 42b1d3fccfefb70f8158f0f604b4dc4d3a0d1be5 Mon Sep 17 00:00:00 2001 From: Shreesh Chhabbi Date: Thu, 5 Nov 2020 12:06:29 -0800 Subject: [PATCH 196/262] mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS Selecting USE_CAR_NEM_ENHANCED_V1 as of now. This selection in Kconfig programs IA32_L3_MASK_1 (0xc91) & IA32_L3_MASK_2 (0xc92). These will select ways for eviction & non-eviction. TGL will have to switch back to USE_CAR_NEM_ENHANCED_V2 once the IA32_L3_SF_MASK_1 (0x1891) & IA32_L3_SF_MASK_2 (0x1892) programming requirements are understood. Bug=b:171601324 BRANCH=volteer Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache. Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b Signed-off-by: Shreesh Chhabbi Reviewed-on: https://review.coreboot.org/c/coreboot/+/47258 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/tigerlake/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index b276fb905f..f1ac774cd0 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -23,7 +23,8 @@ config CPU_SPECIFIC_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select USE_CAR_NEM_ENHANCED_V2 if !INTEL_CAR_NEM + select USE_CAR_NEM_ENHANCED_V1 if !INTEL_CAR_NEM + select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC From 9c50462fd7ce12cb9b3ef94f5bef39dcfa24ca6c Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 10 Nov 2020 15:55:37 -0800 Subject: [PATCH 197/262] Delete mainboard/google/cheza Work on this mainboard was abandoned and never finished. It's not really usable in its current state, so let's get rid of it. Signed-off-by: Julius Werner Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47427 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Angel Pons --- Documentation/security/vboot/list_vboot.md | 1 - payloads/libpayload/configs/config.cheza | 3 -- src/mainboard/google/cheza/Kconfig | 46 ---------------------- src/mainboard/google/cheza/Kconfig.name | 4 -- src/mainboard/google/cheza/Makefile.inc | 20 ---------- src/mainboard/google/cheza/board.h | 17 -------- src/mainboard/google/cheza/board_info.txt | 6 --- src/mainboard/google/cheza/boardid.c | 37 ----------------- src/mainboard/google/cheza/bootblock.c | 9 ----- src/mainboard/google/cheza/chromeos.c | 33 ---------------- src/mainboard/google/cheza/chromeos.fmd | 42 -------------------- src/mainboard/google/cheza/devicetree.cb | 5 --- src/mainboard/google/cheza/mainboard.c | 37 ----------------- src/mainboard/google/cheza/reset.c | 11 ------ src/mainboard/google/cheza/romstage.c | 22 ----------- 15 files changed, 293 deletions(-) delete mode 100644 payloads/libpayload/configs/config.cheza delete mode 100644 src/mainboard/google/cheza/Kconfig delete mode 100644 src/mainboard/google/cheza/Kconfig.name delete mode 100644 src/mainboard/google/cheza/Makefile.inc delete mode 100644 src/mainboard/google/cheza/board.h delete mode 100644 src/mainboard/google/cheza/board_info.txt delete mode 100644 src/mainboard/google/cheza/boardid.c delete mode 100644 src/mainboard/google/cheza/bootblock.c delete mode 100644 src/mainboard/google/cheza/chromeos.c delete mode 100644 src/mainboard/google/cheza/chromeos.fmd delete mode 100644 src/mainboard/google/cheza/devicetree.cb delete mode 100644 src/mainboard/google/cheza/mainboard.c delete mode 100644 src/mainboard/google/cheza/reset.c delete mode 100644 src/mainboard/google/cheza/romstage.c diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md index 30083f0c90..c0ccfceafb 100644 --- a/Documentation/security/vboot/list_vboot.md +++ b/Documentation/security/vboot/list_vboot.md @@ -20,7 +20,6 @@ - Tricky (Dell Chromebox 3010) - Zako (HP Chromebox G1) - Butterfly (HP Pavilion Chromebook 14) -- Cheza - Banon (Acer Chromebook 15 (CB3-532)) - Celes (Samsung Chromebook 3) - Cyan (Acer Chromebook R11 (C738T)) diff --git a/payloads/libpayload/configs/config.cheza b/payloads/libpayload/configs/config.cheza deleted file mode 100644 index 5f60392fdb..0000000000 --- a/payloads/libpayload/configs/config.cheza +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_LP_CHROMEOS=y -CONFIG_LP_ARCH_ARM64=y -CONFIG_LP_TIMER_ARM64_ARCH=y diff --git a/src/mainboard/google/cheza/Kconfig b/src/mainboard/google/cheza/Kconfig deleted file mode 100644 index 3f3f75607b..0000000000 --- a/src/mainboard/google/cheza/Kconfig +++ /dev/null @@ -1,46 +0,0 @@ - -config BOARD_GOOGLE_CHEZA_COMMON # Umbrella option to be selected by variants - def_bool n - -if BOARD_GOOGLE_CHEZA_COMMON - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_16384 - select COMMON_CBFS_SPI_WRAPPER - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_RTC - select EC_GOOGLE_CHROMEEC_SPI - select RTC - select SOC_QUALCOMM_SDM845 - select SPI_FLASH - select SPI_FLASH_WINBOND - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_TPM2 - select MAINBOARD_HAS_SPI_TPM_CR50 - -config VBOOT - select EC_GOOGLE_CHROMEEC_SWITCHES - select VBOOT_VBNV_FLASH - -config MAINBOARD_DIR - string - default "google/cheza" - -config DRIVER_TPM_SPI_BUS - hex - default 0x5 - -config EC_GOOGLE_CHROMEEC_SPI_BUS - hex - default 0xa - -########################################################## -#### Update below when adding a new derivative board. #### -########################################################## - -config MAINBOARD_PART_NUMBER - string - default "Cheza" if BOARD_GOOGLE_CHEZA - -endif # BOARD_GOOGLE_CHEZA_COMMON diff --git a/src/mainboard/google/cheza/Kconfig.name b/src/mainboard/google/cheza/Kconfig.name deleted file mode 100644 index fbfe4c919b..0000000000 --- a/src/mainboard/google/cheza/Kconfig.name +++ /dev/null @@ -1,4 +0,0 @@ - -config BOARD_GOOGLE_CHEZA - bool "Cheza" - select BOARD_GOOGLE_CHEZA_COMMON diff --git a/src/mainboard/google/cheza/Makefile.inc b/src/mainboard/google/cheza/Makefile.inc deleted file mode 100644 index 949d775624..0000000000 --- a/src/mainboard/google/cheza/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += boardid.c -bootblock-y += chromeos.c -bootblock-y += bootblock.c -bootblock-y += reset.c - -verstage-y += boardid.c -verstage-y += chromeos.c -verstage-y += reset.c - -romstage-y += boardid.c -romstage-y += chromeos.c -romstage-y += romstage.c -romstage-y += reset.c - -ramstage-y += boardid.c -ramstage-y += chromeos.c -ramstage-y += mainboard.c -ramstage-y += reset.c diff --git a/src/mainboard/google/cheza/board.h b/src/mainboard/google/cheza/board.h deleted file mode 100644 index 0207537800..0000000000 --- a/src/mainboard/google/cheza/board.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H -#define __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H - -#include -#include - -#define GPIO_EC_IN_RW GPIO(11) -#define GPIO_AP_EC_INT GPIO(122) -#define GPIO_AP_SUSPEND GPIO(126) -#define GPIO_WP_STATE GPIO(128) -#define GPIO_H1_AP_INT GPIO(129) - -void setup_chromeos_gpios(void); - -#endif /* ! __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H */ diff --git a/src/mainboard/google/cheza/board_info.txt b/src/mainboard/google/cheza/board_info.txt deleted file mode 100644 index 5e6e3b235a..0000000000 --- a/src/mainboard/google/cheza/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Vendor name: Google -Board name: Cheza Qualcomm SDM845 reference board -Category: eval -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/google/cheza/boardid.c b/src/mainboard/google/cheza/boardid.c deleted file mode 100644 index 2a3684646e..0000000000 --- a/src/mainboard/google/cheza/boardid.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -uint32_t board_id(void) -{ - const gpio_t pins[] = {[2] = GPIO(51), [1] = GPIO(62), [0] = GPIO(38)}; - static uint32_t id = UNDEFINED_STRAPPING_ID; - - if (id == UNDEFINED_STRAPPING_ID) - id = gpio_base2_value(pins, ARRAY_SIZE(pins)); - - return id; -} - -uint32_t ram_code(void) -{ - const gpio_t pins[] = {[1] = GPIO(147), [0] = GPIO(146)}; - static uint32_t id = UNDEFINED_STRAPPING_ID; - - if (id == UNDEFINED_STRAPPING_ID) - id = gpio_base2_value(pins, ARRAY_SIZE(pins)); - - return id; -} - -uint32_t sku_id(void) -{ - const gpio_t pins[] = {[1] = GPIO(113), [0] = GPIO(79)}; - static uint32_t id = UNDEFINED_STRAPPING_ID; - - if (id == UNDEFINED_STRAPPING_ID) - id = gpio_base2_value(pins, ARRAY_SIZE(pins)); - - return id; -} diff --git a/src/mainboard/google/cheza/bootblock.c b/src/mainboard/google/cheza/bootblock.c deleted file mode 100644 index 05e53a64bb..0000000000 --- a/src/mainboard/google/cheza/bootblock.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include "board.h" - -void bootblock_mainboard_init(void) -{ - setup_chromeos_gpios(); -} diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c deleted file mode 100644 index cb010919d9..0000000000 --- a/src/mainboard/google/cheza/chromeos.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include "board.h" - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP_STATE); -} - -void setup_chromeos_gpios(void) -{ - gpio_input_pullup(GPIO_EC_IN_RW); - gpio_input_pullup(GPIO_AP_EC_INT); - gpio_output(GPIO_AP_SUSPEND, 1); - gpio_input(GPIO_WP_STATE); - gpio_input_pullup(GPIO_H1_AP_INT); -} - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW), - "EC in RW"}, - {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), - "EC interrupt"}, - {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), - "TPM interrupt"}, - }; - - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd deleted file mode 100644 index 23d2d87ae2..0000000000 --- a/src/mainboard/google/cheza/chromeos.fmd +++ /dev/null @@ -1,42 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -FLASH@0x0 8M { - WP_RO 4M { - RO_SECTION 0x184000 { - BOOTBLOCK 96K - COREBOOT(CBFS) - #TODO: Move FMAP to 2M or 3M once FSG can be smaller - FMAP@0x180000 0x1000 - GBB 0x2f00 - RO_FRID 0x100 - } - RO_VPD(PRESERVE) 16K - RO_DDR_TRAINING(PRESERVE) 8K - RO_LIMITS_CFG(PRESERVE) 4K - RO_FSG(PRESERVE) - } - - RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K - RW_LIMITS_CFG(PRESERVE) 4K - RW_ELOG(PRESERVE) 4K - RW_SHARED 4K { - SHARED_DATA - } - - RW_SECTION_A 1280K { - VBLOCK_A 8K - FW_MAIN_A(CBFS) - RW_FWID_A 256 - } - - - RW_SECTION_B 1280K { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 256 - } - - RW_LEGACY(CBFS) -} diff --git a/src/mainboard/google/cheza/devicetree.cb b/src/mainboard/google/cheza/devicetree.cb deleted file mode 100644 index 717653b379..0000000000 --- a/src/mainboard/google/cheza/devicetree.cb +++ /dev/null @@ -1,5 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -chip soc/qualcomm/sdm845 - device cpu_cluster 0 on end -end diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c deleted file mode 100644 index e2d02de4b7..0000000000 --- a/src/mainboard/google/cheza/mainboard.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -static struct usb_board_data usb1_board_data = { - .pll_bias_control_2 = 0x28, - .imp_ctrl1 = 0x08, - .port_tune1 = 0x20, -}; - -static void setup_usb(void) -{ - /* - * Primary USB is used only for DP functionality on cheza platform. - * Hence Setting up only Secondary USB DWC3 controller. - */ - setup_usb_host1(&usb1_board_data); - - gpio_output(GPIO(120), 1); /* Deassert HUB_RST_L to enable hub. */ -} - -static void mainboard_init(struct device *dev) -{ - setup_usb(); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = &mainboard_init; -} - -struct chip_operations mainboard_ops = { - .name = CONFIG_MAINBOARD_PART_NUMBER, - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/google/cheza/reset.c b/src/mainboard/google/cheza/reset.c deleted file mode 100644 index 9b5810f20b..0000000000 --- a/src/mainboard/google/cheza/reset.c +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage), - but this works well enough for our purposes. */ -void do_board_reset(void) -{ - google_chromeec_reboot(0, EC_REBOOT_COLD, 0); -} diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c deleted file mode 100644 index e4f72a691f..0000000000 --- a/src/mainboard/google/cheza/romstage.c +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -static void prepare_usb(void) -{ - /* - * Do DWC3 core and phy reset. Kick these resets - * off early so they get at least 1ms to settle. - */ - reset_usb1(); -} - -void platform_romstage_main(void) -{ - prepare_usb(); - - /* QCLib: DDR init & train */ - qclib_load_and_run(); -} From 2b5bdaea630ecd35e22473816cd4000dd8f8916e Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 10 Nov 2020 16:02:16 -0800 Subject: [PATCH 198/262] Delete soc/qualcomm/sdm845 Work on this SoC was abandoned and never finished. It's not really usable in its current state, so let's get rid of it. Signed-off-by: Julius Werner Change-Id: I23453e3e47ac336ab61687004470e5e79172cafe Reviewed-on: https://review.coreboot.org/c/coreboot/+/47428 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Angel Pons --- src/soc/qualcomm/sdm845/Kconfig | 36 - src/soc/qualcomm/sdm845/Makefile.inc | 50 - src/soc/qualcomm/sdm845/aop_load_reset.c | 26 - src/soc/qualcomm/sdm845/bootblock.c | 13 - src/soc/qualcomm/sdm845/cbmem.c | 8 - src/soc/qualcomm/sdm845/clock.c | 218 ----- src/soc/qualcomm/sdm845/gpio.c | 58 -- .../qualcomm/sdm845/include/soc/addressmap.h | 31 - src/soc/qualcomm/sdm845/include/soc/aop.h | 8 - src/soc/qualcomm/sdm845/include/soc/clock.h | 194 ---- src/soc/qualcomm/sdm845/include/soc/efuse.h | 17 - src/soc/qualcomm/sdm845/include/soc/gpio.h | 339 ------- src/soc/qualcomm/sdm845/include/soc/mmu.h | 8 - src/soc/qualcomm/sdm845/include/soc/qspi.h | 108 --- src/soc/qualcomm/sdm845/include/soc/symbols.h | 17 - src/soc/qualcomm/sdm845/include/soc/usb.h | 83 -- src/soc/qualcomm/sdm845/memlayout.ld | 63 -- src/soc/qualcomm/sdm845/mmu.c | 26 - src/soc/qualcomm/sdm845/qclib.c | 36 - src/soc/qualcomm/sdm845/qspi.c | 293 ------ src/soc/qualcomm/sdm845/soc.c | 36 - src/soc/qualcomm/sdm845/spi.c | 23 - src/soc/qualcomm/sdm845/timer.c | 10 - src/soc/qualcomm/sdm845/uart_bitbang.c | 31 - src/soc/qualcomm/sdm845/usb.c | 899 ------------------ .../board-status.html/tohtml.sh | 3 - util/qualcomm/scripts/cmm/debug_cb_845.cmm | 113 --- 27 files changed, 2747 deletions(-) delete mode 100644 src/soc/qualcomm/sdm845/Kconfig delete mode 100644 src/soc/qualcomm/sdm845/Makefile.inc delete mode 100644 src/soc/qualcomm/sdm845/aop_load_reset.c delete mode 100644 src/soc/qualcomm/sdm845/bootblock.c delete mode 100644 src/soc/qualcomm/sdm845/cbmem.c delete mode 100644 src/soc/qualcomm/sdm845/clock.c delete mode 100644 src/soc/qualcomm/sdm845/gpio.c delete mode 100644 src/soc/qualcomm/sdm845/include/soc/addressmap.h delete mode 100644 src/soc/qualcomm/sdm845/include/soc/aop.h delete mode 100644 src/soc/qualcomm/sdm845/include/soc/clock.h delete mode 100644 src/soc/qualcomm/sdm845/include/soc/efuse.h delete mode 100644 src/soc/qualcomm/sdm845/include/soc/gpio.h delete mode 100644 src/soc/qualcomm/sdm845/include/soc/mmu.h delete mode 100644 src/soc/qualcomm/sdm845/include/soc/qspi.h delete mode 100644 src/soc/qualcomm/sdm845/include/soc/symbols.h delete mode 100644 src/soc/qualcomm/sdm845/include/soc/usb.h delete mode 100644 src/soc/qualcomm/sdm845/memlayout.ld delete mode 100644 src/soc/qualcomm/sdm845/mmu.c delete mode 100644 src/soc/qualcomm/sdm845/qclib.c delete mode 100644 src/soc/qualcomm/sdm845/qspi.c delete mode 100644 src/soc/qualcomm/sdm845/soc.c delete mode 100644 src/soc/qualcomm/sdm845/spi.c delete mode 100644 src/soc/qualcomm/sdm845/timer.c delete mode 100644 src/soc/qualcomm/sdm845/uart_bitbang.c delete mode 100644 src/soc/qualcomm/sdm845/usb.c delete mode 100644 util/qualcomm/scripts/cmm/debug_cb_845.cmm diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig deleted file mode 100644 index 2b9bef3bd5..0000000000 --- a/src/soc/qualcomm/sdm845/Kconfig +++ /dev/null @@ -1,36 +0,0 @@ - -config SOC_QUALCOMM_SDM845 - bool - default n - select ARCH_BOOTBLOCK_ARMV8_64 - select ARCH_RAMSTAGE_ARMV8_64 - select ARCH_ROMSTAGE_ARMV8_64 - select ARCH_VERSTAGE_ARMV8_64 - select GENERIC_GPIO_LIB - select ARM64_USE_ARCH_TIMER - select SOC_QUALCOMM_COMMON - select CACHE_MRC_SETTINGS - -if SOC_QUALCOMM_SDM845 - -config MEMLAYOUT_LD_FILE - string - default "src/soc/qualcomm/sdm845/memlayout.ld" - -config VBOOT - select VBOOT_SEPARATE_VERSTAGE - select VBOOT_RETURN_FROM_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_BOOTBLOCK - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN - -config SDM845_QSPI - bool - default y if COMMON_CBFS_SPI_WRAPPER - prompt "Build Flash Using SPI-NOR" - -config BOOT_DEVICE_SPI_FLASH_BUS - int - default 16 - -endif diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc deleted file mode 100644 index 4449a69023..0000000000 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ /dev/null @@ -1,50 +0,0 @@ - -ifeq ($(CONFIG_SOC_QUALCOMM_SDM845),y) - -################################################################################ -bootblock-y += bootblock.c -bootblock-y += spi.c -bootblock-y += mmu.c -bootblock-y += timer.c -bootblock-y += gpio.c -bootblock-y += clock.c -bootblock-$(CONFIG_SDM845_QSPI) += qspi.c - -################################################################################ -verstage-y += spi.c -verstage-y += timer.c -verstage-y += gpio.c -verstage-y += clock.c -verstage-$(CONFIG_SDM845_QSPI) += qspi.c - -################################################################################ -romstage-y += spi.c -romstage-y += cbmem.c -romstage-y += timer.c -romstage-y += gpio.c -romstage-y += clock.c -romstage-$(CONFIG_SDM845_QSPI) += qspi.c -romstage-y += usb.c -romstage-y += ../common/qclib.c -romstage-y += qclib.c -romstage-y += ../common/mmu.c -romstage-y += mmu.c - -################################################################################ -ramstage-y += soc.c -ramstage-y += spi.c -ramstage-y += timer.c -ramstage-y += gpio.c -ramstage-y += clock.c -ramstage-$(CONFIG_SDM845_QSPI) += qspi.c -ramstage-y += usb.c -ramstage-y += gpio.c -ramstage-y += clock.c -ramstage-y += aop_load_reset.c - -################################################################################ - -CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include -CPPFLAGS_common += -Isrc/soc/qualcomm/common/include - -endif diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c deleted file mode 100644 index eb90f86383..0000000000 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include - -void aop_fw_load_reset(void) -{ - bool aop_fw_entry; - - struct prog aop_fw_prog = - PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop"); - - if (prog_locate(&aop_fw_prog)) - die("SOC image: AOP_FW not found"); - - aop_fw_entry = selfload(&aop_fw_prog); - if (!aop_fw_entry) - die("SOC image: AOP load failed"); - - clock_reset_aop(); - - printk(BIOS_DEBUG, "\nSOC:AOP brought out of reset.\n"); -} diff --git a/src/soc/qualcomm/sdm845/bootblock.c b/src/soc/qualcomm/sdm845/bootblock.c deleted file mode 100644 index 9db015fa0b..0000000000 --- a/src/soc/qualcomm/sdm845/bootblock.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -void bootblock_soc_init(void) -{ - clock_init(); - sdm845_mmu_init(); - quadspi_init(25 * MHz); -} diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c deleted file mode 100644 index 4b9eb37861..0000000000 --- a/src/soc/qualcomm/sdm845/cbmem.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -void *cbmem_top_chipset(void) -{ - return (void *)((uintptr_t)4 * GiB); -} diff --git a/src/soc/qualcomm/sdm845/clock.c b/src/soc/qualcomm/sdm845/clock.c deleted file mode 100644 index 917d11f180..0000000000 --- a/src/soc/qualcomm/sdm845/clock.c +++ /dev/null @@ -1,218 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -#define DIV(div) (2*div - 1) - -#define AOP_LOADED_SIGNAL_FLAG 0x11223344 - -struct clock_config qup_cfg[] = { - { - .hz = 7372800, - .src = SRC_GPLL0_EVEN_300MHZ, - .div = DIV(1), - .m = 384, - .n = 15625, - .d_2 = 15625, - }, - { - .hz = 19200*KHz, - .src = SRC_XO_19_2MHZ, - .div = DIV(1), - } -}; - -struct clock_config qspi_core_cfg[] = { - { - .hz = 19200*KHz, - .src = SRC_XO_19_2MHZ, - .div = DIV(0), - }, - { - .hz = 100*MHz, - .src = SRC_GPLL0_MAIN_600MHZ, - .div = DIV(6), - }, - { - .hz = 150*MHz, - .src = SRC_GPLL0_MAIN_600MHZ, - .div = DIV(4), - }, - { - .hz = 300*MHz, - .src = SRC_GPLL0_MAIN_600MHZ, - .div = DIV(2), - } -}; - -static int clock_configure_gpll0(void) -{ - /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */ - setbits32(&gcc->gpll0.user_ctl, - 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT | - 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT | - 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT); - return 0; -} - -static int clock_configure_mnd(struct sdm845_clock *clk, uint32_t m, uint32_t n, - uint32_t d_2) -{ - setbits32(&clk->rcg.cfg, - RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); - - write32(&clk->m, m & CLK_CTL_RCG_MND_BMSK); - write32(&clk->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK); - write32(&clk->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK); - - return 0; -} - -static int clock_configure(struct sdm845_clock *clk, - struct clock_config *clk_cfg, - uint32_t hz, uint32_t num_perfs) -{ - uint32_t reg_val; - uint32_t idx; - - for (idx = 0; idx < num_perfs; idx++) - if (hz <= clk_cfg[idx].hz) - break; - - assert(hz == clk_cfg[idx].hz); - - reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | - (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); - - /* Set clock config */ - write32(&clk->rcg.cfg, reg_val); - - if (clk_cfg[idx].m != 0) - clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n, - clk_cfg[idx].d_2); - - /* Commit config to RCG*/ - setbits32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); - - return 0; -} - -static bool clock_is_off(u32 *cbcr_addr) -{ - return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK); -} - -static int clock_enable_vote(void *cbcr_addr, void *vote_addr, - uint32_t vote_bit) -{ - - /* Set clock vote bit */ - setbits32(vote_addr, BIT(vote_bit)); - - /* Ensure clock is enabled */ - while (clock_is_off(cbcr_addr)) - ; - - return 0; -} - -static int clock_enable(void *cbcr_addr) -{ - - /* Set clock enable bit */ - setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); - - /* Ensure clock is enabled */ - while (clock_is_off(cbcr_addr)) - ; - - return 0; -} - -void clock_reset_aop(void) -{ - /* Bring AOP out of RESET */ - uint32_t *mailbox; - mailbox = (uint32_t *)_aop_ss_msg_ram_drv15; - *mailbox = AOP_LOADED_SIGNAL_FLAG; -} - -void clock_configure_qspi(uint32_t hz) -{ - clock_configure((struct sdm845_clock *)&gcc->qspi_core, - qspi_core_cfg, hz, - ARRAY_SIZE(qspi_core_cfg)); - clock_enable(&gcc->qspi_cnoc_ahb_cbcr); - clock_enable(&gcc->qspi_core_cbcr); -} - -int clock_reset_bcr(void *bcr_addr, bool reset) -{ - struct sdm845_bcr *bcr = bcr_addr; - - if (reset) - setbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); - else - clrbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); - - return 0; -} - -void clock_configure_qup(int qup, uint32_t hz) -{ - int s = qup % QUP_WRAP0_S7; - struct sdm845_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? - (struct sdm845_qupv3_clock *)&gcc->qup_wrap0_s[s] : - (struct sdm845_qupv3_clock *)&gcc->qup_wrap1_s[s]; - clock_configure(&qup_clk->clk, qup_cfg, hz, ARRAY_SIZE(qup_cfg)); -} - -void clock_enable_qup(int qup) -{ - int s = qup % QUP_WRAP0_S7; - int clk_en_off = qup < QUP_WRAP1_S0 ? - QUPV3_WRAP0_CLK_ENA_S(s) : QUPV3_WRAP1_CLK_ENA_S(s); - struct sdm845_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? - &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; - - clock_enable_vote(&qup_clk->clk, &gcc->apcs_clk_br_en1, - clk_en_off); - -} - -void clock_init(void) -{ - - clock_configure_gpll0(); - - clock_enable_vote(&gcc->qup_wrap0_core_2x_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP0_CORE_2X_CLK_ENA); - clock_enable_vote(&gcc->qup_wrap0_core_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP0_CORE_CLK_ENA); - clock_enable_vote(&gcc->qup_wrap0_m_ahb_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP_0_M_AHB_CLK_ENA); - clock_enable_vote(&gcc->qup_wrap0_s_ahb_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP_0_S_AHB_CLK_ENA); - - clock_enable_vote(&gcc->qup_wrap1_core_2x_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP1_CORE_2X_CLK_ENA); - clock_enable_vote(&gcc->qup_wrap1_core_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP1_CORE_CLK_ENA); - clock_enable_vote(&gcc->qup_wrap1_m_ahb_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP_1_M_AHB_CLK_ENA); - clock_enable_vote(&gcc->qup_wrap1_s_ahb_cbcr, - &gcc->apcs_clk_br_en1, - QUPV3_WRAP_1_S_AHB_CLK_ENA); -} diff --git a/src/soc/qualcomm/sdm845/gpio.c b/src/soc/qualcomm/sdm845/gpio.c deleted file mode 100644 index 976e28a279..0000000000 --- a/src/soc/qualcomm/sdm845/gpio.c +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, - uint32_t drive_str, uint32_t enable) -{ - uint32_t reg_val; - struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; - - reg_val = ((enable & GPIO_CFG_OE_BMSK) << GPIO_CFG_OE_SHFT) | - ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) | - ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) | - ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT); - - write32(®s->cfg, reg_val); -} - -void gpio_set(gpio_t gpio, int value) -{ - struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; - write32(®s->in_out, (!!value) << GPIO_IO_OUT_SHFT); -} - -int gpio_get(gpio_t gpio) -{ - struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; - - return ((read32(®s->in_out) >> GPIO_IO_IN_SHFT) & - GPIO_IO_IN_BMSK); -} - -void gpio_input_pulldown(gpio_t gpio) -{ - gpio_configure(gpio, GPIO_FUNC_DISABLE, - GPIO_PULL_DOWN, GPIO_2MA, GPIO_DISABLE); -} - -void gpio_input_pullup(gpio_t gpio) -{ - gpio_configure(gpio, GPIO_FUNC_DISABLE, - GPIO_PULL_UP, GPIO_2MA, GPIO_DISABLE); -} - -void gpio_input(gpio_t gpio) -{ - gpio_configure(gpio, GPIO_FUNC_DISABLE, - GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE); -} - -void gpio_output(gpio_t gpio, int value) -{ - gpio_set(gpio, value); - gpio_configure(gpio, GPIO_FUNC_DISABLE, - GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); -} diff --git a/src/soc/qualcomm/sdm845/include/soc/addressmap.h b/src/soc/qualcomm/sdm845/include/soc/addressmap.h deleted file mode 100644 index aa80a1439e..0000000000 --- a/src/soc/qualcomm/sdm845/include/soc/addressmap.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__ -#define __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__ - -#define QSPI_BASE 0x88DF000 -#define TLMM_EAST_TILE_BASE 0x03500000 -#define TLMM_NORTH_TILE_BASE 0x03900000 -#define TLMM_SOUTH_TILE_BASE 0x03D00000 -#define GCC_BASE 0x00100000 - -/* - * USB BASE ADDRESSES - */ -#define QFPROM_BASE 0x00780000 -#define QUSB_PRIM_PHY_BASE 0x088e2000 -#define QUSB_PRIM_PHY_DIG_BASE 0x088e2200 -#define QUSB_SEC_PHY_BASE 0x088e3000 -#define QUSB_SEC_PHY_DIG_BASE 0x088e3200 -#define QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000 -#define QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200 -#define QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400 -#define QMP_PHY_PCS_REG_BASE 0x088e9c00 -#define QMP_UNIPHY_QSERDES_COM_REG_BASE 0x088eb000 -#define QMP_UNIPHY_QSERDES_TX_REG_BASE 0x088eb200 -#define QMP_UNIPHY_QSERDES_RX_REG_BASE 0x088eb400 -#define QMP_UNIPHY_PCS_REG_BASE 0x088eb800 -#define USB_HOST0_DWC3_BASE 0x0a60c100 -#define USB_HOST1_DWC3_BASE 0x0a80c100 - -#endif /* __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sdm845/include/soc/aop.h b/src/soc/qualcomm/sdm845/include/soc/aop.h deleted file mode 100644 index 2f82747486..0000000000 --- a/src/soc/qualcomm/sdm845/include/soc/aop.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_QUALCOMM_SDM845_AOP_H__ -#define _SOC_QUALCOMM_SDM845_AOP_H__ - -void aop_fw_load_reset(void); - -#endif // _SOC_QUALCOMM_SDM845_AOP_H__ diff --git a/src/soc/qualcomm/sdm845/include/soc/clock.h b/src/soc/qualcomm/sdm845/include/soc/clock.h deleted file mode 100644 index 78d5dfd22d..0000000000 --- a/src/soc/qualcomm/sdm845/include/soc/clock.h +++ /dev/null @@ -1,194 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -#ifndef __SOC_QUALCOMM_SDM845_CLOCK_H__ -#define __SOC_QUALCOMM_SDM845_CLOCK_H__ - -#define QUPV3_WRAP_0_M_AHB_CLK_ENA 6 -#define QUPV3_WRAP_0_S_AHB_CLK_ENA 7 -#define QUPV3_WRAP0_CORE_2X_CLK_ENA 9 -#define QUPV3_WRAP0_CORE_CLK_ENA 8 -#define QUPV3_WRAP1_CORE_2X_CLK_ENA 18 -#define QUPV3_WRAP1_CORE_CLK_ENA 19 -#define QUPV3_WRAP_1_M_AHB_CLK_ENA 20 -#define QUPV3_WRAP_1_S_AHB_CLK_ENA 21 -#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx) -#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx) - -#define GPLL0_EVEN_HZ (300*MHz) -#define GPLL0_MAIN_HZ (600*MHz) -#define QUP_WRAP_CORE_2X_19_2MHZ (19200*KHz) - -#define SRC_XO_19_2MHZ 0 -#define SRC_GPLL0_MAIN_600MHZ 1 -#define SRC_GPLL0_EVEN_300MHZ 6 - -#define AOP_RESET_SHFT 0 -#define RCG_MODE_DUAL_EDGE 2 - -struct sdm845_rcg { - u32 cmd; - u32 cfg; -}; - -struct sdm845_clock { - u32 cbcr; - struct sdm845_rcg rcg; - u32 m; - u32 n; - u32 d_2; -}; - -struct sdm845_qupv3_clock { - struct sdm845_clock clk; - u8 _res[0x130 - 0x18]; -}; - -struct sdm845_gpll { - u32 mode; - u32 l_val; - u32 cal_l_val; - u32 user_ctl; - u32 user_ctl_u; - u32 config_ctl; - u32 config_ctl_u; - u32 test_ctl; - u32 test_ctl_u; - u8 _res[0x1000 - 0x24]; -}; - -struct sdm845_gcc { - struct sdm845_gpll gpll0; - u8 _res0[0xf000 - 0x1000]; - u32 usb30_prim_bcr; - u8 _res1[0x10000 - 0xf004]; - u32 usb30_sec_bcr; - u8 _res2[0x12000 - 0x10004]; - u32 qusb2phy_prim_bcr; - u32 qusb2phy_sec_bcr; - u8 _res3[0x17000 - 0x12008]; - u32 qup_wrap0_bcr; - u32 qup_wrap0_m_ahb_cbcr; - u32 qup_wrap0_s_ahb_cbcr; - u32 qup_wrap0_core_cbcr; - u32 qup_wrap0_core_cdivr; - u32 qup_wrap0_core_2x_cbcr; - struct sdm845_rcg qup_wrap0_core_2x; - u8 _res4[0x17030 - 0x17020]; - struct sdm845_qupv3_clock qup_wrap0_s[8]; - u8 _res5[0x18000 - 0x179b0]; - u32 qup_wrap1_bcr; - u32 qup_wrap1_core_2x_cbcr; - u32 qup_wrap1_core_cbcr; - u32 qup_wrap1_m_ahb_cbcr; - u32 qup_wrap1_s_ahb_cbcr; - struct sdm845_qupv3_clock qup_wrap1_s[8]; - u32 qup_wrap1_core_cdivr; - u8 _res6[0x4B000 - 0x18998]; - u32 qspi_cnoc_ahb_cbcr; - u32 qspi_core_cbcr; - struct sdm845_rcg qspi_core; - u8 _res7[0x50000-0x4b010]; - u32 usb3_phy_prim_bcr; - u32 usb3phy_phy_prim_bcr; - u32 usb3_dp_phy_prim_bcr; - u32 usb3_phy_sec_bcr; - u32 usb3phy_phy_sec_bcr; - u8 _res8[0x5200c-0x50014]; - u32 apcs_clk_br_en1; - u8 _res9[0x1000000-0x52010]; -}; -check_member(sdm845_gcc, usb30_prim_bcr, 0xf000); -check_member(sdm845_gcc, usb30_sec_bcr, 0x10000); -check_member(sdm845_gcc, qusb2phy_prim_bcr, 0x12000); -check_member(sdm845_gcc, qusb2phy_sec_bcr, 0x12004); -check_member(sdm845_gcc, usb3phy_phy_prim_bcr, 0x50004); -check_member(sdm845_gcc, usb3_phy_prim_bcr, 0x50000); -check_member(sdm845_gcc, usb3_phy_sec_bcr, 0x5000c); -check_member(sdm845_gcc, usb3phy_phy_sec_bcr, 0x50010); -check_member(sdm845_gcc, apcs_clk_br_en1, 0x5200c); - -enum clk_ctl_gpll_user_ctl { - CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2, - CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0, - CLK_CTL_GPLL_PLLOUT_EVEN_SHFT = 1, - CLK_CTL_GPLL_PLLOUT_ODD_SHFT = 2 -}; - -enum clk_ctl_cfg_rcgr { - CLK_CTL_CFG_HW_CTL_BMSK = 0x100000, - CLK_CTL_CFG_HW_CTL_SHFT = 20, - CLK_CTL_CFG_MODE_BMSK = 0x3000, - CLK_CTL_CFG_MODE_SHFT = 12, - CLK_CTL_CFG_SRC_SEL_BMSK = 0x700, - CLK_CTL_CFG_SRC_SEL_SHFT = 8, - CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F, - CLK_CTL_CFG_SRC_DIV_SHFT = 0 -}; - -enum clk_ctl_cmd_rcgr { - CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000, - CLK_CTL_CMD_ROOT_OFF_SHFT = 31, - CLK_CTL_CMD_ROOT_EN_BMSK = 0x2, - CLK_CTL_CMD_ROOT_EN_SHFT = 1, - CLK_CTL_CMD_UPDATE_BMSK = 0x1, - CLK_CTL_CMD_UPDATE_SHFT = 0 -}; - -enum clk_ctl_cbcr { - CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000, - CLK_CTL_CBC_CLK_OFF_SHFT = 31, - CLK_CTL_CBC_CLK_EN_BMSK = 0x1, - CLK_CTL_CBC_CLK_EN_SHFT = 0 -}; - -enum clk_ctl_rcg_mnd { - CLK_CTL_RCG_MND_BMSK = 0xFFFF, - CLK_CTL_RCG_MND_SHFT = 0, -}; - -enum clk_ctl_bcr { - CLK_CTL_BCR_BLK_ARES_BMSK = 0x1, - CLK_CTL_BCR_BLK_ARES_SHFT = 0, -}; - -enum clk_qup { - QUP_WRAP0_S0, - QUP_WRAP0_S1, - QUP_WRAP0_S2, - QUP_WRAP0_S3, - QUP_WRAP0_S4, - QUP_WRAP0_S5, - QUP_WRAP0_S6, - QUP_WRAP0_S7, - QUP_WRAP1_S0, - QUP_WRAP1_S1, - QUP_WRAP1_S2, - QUP_WRAP1_S3, - QUP_WRAP1_S4, - QUP_WRAP1_S5, - QUP_WRAP1_S6, - QUP_WRAP1_S7 -}; - -struct clock_config { - uint32_t hz; - uint8_t src; - uint8_t div; - uint16_t m; - uint16_t n; - uint16_t d_2; -}; - -static struct sdm845_gcc *const gcc = (void *)GCC_BASE; - -void clock_init(void); -void clock_reset_aop(void); -void clock_configure_qspi(uint32_t hz); -int clock_reset_bcr(void *bcr_addr, bool reset); -void clock_configure_qup(int qup, uint32_t hz); -void clock_enable_qup(int qup); - -#endif // __SOC_QUALCOMM_SDM845_CLOCK_H__ diff --git a/src/soc/qualcomm/sdm845/include/soc/efuse.h b/src/soc/qualcomm/sdm845/include/soc/efuse.h deleted file mode 100644 index 112ffd3c20..0000000000 --- a/src/soc/qualcomm/sdm845/include/soc/efuse.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ -#define __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ - -/** - * USB EFUSE registers - */ -struct qfprom_corr { - u8 rsvd[0x41E8 - 0x0]; - u32 qusb_hstx_trim_lsb; - u32 qusb_hstx_trim_msb; -}; - -check_member(qfprom_corr, qusb_hstx_trim_lsb, 0x41E8); -check_member(qfprom_corr, qusb_hstx_trim_msb, 0x41EC); -#endif /* __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sdm845/include/soc/gpio.h b/src/soc/qualcomm/sdm845/include/soc/gpio.h deleted file mode 100644 index 04f92d6155..0000000000 --- a/src/soc/qualcomm/sdm845/include/soc/gpio.h +++ /dev/null @@ -1,339 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_QUALCOMM_SDM845_GPIO_H_ -#define _SOC_QUALCOMM_SDM845_GPIO_H_ - -#include -#include - -typedef struct { - u32 addr; -} gpio_t; - -#define TLMM_TILE_SIZE 0x00400000 -#define TLMM_GPIO_OFF_DELTA 0x00001000 -#define TLMM_GPIO_TILE_NUM 3 - -#define TLMM_GPIO_IN_OUT_OFF 0x4 -#define TLMM_GPIO_ID_STATUS_OFF 0x10 - -#define GPIO_FUNC_ENABLE 1 -#define GPIO_FUNC_DISABLE 0 - -/* GPIO TLMM: Direction */ -#define GPIO_INPUT 0 -#define GPIO_OUTPUT 1 - -/* GPIO TLMM: Pullup/Pulldown */ -#define GPIO_NO_PULL 0 -#define GPIO_PULL_DOWN 1 -#define GPIO_KEEPER 2 -#define GPIO_PULL_UP 3 - -/* GPIO TLMM: Drive Strength */ -#define GPIO_2MA 0 -#define GPIO_4MA 1 -#define GPIO_6MA 2 -#define GPIO_8MA 3 -#define GPIO_10MA 4 -#define GPIO_12MA 5 -#define GPIO_14MA 6 -#define GPIO_16MA 7 - -/* GPIO TLMM: Status */ -#define GPIO_DISABLE 0 -#define GPIO_ENABLE 1 - -/* GPIO TLMM: Mask */ -#define GPIO_CFG_PULL_BMSK 0x3 -#define GPIO_CFG_FUNC_BMSK 0xF -#define GPIO_CFG_DRV_BMSK 0x7 -#define GPIO_CFG_OE_BMSK 0x1 - -/* GPIO TLMM: Shift */ -#define GPIO_CFG_PULL_SHFT 0 -#define GPIO_CFG_FUNC_SHFT 2 -#define GPIO_CFG_DRV_SHFT 6 -#define GPIO_CFG_OE_SHFT 9 - -/* GPIO IO: Mask */ -#define GPIO_IO_IN_BMSK 0x1 -#define GPIO_IO_OUT_BMSK 0x1 - -/* GPIO IO: Shift */ -#define GPIO_IO_IN_SHFT 0 -#define GPIO_IO_OUT_SHFT 1 - -/* GPIO ID STATUS: Mask */ -#define GPIO_ID_STATUS_BMSK 0x1 - -/* GPIO MAX Valid # */ -#define GPIO_NUM_MAX 149 - -#define GPIO_FUNC_GPIO 0 - -#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR}) - -#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ -GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \ -GPIO##index##_FUNC_##func1 = 1, \ -GPIO##index##_FUNC_##func2 = 2, \ -GPIO##index##_FUNC_##func3 = 3, \ -GPIO##index##_FUNC_##func4 = 4, \ -GPIO##index##_FUNC_##func5 = 5, \ -GPIO##index##_FUNC_##func6 = 6, \ -GPIO##index##_FUNC_##func7 = 7 - -enum { - PIN(0, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(1, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(2, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(3, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(4, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(5, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(6, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(7, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(8, EAST, QUP_L4_0_CS, GP_PDM_MIRB, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(9, EAST, QUP_L5_0_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(10, EAST, MDP_VSYNC_P_MIRA, QUP_L6_0_CS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(11, EAST, MDP_VSYNC_S_MIRA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(12, SOUTH, MDP_VSYNC_E, RES_2, TSIF1_SYNC, RES_4, RES_5, - RES_6, RES_7), - PIN(13, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(14, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(15, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(16, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(17, SOUTH, CCI_I2C_SDA0, QUP_L0, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(18, SOUTH, CCI_I2C_SCL0, QUP_L1, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(19, SOUTH, CCI_I2C_SDA1, QUP_L2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(20, SOUTH, CCI_I2C_SCL1, QUP_L3, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(21, SOUTH, CCI_TIMER0, GCC_GP2_CLK_MIRB, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(22, SOUTH, CCI_TIMER1, GCC_GP3_CLK_MIRB, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(23, SOUTH, CCI_TIMER2, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(24, SOUTH, CCI_TIMER3, CCI_ASYNC_IN1, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(25, SOUTH, CCI_TIMER4, CCI_ASYNC_IN2, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(26, SOUTH, CCI_ASYNC_IN0, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(27, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(28, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(29, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(30, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(31, NORTH, QUP_L0, QUP_L2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(32, NORTH, QUP_L1, QUP_L3, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(33, NORTH, QUP_L2, QUP_L0, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(34, NORTH, QUP_L3, QUP_L1, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(35, SOUTH, PCI_E0_RST_N, QUP_L4_1_CS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(36, SOUTH, PCI_E0_CLKREQN, QUP_L5_1_CS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(37, SOUTH, QUP_L6_1_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(38, NORTH, USB_PHY_PS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(39, EAST, LPASS_SLIMBUS_DATA2, RES_2, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(40, SOUTH, SD_WRITE_PROTECT, TSIF1_ERROR, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(41, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(42, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(43, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(44, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(45, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(46, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(47, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(48, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(49, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(50, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(51, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(52, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(53, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(54, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(55, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(56, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(57, NORTH, QUA_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(58, NORTH, QUA_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(59, NORTH, QUA_MI2S_WS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(60, NORTH, QUA_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(61, NORTH, QUA_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(62, NORTH, QUA_MI2S_DATA2, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(63, NORTH, QUA_MI2S_DATA3, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(64, NORTH, PRI_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(65, NORTH, PRI_MI2S_SCK, QUP_L0, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(66, NORTH, PRI_MI2S_WS, QUP_L1, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(67, NORTH, PRI_MI2S_DATA0, QUP_L2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(68, NORTH, PRI_MI2S_DATA1, QUP_L3, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(69, EAST, SPKR_I2S_MCLK, AUDIO_REF_CLK, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(70, EAST, LPASS_SLIMBUS_CLK, SPKR_I2S_SCK, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(71, EAST, LPASS_SLIMBUS_DATA0, SPKR_I2S_DATA_OUT, RES_3, - RES_4, RES_5, RES_6, RES_7), - PIN(72, EAST, LPASS_SLIMBUS_DATA1, SPKR_I2S_WS, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(73, EAST, BTFM_SLIMBUS_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(74, EAST, BTFM_SLIMBUS_CLK, TER_MI2S_MCLK, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(75, EAST, TER_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(76, EAST, TER_MI2S_WS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(77, EAST, TER_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(78, EAST, TER_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(79, NORTH, SEC_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(80, NORTH, SEC_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(81, NORTH, SEC_MI2S_WS, QUP_L0, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(82, NORTH, SEC_MI2S_DATA0, QUP_L1, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(83, NORTH, SEC_MI2S_DATA1, QUP_L2, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(84, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(85, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(86, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(87, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(88, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(89, SOUTH, TSIF1_CLK, QUP_L0, QSPI_CS_N_1, RES_4, RES_5, - RES_6, RES_7), - PIN(90, SOUTH, TSIF1_EN, MDP_VSYNC0_OUT, QUP_L1, QSPI_CS_N_0, - MDP_VSYNC1_OUT, MDP_VSYNC2_OUT, MDP_VSYNC3_OUT), - PIN(91, SOUTH, TSIF1_DATA, SDC4_CMD, QUP_L2, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(92, SOUTH, TSIF2_ERROR, SDC4_DATA, QUP_L3, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(93, SOUTH, TSIF2_CLK, SDC4_CLK, QUP_L0, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(94, SOUTH, TSIF2_EN, SDC4_DATA, QUP_L1, QSPI_DATA, - RES_5, RES_6, RES_7), - PIN(95, SOUTH, TSIF2_DATA, SDC4_DATA, QUP_L2, QSPI_CLK, - RES_5, RES_6, RES_7), - PIN(96, SOUTH, TSIF2_SYNC, SDC4_DATA, QUP_L3, RES_4, - RES_5, RES_6, RES_7), - PIN(97, NORTH, RFFE6_CLK, GRFC37, MDP_VSYNC_P_MIRB, - RES_4, RES_5, RES_6, RES_7), - PIN(98, NORTH, RFFE6_DATA, MDP_VSYNC_S_MIRB, RES_3, - RES_4, RES_5, RES_6, RES_7), - PIN(99, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(100, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(101, NORTH, GRFC4, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(102, NORTH, PCI_E1_RST_N, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(103, NORTH, PCI_E1_CLKREQN, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(104, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(105, NORTH, UIM2_DATA, QUP_L0, QUP_L4_8_CS, RES_4, RES_5, - RES_6, RES_7), - PIN(106, NORTH, UIM2_CLK, QUP_L1, QUP_L5_8_CS, RES_4, RES_5, - RES_6, RES_7), - PIN(107, NORTH, UIM2_RESET, QUP_L2, QUP_L6_8_CS, RES_4, RES_5, - RES_6, RES_7), - PIN(108, NORTH, UIM2_PRESENT, QUP_L3, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(109, NORTH, UIM1_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(110, NORTH, UIM1_CLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(111, NORTH, UIM1_RESET, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(112, NORTH, UIM1_PRESENT, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(113, NORTH, UIM_BATT_ALARM, EDP_HOT_PLUG_DETECT, RES_3, - RES_4, RES_5, RES_6, RES_7), - PIN(114, NORTH, GRFC8, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRE, - RES_5, RES_6, RES_7), - PIN(115, NORTH, GRFC9, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRF, - RES_5, RES_6, RES_7), - PIN(116, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(117, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(118, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(119, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(120, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(121, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(122, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(123, EAST, QUP_L4_9_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(124, EAST, QUP_L5_9_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(125, EAST, QUP_L6_9_CS, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(126, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(127, NORTH, GRFC3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(128, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRB, RES_4, - RES_5, RES_6, RES_7), - PIN(129, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRC, RES_4, - RES_5, RES_6, RES_7), - PIN(130, NORTH, QLINK_REQUEST, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(131, NORTH, QLINK_ENABLE, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(132, NORTH, GRFC2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(133, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(134, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(135, NORTH, GRFC0, PA_INDICATOR_1_OR_2, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(136, NORTH, GRFC1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(137, NORTH, RFFE3_DATA, GRFC35, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(138, NORTH, RFFE3_CLK, GRFC32, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(139, NORTH, RFFE4_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(140, NORTH, RFFE4_CLK, GRFC36, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(141, NORTH, RFFE5_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(142, NORTH, RFFE5_CLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(143, NORTH, GRFC5, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRD, - RES_5, RES_6, RES_7), - PIN(144, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(145, NORTH, RES_1, GPS_TX_AGGRESSOR_MIRA, RES_3, RES_4, - RES_5, RES_6, RES_7), - PIN(146, NORTH, RFFE2_DATA, GRFC34, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(147, NORTH, RFFE2_CLK, GRFC33, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(148, NORTH, RFFE1_DATA, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), - PIN(149, NORTH, RFFE1_CLK, RES_2, RES_3, RES_4, RES_5, - RES_6, RES_7), -}; - -struct tlmm_gpio { - uint32_t cfg; - uint32_t in_out; -}; - -void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, - uint32_t drive_str, uint32_t enable); - -#endif // _SOC_QUALCOMM_SDM845_GPIO_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/mmu.h b/src/soc/qualcomm/sdm845/include/soc/mmu.h deleted file mode 100644 index 868a6c8105..0000000000 --- a/src/soc/qualcomm/sdm845/include/soc/mmu.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_QUALCOMM_SDM845_MMU_H__ -#define _SOC_QUALCOMM_SDM845_MMU_H__ - -void sdm845_mmu_init(void); - -#endif // _SOC_QUALCOMM_SDM845_MMU_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/qspi.h b/src/soc/qualcomm/sdm845/include/soc/qspi.h deleted file mode 100644 index 5357e48975..0000000000 --- a/src/soc/qualcomm/sdm845/include/soc/qspi.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include -#include - -#ifndef __SOC_QUALCOMM_SDM845_QSPI_H__ -#define __SOC_QUALCOMM_SDM845_QSPI_H__ - -struct sdm845_qspi_regs { - u32 mstr_cfg; - u32 ahb_mstr_cfg; - u32 reserve_0; - u32 mstr_int_en; - u32 mstr_int_sts; - u32 pio_xfer_ctrl; - u32 pio_xfer_cfg; - u32 pio_xfer_sts; - u32 pio_dataout_1byte; - u32 pio_dataout_4byte; - u32 rd_fifo_cfg; - u32 rd_fifo_sts; - u32 rd_fifo_rst; - u32 reserve_1[3]; - u32 next_dma_desc_addr; - u32 current_dma_desc_addr; - u32 current_mem_addr; - u32 hw_version; - u32 rd_fifo[16]; -}; - -check_member(sdm845_qspi_regs, rd_fifo, 0x50); -static struct sdm845_qspi_regs * const sdm845_qspi = (void *) QSPI_BASE; - -// MSTR_CONFIG register - -#define TX_DATA_OE_DELAY_SHIFT 24 -#define TX_DATA_OE_DELAY_MASK (0x3 << TX_DATA_OE_DELAY_SHIFT) -#define TX_CS_N_DELAY_SHIFT 22 -#define TX_CS_N_DELAY_MASK (0x3 << TX_CS_N_DELAY_SHIFT) -#define TX_CLK_DELAY_SHIFT 20 -#define TX_CLK_DELAY_MASK (0x3 << TX_CLK_DELAY_SHIFT) -#define TX_DATA_DELAY_SHIFT 18 -#define TX_DATA_DELAY_MASK (0x3 << TX_DATA_DELAY_SHIFT) -#define LPA_BASE_SHIFT 14 -#define LPA_BASE_MASK (0xF << LPA_BASE_SHIFT) -#define SBL_EN BIT(13) -#define CHIP_SELECT_NUM BIT(12) -#define SPI_MODE_SHIFT 10 -#define SPI_MODE_MASK (0x3 << SPI_MODE_SHIFT) -#define BIG_ENDIAN_MODE BIT(9) -#define DMA_ENABLE BIT(8) -#define PIN_WPN BIT(7) -#define PIN_HOLDN BIT(6) -#define FB_CLK_EN BIT(4) -#define FULL_CYCLE_MODE BIT(3) - -// MSTR_INT_ENABLE and MSTR_INT_STATUS register - -#define DMA_CHAIN_DONE BIT(31) -#define TRANSACTION_DONE BIT(16) -#define WRITE_FIFO_OVERRUN BIT(11) -#define WRITE_FIFO_FULL BIT(10) -#define HRESP_FROM_NOC_ERR BIT(3) -#define RESP_FIFO_RDY BIT(2) -#define RESP_FIFO_NOT_EMPTY BIT(1) -#define RESP_FIFO_UNDERRUN BIT(0) - -// PIO_TRANSFER_CONFIG register - -#define TRANSFER_FRAGMENT BIT(8) -#define MULTI_IO_MODE_SHIFT 1 -#define MULTI_IO_MODE_MASK (0x7 << MULTI_IO_MODE_SHIFT) -#define TRANSFER_DIRECTION BIT(0) - -// PIO_TRANSFER_STATUS register - -#define WR_FIFO_BYTES_SHIFT 16 -#define WR_FIFO_BYTES_MASK (0xFFFF << WR_FIFO_BYTES_SHIFT) - -// RD_FIFO_CONFIG register - -#define CONTINUOUS_MODE BIT(0) - -// RD_FIFO_STATUS register - -#define FIFO_EMPTY BIT(11) -#define WR_CNTS_SHIFT 4 -#define WR_CNTS_MASK (0x7F << WR_CNTS_SHIFT) -#define RDY_64BYTE BIT(3) -#define RDY_32BYTE BIT(2) -#define RDY_16BYTE BIT(1) -#define FIFO_RDY BIT(0) - -// RD_FIFO_RESET register - -#define RESET_FIFO BIT(0) - -#define QSPI_MAX_PACKET_COUNT 0xFFC0 - -void quadspi_init(uint32_t hz); -int sdm845_claim_bus(const struct spi_slave *slave); -int sdm845_setup_bus(const struct spi_slave *slave); -void sdm845_release_bus(const struct spi_slave *slave); -int sdm845_xfer(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes); -int sdm845_xfer_dual(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes); -#endif /* __SOC_QUALCOMM_SDM845_QSPI_H__ */ diff --git a/src/soc/qualcomm/sdm845/include/soc/symbols.h b/src/soc/qualcomm/sdm845/include/soc/symbols.h deleted file mode 100644 index 64482c73d2..0000000000 --- a/src/soc/qualcomm/sdm845/include/soc/symbols.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_QUALCOMM_SDM845_SYMBOLS_H_ -#define _SOC_QUALCOMM_SDM845_SYMBOLS_H_ - -#include - -DECLARE_REGION(ssram) -DECLARE_REGION(bsram) -DECLARE_REGION(dram_reserved) -DECLARE_REGION(dcb); -DECLARE_REGION(pmic); -DECLARE_REGION(limits_cfg); -DECLARE_REGION(aop); -DECLARE_REGION(aop_ss_msg_ram_drv15); - -#endif // _SOC_QUALCOMM_SDM845_SYMBOLS_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/usb.h b/src/soc/qualcomm/sdm845/include/soc/usb.h deleted file mode 100644 index 5ce8f805ca..0000000000 --- a/src/soc/qualcomm/sdm845/include/soc/usb.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#include - -#ifndef _SDM845_USB_H_ -#define _SDM845_USB_H_ - -/* QSCRATCH_GENERAL_CFG register bit offset */ -#define PIPE_UTMI_CLK_SEL BIT(0) -#define PIPE3_PHYSTATUS_SW BIT(3) -#define PIPE_UTMI_CLK_DIS BIT(8) - -/* Global USB3 Control Registers */ -#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18) -#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27) -#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) -#define DWC3_GCTL_PRTCAP_OTG 3 -#define DWC3_GCTL_PRTCAP_HOST 1 - -/* Global USB2 PHY Configuration Register */ -#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) -#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) -#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) -#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) -#define USBTRDTIM_UTMI_8_BIT 9 -#define UTMI_PHYIF_8_BIT 0 - -#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) -#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) -#define DWC3_GCTL_DISSCRAMBLE (1 << 3) -#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) -#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) - -#define PORT_TUNE1_MASK 0xf0 - -/* QUSB2PHY_PWR_CTRL1 register related bits */ -#define POWER_DOWN BIT(0) - -/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */ -#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4 - -/* STAT5 register bits */ -#define VSTATUS_PLL_LOCK_STATUS_MASK BIT(0) - -/* QUSB PHY register values */ -#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03 -#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c -#define QUSB2PHY_PLL_CMODE 0x80 -#define QUSB2PHY_PLL_LOCK_DELAY 0x0a -#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19 -#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x40 -#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x20 -#define QUSB2PHY_PWR_CTRL2 0x21 -#define QUSB2PHY_IMP_CTRL1 0x0 -#define QUSB2PHY_IMP_CTRL2 0x58 -#define QUSB2PHY_PORT_TUNE1 0x30 -#define QUSB2PHY_PORT_TUNE2 0x29 -#define QUSB2PHY_PORT_TUNE3 0xca -#define QUSB2PHY_PORT_TUNE4 0x04 -#define QUSB2PHY_PORT_TUNE5 0x03 -#define QUSB2PHY_CHG_CTRL2 0x0 - -/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */ -#define USB3_PCS_PHYSTATUS BIT(6) - -struct usb_board_data { - /* Register values going to override from the boardfile */ - u32 pll_bias_control_2; - u32 imp_ctrl1; - u32 port_tune1; -}; - -struct qmp_phy_init_tbl { - u32 *address; - u32 val; -}; - -void setup_usb_host0(struct usb_board_data *data); -void setup_usb_host1(struct usb_board_data *data); -/* Call reset_ before setup_ */ -void reset_usb0(void); -void reset_usb1(void); - -#endif /* _SDM845_USB_H_ */ diff --git a/src/soc/qualcomm/sdm845/memlayout.ld b/src/soc/qualcomm/sdm845/memlayout.ld deleted file mode 100644 index 30b4920288..0000000000 --- a/src/soc/qualcomm/sdm845/memlayout.ld +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -/* SYSTEM_IMEM : 0x14680000 - 0x146C0000 */ -#define SSRAM_START(addr) SYMBOL(ssram, addr) -#define SSRAM_END(addr) SYMBOL(essram, addr) - -/* BOOT_IMEM : 0x14800000 - 0x14980000 */ -#define BSRAM_START(addr) SYMBOL(bsram, addr) -#define BSRAM_END(addr) SYMBOL(ebsram, addr) - -/* AOP : 0x0B000000 - 0x0B100000 */ -#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) -#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) - -/* AOPMSG : 0x0C300000 - 0x0C400000 */ -#define AOPMSG_START(addr) SYMBOL(aopmsg, addr) -#define AOPMSG_END(addr) SYMBOL(eaopmsg, addr) - -SECTIONS -{ - AOPSRAM_START(0x0B000000) - REGION(aop, 0x0B000000, 0x100000, 4096) - AOPSRAM_END(0x0B100000) - - AOPMSG_START(0x0C300000) - REGION(aop_ss_msg_ram_drv15, 0x0C3F0000, 0x400, 0x100) - AOPMSG_END(0x0C400000) - - SSRAM_START(0x14680000) - OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) - DMA_COHERENT(0x14699000, 8K) - REGION(qcsdi, 0x146AC000, 44K, 4K) - SSRAM_END(0x146C0000) - - BSRAM_START(0x14800000) - REGION(fw_reserved2, 0x14800000, 0x16000, 0x1000) - BOOTBLOCK(0x14816000, 40K) - TTB(0x14820000, 56K) - VBOOT2_WORK(0x1482E000, 12K) - STACK(0x14832000, 16K) - TIMESTAMP(0x14836000, 1K) - PRERAM_CBMEM_CONSOLE(0x14836400, 32K) - PRERAM_CBFS_CACHE(0x1483E400, 70K) - FMAP_CACHE(0x1484FC00, 2K) - REGION(bsram_unused, 0x14850400, 0x9DB00, 0x100) - REGION(ddr_information, 0x148EDF00, 256, 256) - REGION(limits_cfg, 0x148EE000, 4K, 4K) - REGION(qclib_serial_log, 0x148EF000, 4K, 4K) - REGION(ddr_training, 0x148F0000, 8K, 4K) - REGION(qclib, 0x148F2000, 512K, 4K) - REGION(dcb, 0x14972000, 16K, 4K) - REGION(pmic, 0x14976000, 40K, 4K) - BSRAM_END(0x14980000) - - DRAM_START(0x80000000) - /* Various hardware/software subsystems make use of this area */ - REGION(dram_reserved, 0x85000000, 0x1A800000, 0x1000) - POSTRAM_CBFS_CACHE(0x9F800000, 384K) - RAMSTAGE(0x9F860000, 2M) -} diff --git a/src/soc/qualcomm/sdm845/mmu.c b/src/soc/qualcomm/sdm845/mmu.c deleted file mode 100644 index 7af4f95675..0000000000 --- a/src/soc/qualcomm/sdm845/mmu.c +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -void sdm845_mmu_init(void) -{ - mmu_init(); - - mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); - mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); - mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); - mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), - UNCACHED_RAM); - - mmu_enable(); -} - -void soc_mmu_dram_config_post_dram_init(void) -{ - mmu_config_range((void *)_aop, REGION_SIZE(aop), CACHED_RAM); -} diff --git a/src/soc/qualcomm/sdm845/qclib.c b/src/soc/qualcomm/sdm845/qclib.c deleted file mode 100644 index 561713949a..0000000000 --- a/src/soc/qualcomm/sdm845/qclib.c +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -int qclib_soc_blob_load(void) -{ - size_t size; - ssize_t ssize; - - /* Attempt to load PMICCFG Blob */ - size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", - _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); - if (!size) - return -1; - qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); - - /* Attempt to load DCB Blob */ - size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", - _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); - if (!size) - return -1; - qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); - - /* Attempt to load Limits Config Blob */ - ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, - REGION_SIZE(limits_cfg)); - if (ssize < 0) - return -1; - qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, - _limits_cfg, ssize, 0); - - return 0; -} diff --git a/src/soc/qualcomm/sdm845/qspi.c b/src/soc/qualcomm/sdm845/qspi.c deleted file mode 100644 index 8c98316655..0000000000 --- a/src/soc/qualcomm/sdm845/qspi.c +++ /dev/null @@ -1,293 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define CACHE_LINE_SIZE 64 - -static int curr_desc_idx = -1; - -struct cmd_desc { - uint32_t data_address; - uint32_t next_descriptor; - uint32_t direction:1; - uint32_t multi_io_mode:3; - uint32_t reserved1:4; - uint32_t fragment:1; - uint32_t reserved2:7; - uint32_t length:16; - //------------------------// - uint32_t bounce_src; - uint32_t bounce_dst; - uint32_t bounce_length; - uint64_t padding[5]; -}; - -enum qspi_mode { - SDR_1BIT = 1, - SDR_2BIT = 2, - SDR_4BIT = 3, - DDR_1BIT = 5, - DDR_2BIT = 6, - DDR_4BIT = 7, -}; - -enum cs_state { - CS_DEASSERT, - CS_ASSERT -}; - -struct xfer_cfg { - enum qspi_mode mode; -}; - -enum bus_xfer_direction { - MASTER_READ = 0, - MASTER_WRITE = 1, -}; - -struct { - struct cmd_desc descriptors[3]; - uint8_t buffers[3][CACHE_LINE_SIZE]; -} *dma = (void *)_dma_coherent; - -static void dma_transfer_chain(struct cmd_desc *chain) -{ - uint32_t mstr_int_status; - - write32(&sdm845_qspi->mstr_int_sts, 0xFFFFFFFF); - write32(&sdm845_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain); - - while (1) { - mstr_int_status = read32(&sdm845_qspi->mstr_int_sts); - if (mstr_int_status & DMA_CHAIN_DONE) - break; - } -} - -static void flush_chain(void) -{ - struct cmd_desc *desc = &dma->descriptors[0]; - uint8_t *src; - uint8_t *dst; - - dma_transfer_chain(desc); - - while (desc) { - if (desc->direction == MASTER_READ) { - if (desc->bounce_length == 0) - dcache_invalidate_by_mva( - (void *)(uintptr_t) desc->data_address, - desc->length); - else { - src = (void *)(uintptr_t) desc->bounce_src; - dst = (void *)(uintptr_t) desc->bounce_dst; - memcpy(dst, src, desc->bounce_length); - } - } - desc = (void *)(uintptr_t) desc->next_descriptor; - } - curr_desc_idx = -1; -} - -static struct cmd_desc *allocate_descriptor(void) -{ - struct cmd_desc *current; - struct cmd_desc *next; - uint8_t index; - - current = (curr_desc_idx == -1) ? - NULL : &dma->descriptors[curr_desc_idx]; - - index = ++curr_desc_idx; - next = &dma->descriptors[index]; - - next->data_address = (uint32_t) (uintptr_t) dma->buffers[index]; - - next->next_descriptor = 0; - next->direction = MASTER_READ; - next->multi_io_mode = 0; - next->reserved1 = 0; - next->fragment = 0; - next->reserved2 = 0; - next->length = 0; - next->bounce_src = 0; - next->bounce_dst = 0; - next->bounce_length = 0; - - if (current) { - current->next_descriptor = (uint32_t)(uintptr_t) next; - current->fragment = 1; - } - - return next; -} - -static void cs_change(enum cs_state state) -{ - gpio_set(GPIO(90), state == CS_DEASSERT); -} - -static void configure_gpios(void) -{ - gpio_output(GPIO(90), 1); - - gpio_configure(GPIO(91), GPIO91_FUNC_QSPI_DATA, - GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); - - gpio_configure(GPIO(92), GPIO92_FUNC_QSPI_DATA, - GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); - - gpio_configure(GPIO(95), GPIO95_FUNC_QSPI_CLK, - GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); -} - -static void queue_bounce_data(uint8_t *data, uint32_t data_bytes, - enum qspi_mode data_mode, bool write) -{ - struct cmd_desc *desc; - uint8_t *ptr; - - desc = allocate_descriptor(); - desc->direction = write; - desc->multi_io_mode = data_mode; - ptr = (void *)(uintptr_t) desc->data_address; - - if (write) { - memcpy(ptr, data, data_bytes); - } else { - desc->bounce_src = (uint32_t)(uintptr_t) ptr; - desc->bounce_dst = (uint32_t)(uintptr_t) data; - desc->bounce_length = data_bytes; - } - - desc->length = data_bytes; -} - -static void queue_direct_data(uint8_t *data, uint32_t data_bytes, - enum qspi_mode data_mode, bool write) -{ - struct cmd_desc *desc; - - desc = allocate_descriptor(); - desc->direction = write; - desc->multi_io_mode = data_mode; - desc->data_address = (uint32_t)(uintptr_t) data; - desc->length = data_bytes; - - if (write) - dcache_clean_by_mva(data, data_bytes); - else - dcache_invalidate_by_mva(data, data_bytes); -} - -static void queue_data(uint8_t *data, uint32_t data_bytes, - enum qspi_mode data_mode, bool write) -{ - uint8_t *aligned_ptr; - uint8_t *epilog_ptr; - uint32_t prolog_bytes, aligned_bytes, epilog_bytes; - - if (data_bytes == 0) - return; - - aligned_ptr = - (uint8_t *)ALIGN_UP((uintptr_t)data, CACHE_LINE_SIZE); - - prolog_bytes = MIN(data_bytes, aligned_ptr - data); - aligned_bytes = ALIGN_DOWN(data_bytes - prolog_bytes, CACHE_LINE_SIZE); - epilog_bytes = data_bytes - prolog_bytes - aligned_bytes; - - epilog_ptr = data + prolog_bytes + aligned_bytes; - - if (prolog_bytes) - queue_bounce_data(data, prolog_bytes, data_mode, write); - if (aligned_bytes) - queue_direct_data(aligned_ptr, aligned_bytes, data_mode, write); - if (epilog_bytes) - queue_bounce_data(epilog_ptr, epilog_bytes, data_mode, write); -} - -static void reg_init(void) -{ - uint32_t spi_mode; - uint32_t tx_data_oe_delay, tx_data_delay; - uint32_t mstr_config; - - spi_mode = 0; - - tx_data_oe_delay = 0; - tx_data_delay = 0; - - mstr_config = (tx_data_oe_delay << TX_DATA_OE_DELAY_SHIFT) | - (tx_data_delay << TX_DATA_DELAY_SHIFT) | (SBL_EN) | - (spi_mode << SPI_MODE_SHIFT) | - (PIN_HOLDN) | - (FB_CLK_EN) | - (DMA_ENABLE) | - (FULL_CYCLE_MODE); - - write32(&sdm845_qspi->mstr_cfg, mstr_config); - write32(&sdm845_qspi->ahb_mstr_cfg, 0xA42); - write32(&sdm845_qspi->mstr_int_en, 0x0); - write32(&sdm845_qspi->mstr_int_sts, 0xFFFFFFFF); - write32(&sdm845_qspi->rd_fifo_cfg, 0x0); - write32(&sdm845_qspi->rd_fifo_rst, RESET_FIFO); -} - -void quadspi_init(uint32_t hz) -{ - assert(dcache_line_bytes() == CACHE_LINE_SIZE); - clock_configure_qspi(hz * 4); - configure_gpios(); - reg_init(); -} - -int sdm845_claim_bus(const struct spi_slave *slave) -{ - cs_change(CS_ASSERT); - return 0; -} - -void sdm845_release_bus(const struct spi_slave *slave) -{ - cs_change(CS_DEASSERT); -} - -static int xfer(enum qspi_mode mode, const void *dout, size_t out_bytes, - void *din, size_t in_bytes) -{ - if ((out_bytes && !dout) || (in_bytes && !din) || - (in_bytes && out_bytes)) { - return -1; - } - - queue_data((uint8_t *) (out_bytes ? dout : din), - in_bytes | out_bytes, mode, !!out_bytes); - - flush_chain(); - - return 0; -} - -int sdm845_xfer(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes) -{ - return xfer(SDR_1BIT, dout, out_bytes, din, in_bytes); -} - -int sdm845_xfer_dual(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes) -{ - return xfer(SDR_2BIT, dout, out_bytes, din, in_bytes); -} diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c deleted file mode 100644 index 07716e83bd..0000000000 --- a/src/soc/qualcomm/sdm845/soc.c +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -static void soc_read_resources(struct device *dev) -{ - ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, - ddr_region->size / KiB); - reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB, - REGION_SIZE(dram_reserved) / KiB); -} - -static void soc_init(struct device *dev) -{ - aop_fw_load_reset(); -} - -static struct device_operations soc_ops = { - .read_resources = soc_read_resources, - .init = soc_init, -}; - -static void enable_soc_dev(struct device *dev) -{ - dev->ops = &soc_ops; -} - -struct chip_operations soc_qualcomm_sdm845_ops = { - CHIP_NAME("SOC Qualcomm SDM845") - .enable_dev = enable_soc_dev, -}; diff --git a/src/soc/qualcomm/sdm845/spi.c b/src/soc/qualcomm/sdm845/spi.c deleted file mode 100644 index 88314f4d85..0000000000 --- a/src/soc/qualcomm/sdm845/spi.c +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -static const struct spi_ctrlr spi_ctrlr = { - .claim_bus = sdm845_claim_bus, - .release_bus = sdm845_release_bus, - .xfer = sdm845_xfer, - .xfer_dual = sdm845_xfer_dual, - .max_xfer_size = QSPI_MAX_PACKET_COUNT, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, - .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sdm845/timer.c b/src/soc/qualcomm/sdm845/timer.c deleted file mode 100644 index 19e466aa17..0000000000 --- a/src/soc/qualcomm/sdm845/timer.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -void init_timer(void) -{ - raw_write_cntfrq_el0(19200*KHz); -} diff --git a/src/soc/qualcomm/sdm845/uart_bitbang.c b/src/soc/qualcomm/sdm845/uart_bitbang.c deleted file mode 100644 index 8d7138e5d1..0000000000 --- a/src/soc/qualcomm/sdm845/uart_bitbang.c +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -#define UART_TX_PIN GPIO(4) - -static void set_tx(int line_state) -{ - gpio_set(UART_TX_PIN, line_state); -} - -void uart_init(unsigned int idx) -{ - gpio_output(UART_TX_PIN, 1); -} - -void uart_tx_byte(unsigned int idx, unsigned char data) -{ - uart_bitbang_tx_byte(data, set_tx); -} - -void uart_tx_flush(unsigned int idx) -{ - /* unnecessary, PIO Tx means transaction is over when tx_byte returns */ -} - -unsigned char uart_rx_byte(unsigned int idx) -{ - return 0; /* not implemented */ -} diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c deleted file mode 100644 index 11c3edb548..0000000000 --- a/src/soc/qualcomm/sdm845/usb.c +++ /dev/null @@ -1,899 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include - -struct usb_qusb_phy_dig { - u8 rsvd1[16]; - u32 pwr_ctrl1; - u32 pwr_ctrl2; - u8 rsvd2[8]; - u32 imp_ctrl1; - u32 imp_ctrl2; - u8 rsvd3[20]; - u32 chg_ctrl2; - u32 tune1; - u32 tune2; - u32 tune3; - u32 tune4; - u32 tune5; - u8 rsvd4[44]; - u32 debug_ctrl2; - u8 rsvd5[28]; - u32 debug_stat5; -}; -check_member(usb_qusb_phy_dig, tune5, 0x50); -check_member(usb_qusb_phy_dig, debug_ctrl2, 0x80); -check_member(usb_qusb_phy_dig, debug_stat5, 0xA0); - -struct usb_qusb_phy_pll { - u8 rsvd0[4]; - u32 analog_controls_two; - u8 rsvd1[36]; - u32 cmode; - u8 rsvd2[132]; - u32 dig_tim; - u8 rsvd3[204]; - u32 lock_delay; - u8 rsvd4[4]; - u32 clock_inverters; - u8 rsvd5[4]; - u32 bias_ctrl_1; - u32 bias_ctrl_2; -}; -check_member(usb_qusb_phy_pll, cmode, 0x2C); -check_member(usb_qusb_phy_pll, bias_ctrl_2, 0x198); -check_member(usb_qusb_phy_pll, dig_tim, 0xB4); - -/* Only for QMP V3 PHY - QSERDES COM registers */ -struct usb3_phy_qserdes_com_reg_layout { - u8 _reserved1[16]; - u32 com_ssc_en_center; - u32 com_ssc_adj_per1; - u32 com_ssc_adj_per2; - u32 com_ssc_per1; - u32 com_ssc_per2; - u32 com_ssc_step_size1; - u32 com_ssc_step_size2; - u8 _reserved2[8]; - u32 com_bias_en_clkbuflr_en; - u32 com_sys_clk_enable1; - u32 com_sys_clk_ctrl; - u32 com_sysclk_buf_enable; - u32 com_pll_en; - u32 com_pll_ivco; - u8 _reserved3[20]; - u32 com_cp_ctrl_mode0; - u8 _reserved4[4]; - u32 com_pll_rctrl_mode0; - u8 _reserved5[4]; - u32 com_pll_cctrl_mode0; - u8 _reserved6[12]; - u32 com_sysclk_en_sel; - u8 _reserved7[8]; - u32 com_resetsm_ctrl2; - u32 com_lock_cmp_en; - u32 com_lock_cmp_cfg; - u32 com_lock_cmp1_mode0; - u32 com_lock_cmp2_mode0; - u32 com_lock_cmp3_mode0; - u8 _reserved8[12]; - u32 com_dec_start_mode0; - u8 _reserved9[4]; - u32 com_div_frac_start1_mode0; - u32 com_div_frac_start2_mode0; - u32 com_div_frac_start3_mode0; - u8 _reserved10[20]; - u32 com_integloop_gain0_mode0; - u32 com_integloop_gain1_mode0; - u8 _reserved11[16]; - u32 com_vco_tune_map; - u32 com_vco_tune1_mode0; - u32 com_vco_tune2_mode0; - u8 _reserved12[60]; - u32 com_clk_select; - u32 com_hsclk_sel; - u8 _reserved13[8]; - u32 com_coreclk_div_mode0; - u8 _reserved14[8]; - u32 com_core_clk_en; - u32 com_c_ready_status; - u32 com_cmn_config; - u32 com_cmn_rate_override; - u32 com_svs_mode_clk_sel; -}; -check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010); -check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per1, 0x014); -check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per2, 0x018); -check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per1, 0x01c); -check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per2, 0x020); -check_member(usb3_phy_qserdes_com_reg_layout, com_bias_en_clkbuflr_en, 0x034); -check_member(usb3_phy_qserdes_com_reg_layout, com_pll_ivco, 0x048); -check_member(usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode0, 0x060); -check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel, 0x080); -check_member(usb3_phy_qserdes_com_reg_layout, com_resetsm_ctrl2, 0x08c); -check_member(usb3_phy_qserdes_com_reg_layout, com_dec_start_mode0, 0x0b0); -check_member(usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode0, 0x0b8); -check_member(usb3_phy_qserdes_com_reg_layout, com_integloop_gain0_mode0, 0x0d8); -check_member(usb3_phy_qserdes_com_reg_layout, com_vco_tune_map, 0x0f0); -check_member(usb3_phy_qserdes_com_reg_layout, com_clk_select, 0x138); -check_member(usb3_phy_qserdes_com_reg_layout, com_coreclk_div_mode0, 0x148); -check_member(usb3_phy_qserdes_com_reg_layout, com_core_clk_en, 0x154); -check_member(usb3_phy_qserdes_com_reg_layout, com_svs_mode_clk_sel, 0x164); - -/* Only for QMP V3 PHY - TX registers */ -struct usb3_phy_qserdes_tx_reg_layout { - u8 _reserved1[68]; - u32 tx_res_code_lane_offset_tx; - u32 tx_res_code_lane_offset_rx; - u8 _reserved2[20]; - u32 tx_highz_drvr_en; - u8 _reserved3[40]; - u32 tx_lane_mode_1; - u8 _reserved4[20]; - u32 tx_rcv_detect_lvl_2; -}; -check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx, 0x044); -check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx, 0x048); -check_member(usb3_phy_qserdes_tx_reg_layout, tx_highz_drvr_en, 0x060); -check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x08c); -check_member(usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2, 0x0a4); - -/* Only for QMP V3 PHY - RX registers */ -struct usb3_phy_qserdes_rx_reg_layout { - u8 _reserved1[8]; - u32 rx_ucdr_fo_gain; - u32 rx_ucdr_so_gain_half; - u8 _reserved2[32]; - u32 rx_ucdr_fastlock_fo_gain; - u32 rx_ucdr_so_saturtn_and_en; - u8 _reserved3[12]; - u32 rx_ucdr_pi_cntrls; - u8 _reserved4[120]; - u32 rx_vga_cal_ctrl2; - u8 _reserved5[16]; - u32 rx_rx_equ_adap_ctrl2; - u32 rx_rx_equ_adap_ctrl3; - u32 rx_rx_equ_adap_ctrl4; - u8 _reserved6[24]; - u32 rx_rx_eq_offset_adap_ctrl1; - u32 rx_rx_offset_adap_ctrl2; - u32 rx_sigdet_enables; - u32 rx_sigdet_ctrl; - u8 _reserved7[4]; - u32 rx_sigdet_deglitch_ctrl; - u32 rx_rx_band; - u8 _reserved8[80]; - u32 rx_rx_mode_00; -}; -check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fo_gain, 0x008); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain_half, 0x00c); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain, 0x030); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_saturtn_and_en, 0x034); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_cntrls, 0x044); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_ctrl2, 0x0c0); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl2, 0x0d4); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl3, 0x0d8); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl4, 0x0dc); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_eq_offset_adap_ctrl1, 0x0f8); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_offset_adap_ctrl2, 0x0fc); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_enables, 0x100); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_ctrl, 0x104); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_deglitch_ctrl, 0x10c); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_band, 0x110); -check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_00, 0x164); - -/* Only for QMP V3 PHY - PCS registers */ -struct usb3_phy_pcs_reg_layout { - u32 pcs_sw_reset; - u32 pcs_power_down_control; - u32 pcs_start_control; - u32 pcs_txmgn_v0; - u32 pcs_txmgn_v1; - u32 pcs_txmgn_v2; - u32 pcs_txmgn_v3; - u32 pcs_txmgn_v4; - u32 pcs_txmgn_ls; - u32 pcs_txdeemph_m6db_v0; - u32 pcs_txdeemph_m3p5db_v0; - u32 pcs_txdeemph_m6db_v1; - u32 pcs_txdeemph_m3p5db_v1; - u32 pcs_txdeemph_m6db_v2; - u32 pcs_txdeemph_m3p5db_v2; - u32 pcs_txdeemph_m6db_v3; - u32 pcs_txdeemph_m3p5db_v3; - u32 pcs_txdeemph_m6db_v4; - u32 pcs_txdeemph_m3p5db_v4; - u32 pcs_txdeemph_m6db_ls; - u32 pcs_txdeemph_m3p5db_ls; - u8 _reserved1[8]; - u32 pcs_rate_slew_cntrl; - u8 _reserved2[4]; - u32 pcs_power_state_config2; - u8 _reserved3[8]; - u32 pcs_rcvr_dtct_dly_p1u2_l; - u32 pcs_rcvr_dtct_dly_p1u2_h; - u32 pcs_rcvr_dtct_dly_u3_l; - u32 pcs_rcvr_dtct_dly_u3_h; - u32 pcs_lock_detect_config1; - u32 pcs_lock_detect_config2; - u32 pcs_lock_detect_config3; - u32 pcs_tsync_rsync_time; - u8 _reserved4[16]; - u32 pcs_pwrup_reset_dly_time_auxclk; - u8 _reserved5[12]; - u32 pcs_lfps_ecstart_eqtlock; - u8 _reserved6[4]; - u32 pcs_rxeqtraining_wait_time; - u32 pcs_rxeqtraining_run_time; - u8 _reserved7[4]; - u32 pcs_fll_ctrl1; - u32 pcs_fll_ctrl2; - u32 pcs_fll_cnt_val_l; - u32 pcs_fll_cnt_val_h_tol; - u32 pcs_fll_man_code; - u32 pcs_autonomous_mode_ctrl; - u8 _reserved8[152]; - u32 pcs_ready_status; - u8 _reserved9[96]; - u32 pcs_rx_sigdet_lvl; - u8 _reserved10[48]; - u32 pcs_refgen_req_config1; - u32 pcs_refgen_req_config2; -}; -check_member(usb3_phy_pcs_reg_layout, pcs_sw_reset, 0x000); -check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v0, 0x00c); -check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v1, 0x010); -check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v2, 0x014); -check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v3, 0x018); -check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v4, 0x01c); -check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_ls, 0x020); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v0, 0x024); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v0, 0x028); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v1, 0x02c); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v1, 0x030); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v2, 0x034); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v2, 0x038); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v3, 0x03c); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v3, 0x040); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v4, 0x044); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v4, 0x048); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_ls, 0x04c); -check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_ls, 0x050); -check_member(usb3_phy_pcs_reg_layout, pcs_rate_slew_cntrl, 0x05c); -check_member(usb3_phy_pcs_reg_layout, pcs_power_state_config2, 0x064); -check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_l, 0x070); -check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_h, 0x074); -check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_l, 0x078); -check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_h, 0x07c); -check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0x080); -check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config2, 0x084); -check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config3, 0x088); -check_member(usb3_phy_pcs_reg_layout, pcs_pwrup_reset_dly_time_auxclk, 0x0a0); -check_member(usb3_phy_pcs_reg_layout, pcs_rxeqtraining_wait_time, 0x0b8); -check_member(usb3_phy_pcs_reg_layout, pcs_fll_cnt_val_h_tol, 0x0d0); -check_member(usb3_phy_pcs_reg_layout, pcs_autonomous_mode_ctrl, 0x0d8); -check_member(usb3_phy_pcs_reg_layout, pcs_ready_status, 0x174); -check_member(usb3_phy_pcs_reg_layout, pcs_refgen_req_config2, 0x210); - -static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout = - (void *)QMP_PHY_QSERDES_COM_REG_BASE; -static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout = - (void *)QMP_PHY_QSERDES_TX_REG_BASE; -static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout = - (void *)QMP_PHY_QSERDES_RX_REG_BASE; -static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = - (void *)QMP_PHY_PCS_REG_BASE; - -static struct usb3_phy_qserdes_com_reg_layout *const - uniphy_qserdes_com_reg_layout = - (void *)QMP_UNIPHY_QSERDES_COM_REG_BASE; -static struct usb3_phy_qserdes_tx_reg_layout - *const uniphy_qserdes_tx_reg_layout = - (void *)QMP_UNIPHY_QSERDES_TX_REG_BASE; -static struct usb3_phy_qserdes_rx_reg_layout - *const uniphy_qserdes_rx_reg_layout = - (void *)QMP_UNIPHY_QSERDES_RX_REG_BASE; -static struct usb3_phy_pcs_reg_layout *const uniphy_pcs_reg_layout = - (void *)QMP_UNIPHY_PCS_REG_BASE; - -struct usb_dwc3 { - u32 sbuscfg0; - u32 sbuscfg1; - u32 txthrcfg; - u32 rxthrcfg; - u32 ctl; - u32 pmsts; - u32 sts; - u32 uctl1; - u32 snpsid; - u32 gpio; - u32 uid; - u32 uctl; - u64 buserraddr; - u64 prtbimap; - u8 reserved1[32]; - u32 dbgfifospace; - u32 dbgltssm; - u32 dbglnmcc; - u32 dbgbmu; - u32 dbglspmux; - u32 dbglsp; - u32 dbgepinfo0; - u32 dbgepinfo1; - u64 prtbimap_hs; - u64 prtbimap_fs; - u8 reserved2[112]; - u32 usb2phycfg; - u8 reserved3[60]; - u32 usb2i2cctl; - u8 reserved4[60]; - u32 usb2phyacc; - u8 reserved5[60]; - u32 usb3pipectl; - u8 reserved6[60]; -}; -check_member(usb_dwc3, usb3pipectl, 0x1c0); - -static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { - {&qserdes_com_reg_layout->com_pll_ivco, 0x07}, - {&qserdes_com_reg_layout->com_sysclk_en_sel, 0x14}, - {&qserdes_com_reg_layout->com_bias_en_clkbuflr_en, 0x08}, - {&qserdes_com_reg_layout->com_clk_select, 0x30}, - {&qserdes_com_reg_layout->com_sys_clk_ctrl, 0x02}, - {&qserdes_com_reg_layout->com_resetsm_ctrl2, 0x08}, - {&qserdes_com_reg_layout->com_cmn_config, 0x16}, - {&qserdes_com_reg_layout->com_svs_mode_clk_sel, 0x01}, - {&qserdes_com_reg_layout->com_hsclk_sel, 0x80}, - {&qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, - {&qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, - {&qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, - {&qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, - {&qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, - {&qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, - {&qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, - {&qserdes_com_reg_layout->com_integloop_gain1_mode0, 0x00}, - {&qserdes_com_reg_layout->com_integloop_gain0_mode0, 0x3f}, - {&qserdes_com_reg_layout->com_vco_tune2_mode0, 0x01}, - {&qserdes_com_reg_layout->com_vco_tune1_mode0, 0xc9}, - {&qserdes_com_reg_layout->com_coreclk_div_mode0, 0x0a}, - {&qserdes_com_reg_layout->com_lock_cmp3_mode0, 0x00}, - {&qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, - {&qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x15}, - {&qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, - {&qserdes_com_reg_layout->com_core_clk_en, 0x00}, - {&qserdes_com_reg_layout->com_lock_cmp_cfg, 0x00}, - {&qserdes_com_reg_layout->com_vco_tune_map, 0x00}, - {&qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, - {&qserdes_com_reg_layout->com_ssc_en_center, 0x01}, - {&qserdes_com_reg_layout->com_ssc_per1, 0x31}, - {&qserdes_com_reg_layout->com_ssc_per2, 0x01}, - {&qserdes_com_reg_layout->com_ssc_adj_per1, 0x00}, - {&qserdes_com_reg_layout->com_ssc_adj_per2, 0x00}, - {&qserdes_com_reg_layout->com_ssc_step_size1, 0x85}, - {&qserdes_com_reg_layout->com_ssc_step_size2, 0x07}, -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { - {&qserdes_tx_reg_layout->tx_highz_drvr_en, 0x10}, - {&qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, - {&qserdes_tx_reg_layout->tx_lane_mode_1, 0x16}, - {&qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x09}, - {&qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x06}, -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { - {&qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x0b}, - {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl2, 0x0f}, - {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl3, 0x4e}, - {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl4, 0x18}, - {&qserdes_rx_reg_layout->rx_rx_eq_offset_adap_ctrl1, 0x77}, - {&qserdes_rx_reg_layout->rx_rx_offset_adap_ctrl2, 0x80}, - {&qserdes_rx_reg_layout->rx_sigdet_ctrl, 0x03}, - {&qserdes_rx_reg_layout->rx_sigdet_deglitch_ctrl, 0x16}, - {&qserdes_rx_reg_layout->rx_ucdr_so_saturtn_and_en, 0x75}, - {&qserdes_rx_reg_layout->rx_ucdr_pi_cntrls, 0x80}, - {&qserdes_rx_reg_layout->rx_ucdr_fo_gain, 0x0a}, - {&qserdes_rx_reg_layout->rx_ucdr_so_gain_half, 0x06}, - {&qserdes_rx_reg_layout->rx_sigdet_enables, 0x00}, -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { - /* FLL settings */ - {&pcs_reg_layout->pcs_fll_ctrl2, 0x83}, - {&pcs_reg_layout->pcs_fll_cnt_val_l, 0x09}, - {&pcs_reg_layout->pcs_fll_cnt_val_h_tol, 0xa2}, - {&pcs_reg_layout->pcs_fll_man_code, 0x40}, - {&pcs_reg_layout->pcs_fll_ctrl1, 0x02}, - - /* Lock Det settings */ - {&pcs_reg_layout->pcs_lock_detect_config1, 0xd1}, - {&pcs_reg_layout->pcs_lock_detect_config2, 0x1f}, - {&pcs_reg_layout->pcs_lock_detect_config3, 0x47}, - {&pcs_reg_layout->pcs_power_state_config2, 0x1b}, - - {&pcs_reg_layout->pcs_rx_sigdet_lvl, 0xba}, - {&pcs_reg_layout->pcs_txmgn_v0, 0x9f}, - {&pcs_reg_layout->pcs_txmgn_v1, 0x9f}, - {&pcs_reg_layout->pcs_txmgn_v2, 0xb7}, - {&pcs_reg_layout->pcs_txmgn_v3, 0x4e}, - {&pcs_reg_layout->pcs_txmgn_v4, 0x65}, - {&pcs_reg_layout->pcs_txmgn_ls, 0x6b}, - {&pcs_reg_layout->pcs_txdeemph_m6db_v0, 0x15}, - {&pcs_reg_layout->pcs_txdeemph_m3p5db_v0, 0x0d}, - {&pcs_reg_layout->pcs_txdeemph_m6db_v1, 0x15}, - {&pcs_reg_layout->pcs_txdeemph_m3p5db_v1, 0x0d}, - {&pcs_reg_layout->pcs_txdeemph_m6db_v2, 0x15}, - {&pcs_reg_layout->pcs_txdeemph_m3p5db_v2, 0x0d}, - {&pcs_reg_layout->pcs_txdeemph_m6db_v3, 0x15}, - {&pcs_reg_layout->pcs_txdeemph_m3p5db_v3, 0x1d}, - {&pcs_reg_layout->pcs_txdeemph_m6db_v4, 0x15}, - {&pcs_reg_layout->pcs_txdeemph_m3p5db_v4, 0x0d}, - {&pcs_reg_layout->pcs_txdeemph_m6db_ls, 0x15}, - {&pcs_reg_layout->pcs_txdeemph_m3p5db_ls, 0x0d}, - {&pcs_reg_layout->pcs_rate_slew_cntrl, 0x02}, - {&pcs_reg_layout->pcs_pwrup_reset_dly_time_auxclk, 0x04}, - {&pcs_reg_layout->pcs_tsync_rsync_time, 0x44}, - {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_l, 0xe7}, - {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_h, 0x03}, - {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_l, 0x40}, - {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_h, 0x00}, - {&pcs_reg_layout->pcs_rxeqtraining_wait_time, 0x75}, - {&pcs_reg_layout->pcs_lfps_ecstart_eqtlock, 0x86}, - {&pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { - {&uniphy_qserdes_com_reg_layout->com_pll_ivco, 0x07}, - {&uniphy_qserdes_com_reg_layout->com_sysclk_en_sel, 0x14}, - {&uniphy_qserdes_com_reg_layout->com_bias_en_clkbuflr_en, 0x04}, - {&uniphy_qserdes_com_reg_layout->com_clk_select, 0x30}, - {&uniphy_qserdes_com_reg_layout->com_sys_clk_ctrl, 0x02}, - {&uniphy_qserdes_com_reg_layout->com_resetsm_ctrl2, 0x08}, - {&uniphy_qserdes_com_reg_layout->com_cmn_config, 0x06}, - {&uniphy_qserdes_com_reg_layout->com_svs_mode_clk_sel, 0x01}, - {&uniphy_qserdes_com_reg_layout->com_hsclk_sel, 0x80}, - {&uniphy_qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, - {&uniphy_qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, - {&uniphy_qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, - {&uniphy_qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, - {&uniphy_qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, - {&uniphy_qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, - {&uniphy_qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, - {&uniphy_qserdes_com_reg_layout->com_integloop_gain1_mode0, 0x00}, - {&uniphy_qserdes_com_reg_layout->com_integloop_gain0_mode0, 0x3f}, - {&uniphy_qserdes_com_reg_layout->com_vco_tune2_mode0, 0x01}, - {&uniphy_qserdes_com_reg_layout->com_vco_tune1_mode0, 0xc9}, - {&uniphy_qserdes_com_reg_layout->com_coreclk_div_mode0, 0x0a}, - {&uniphy_qserdes_com_reg_layout->com_lock_cmp3_mode0, 0x00}, - {&uniphy_qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, - {&uniphy_qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x15}, - {&uniphy_qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, - {&uniphy_qserdes_com_reg_layout->com_core_clk_en, 0x00}, - {&uniphy_qserdes_com_reg_layout->com_lock_cmp_cfg, 0x00}, - {&uniphy_qserdes_com_reg_layout->com_vco_tune_map, 0x00}, - {&uniphy_qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, - {&uniphy_qserdes_com_reg_layout->com_ssc_en_center, 0x01}, - {&uniphy_qserdes_com_reg_layout->com_ssc_per1, 0x31}, - {&uniphy_qserdes_com_reg_layout->com_ssc_per2, 0x01}, - {&uniphy_qserdes_com_reg_layout->com_ssc_adj_per1, 0x00}, - {&uniphy_qserdes_com_reg_layout->com_ssc_adj_per2, 0x00}, - {&uniphy_qserdes_com_reg_layout->com_ssc_step_size1, 0x85}, - {&uniphy_qserdes_com_reg_layout->com_ssc_step_size2, 0x07}, -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { - {&uniphy_qserdes_tx_reg_layout->tx_highz_drvr_en, 0x10}, - {&uniphy_qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, - {&uniphy_qserdes_tx_reg_layout->tx_lane_mode_1, 0xc6}, - {&uniphy_qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x06}, - {&uniphy_qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x06}, -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { - {&uniphy_qserdes_rx_reg_layout->rx_vga_cal_ctrl2, 0x0c}, - {&uniphy_qserdes_rx_reg_layout->rx_rx_mode_00, 0x50}, - {&uniphy_qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x0b}, - {&uniphy_qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl2, 0x0e}, - {&uniphy_qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl3, 0x4e}, - {&uniphy_qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl4, 0x18}, - {&uniphy_qserdes_rx_reg_layout->rx_rx_eq_offset_adap_ctrl1, 0x77}, - {&uniphy_qserdes_rx_reg_layout->rx_rx_offset_adap_ctrl2, 0x80}, - {&uniphy_qserdes_rx_reg_layout->rx_sigdet_ctrl, 0x03}, - {&uniphy_qserdes_rx_reg_layout->rx_sigdet_deglitch_ctrl, 0x1c}, - {&uniphy_qserdes_rx_reg_layout->rx_ucdr_so_saturtn_and_en, 0x75}, - {&uniphy_qserdes_rx_reg_layout->rx_ucdr_pi_cntrls, 0x80}, - {&uniphy_qserdes_rx_reg_layout->rx_ucdr_fo_gain, 0x0a}, - {&uniphy_qserdes_rx_reg_layout->rx_ucdr_so_gain_half, 0x06}, - {&uniphy_qserdes_rx_reg_layout->rx_sigdet_enables, 0x00}, -}; - -static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { - /* FLL settings */ - {&uniphy_pcs_reg_layout->pcs_fll_ctrl2, 0x83}, - {&uniphy_pcs_reg_layout->pcs_fll_cnt_val_l, 0x09}, - {&uniphy_pcs_reg_layout->pcs_fll_cnt_val_h_tol, 0xa2}, - {&uniphy_pcs_reg_layout->pcs_fll_man_code, 0x40}, - {&uniphy_pcs_reg_layout->pcs_fll_ctrl1, 0x02}, - - /* Lock Det settings */ - {&uniphy_pcs_reg_layout->pcs_lock_detect_config1, 0xd1}, - {&uniphy_pcs_reg_layout->pcs_lock_detect_config2, 0x1f}, - {&uniphy_pcs_reg_layout->pcs_lock_detect_config3, 0x47}, - {&uniphy_pcs_reg_layout->pcs_power_state_config2, 0x1b}, - - {&uniphy_pcs_reg_layout->pcs_rx_sigdet_lvl, 0xba}, - {&uniphy_pcs_reg_layout->pcs_txmgn_v0, 0x9f}, - {&uniphy_pcs_reg_layout->pcs_txmgn_v1, 0x9f}, - {&uniphy_pcs_reg_layout->pcs_txmgn_v2, 0xb5}, - {&uniphy_pcs_reg_layout->pcs_txmgn_v3, 0x4c}, - {&uniphy_pcs_reg_layout->pcs_txmgn_v4, 0x64}, - {&uniphy_pcs_reg_layout->pcs_txmgn_ls, 0x6a}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v0, 0x15}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v0, 0x0d}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v1, 0x15}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v1, 0x0d}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v2, 0x15}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v2, 0x0d}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v3, 0x15}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v3, 0x1d}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v4, 0x15}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v4, 0x0d}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_ls, 0x15}, - {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_ls, 0x0d}, - {&uniphy_pcs_reg_layout->pcs_rate_slew_cntrl, 0x02}, - {&uniphy_pcs_reg_layout->pcs_pwrup_reset_dly_time_auxclk, 0x04}, - {&uniphy_pcs_reg_layout->pcs_tsync_rsync_time, 0x44}, - {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_l, 0xe7}, - {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_h, 0x03}, - {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_u3_l, 0x40}, - {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_u3_h, 0x00}, - {&uniphy_pcs_reg_layout->pcs_rxeqtraining_wait_time, 0x75}, - {&uniphy_pcs_reg_layout->pcs_lfps_ecstart_eqtlock, 0x86}, - {&uniphy_pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, - {&uniphy_pcs_reg_layout->pcs_refgen_req_config1, 0x21}, - {&uniphy_pcs_reg_layout->pcs_refgen_req_config2, 0x60}, -}; - -struct usb_dwc3_cfg { - struct usb_dwc3 *usb_host_dwc3; - struct usb_qusb_phy_pll *qusb_phy_pll; - struct usb_qusb_phy_dig *qusb_phy_dig; - /* Init sequence for QMP PHY blocks - serdes, tx, rx, pcs */ - const struct qmp_phy_init_tbl *serdes_tbl; - int serdes_tbl_num; - const struct qmp_phy_init_tbl *tx_tbl; - int tx_tbl_num; - const struct qmp_phy_init_tbl *rx_tbl; - int rx_tbl_num; - const struct qmp_phy_init_tbl *pcs_tbl; - int pcs_tbl_num; - struct usb3_phy_pcs_reg_layout *qmp_pcs_reg; - - u32 *usb3_bcr; - u32 *qusb2phy_bcr; - u32 *gcc_usb3phy_bcr_reg; - u32 *gcc_qmpphy_bcr_reg; - struct usb_board_data *board_data; - u32 efuse_offset; -}; - -static struct usb_dwc3_cfg usb_port0 = { - .usb_host_dwc3 = (void *)USB_HOST0_DWC3_BASE, - .qusb_phy_pll = (void *)QUSB_PRIM_PHY_BASE, - .qusb_phy_dig = (void *)QUSB_PRIM_PHY_DIG_BASE, - .serdes_tbl = qmp_v3_usb3_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), - .tx_tbl = qmp_v3_usb3_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), - .rx_tbl = qmp_v3_usb3_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), - .pcs_tbl = qmp_v3_usb3_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), - .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE, - .usb3_bcr = &gcc->usb30_prim_bcr, - .qusb2phy_bcr = &gcc->qusb2phy_prim_bcr, - .gcc_usb3phy_bcr_reg = &gcc->usb3_dp_phy_prim_bcr, - .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_prim_bcr, - .efuse_offset = 25, -}; -static struct usb_dwc3_cfg usb_port1 = { - .usb_host_dwc3 = (void *)USB_HOST1_DWC3_BASE, - .qusb_phy_pll = (void *)QUSB_SEC_PHY_BASE, - .qusb_phy_dig = (void *)QUSB_SEC_PHY_DIG_BASE, - .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), - .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), - .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), - .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), - .qmp_pcs_reg = (void *)QMP_UNIPHY_PCS_REG_BASE, - .usb3_bcr = &gcc->usb30_sec_bcr, - .qusb2phy_bcr = &gcc->qusb2phy_sec_bcr, - .gcc_usb3phy_bcr_reg = &gcc->usb3phy_phy_sec_bcr, - .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_sec_bcr, - .efuse_offset = 30, -}; - -static struct qfprom_corr * const qfprom_corr_efuse = (void *)QFPROM_BASE; - -static void reset_usb(struct usb_dwc3_cfg *dwc3) -{ - /* Assert Core reset */ - clock_reset_bcr(dwc3->usb3_bcr, 1); - - /* Assert QUSB PHY reset */ - clock_reset_bcr(dwc3->qusb2phy_bcr, 1); - - /* Assert QMP PHY reset */ - clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 1); - clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 1); -} - -void reset_usb0(void) -{ - /* Before Resetting PHY, put Core in Reset */ - printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(0)\n"); - - reset_usb(&usb_port0); -} - -void reset_usb1(void) -{ - /* Before Resetting PHY, put Core in Reset */ - printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(1)\n"); - - reset_usb(&usb_port1); -} -/* - * Update board specific PHY tuning override values that specified from - * board file. - */ -static void qusb2_phy_override_phy_params(struct usb_dwc3_cfg *dwc3) -{ - /* Override preemphasis value */ - write32(&dwc3->qusb_phy_dig->tune1, - dwc3->board_data->port_tune1); - - /* Override BIAS_CTRL_2 to reduce the TX swing overshooting. */ - write32(&dwc3->qusb_phy_pll->bias_ctrl_2, - dwc3->board_data->pll_bias_control_2); - - /* Override IMP_RES_OFFSET value */ - write32(&dwc3->qusb_phy_dig->imp_ctrl1, - dwc3->board_data->imp_ctrl1); -} - -/* - * Fetches HS Tx tuning value from efuse register and sets the - * QUSB2PHY_PORT_TUNE1/2 register. - * For error case, skip setting the value and use the default value. - */ -static void qusb2_phy_set_tune_param(struct usb_dwc3_cfg *dwc3) -{ - /* - * Efuse registers 4 bit value specifies tuning for HSTX - * output current in TUNE1 Register. Hence Extract 4 bits from - * EFUSE at correct position. - */ - - const int efuse_bits = 4; - int bit_pos = dwc3->efuse_offset; - - u32 bit_mask = (1 << efuse_bits) - 1; - u32 tune_val = - (read32(&qfprom_corr_efuse->qusb_hstx_trim_lsb) >> bit_pos) - & bit_mask; - - if (bit_pos + efuse_bits > 32) { - /* - * Value split between two EFUSE registers, - * get the second part. - */ - int done_bits = 32 - bit_pos; - - bit_mask = (1 << (efuse_bits - done_bits)) - 1; - tune_val |= - (read32(&qfprom_corr_efuse->qusb_hstx_trim_msb) & - bit_mask) << done_bits; - } - - /* - * if efuse reg is updated (i.e non-zero) then use it to program - * tune parameters. - */ - if (tune_val) - clrsetbits32(&dwc3->qusb_phy_dig->tune1, - PORT_TUNE1_MASK, tune_val << 4); -} - -static void tune_phy(struct usb_dwc3_cfg *dwc3, struct usb_qusb_phy_dig *phy) -{ - write32(&phy->pwr_ctrl2, QUSB2PHY_PWR_CTRL2); - /* IMP_CTRL1: Control the impedance reduction */ - write32(&phy->imp_ctrl1, QUSB2PHY_IMP_CTRL1); - /* IMP_CTRL2: Impedance offset/mapping slope */ - write32(&phy->imp_ctrl2, QUSB2PHY_IMP_CTRL1); - write32(&phy->chg_ctrl2, QUSB2PHY_IMP_CTRL2); - /* - * TUNE1: Sets HS Impedance to approx 45 ohms - * then override with efuse value. - */ - write32(&phy->tune1, QUSB2PHY_PORT_TUNE1); - /* TUNE2: Tuning for HS Disconnect Level */ - write32(&phy->tune2, QUSB2PHY_PORT_TUNE2); - /* TUNE3: Tune squelch range */ - write32(&phy->tune3, QUSB2PHY_PORT_TUNE3); - /* TUNE4: Sets EOP_DLY(Squelch rising edge to linestate falling edge) */ - write32(&phy->tune4, QUSB2PHY_PORT_TUNE4); - write32(&phy->tune5, QUSB2PHY_PORT_TUNE5); - - if (dwc3->board_data) { - /* Override board specific PHY tuning values */ - qusb2_phy_override_phy_params(dwc3); - - /* Set efuse value for tuning the PHY */ - qusb2_phy_set_tune_param(dwc3); - } -} - -static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) -{ - /* PWR_CTRL: set the power down bit to disable the PHY */ - setbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); - - write32(&dwc3->qusb_phy_pll->analog_controls_two, - QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); - write32(&dwc3->qusb_phy_pll->clock_inverters, - QUSB2PHY_PLL_CLOCK_INVERTERS); - write32(&dwc3->qusb_phy_pll->cmode, - QUSB2PHY_PLL_CMODE); - write32(&dwc3->qusb_phy_pll->lock_delay, - QUSB2PHY_PLL_LOCK_DELAY); - write32(&dwc3->qusb_phy_pll->dig_tim, - QUSB2PHY_PLL_DIGITAL_TIMERS_TWO); - write32(&dwc3->qusb_phy_pll->bias_ctrl_1, - QUSB2PHY_PLL_BIAS_CONTROL_1); - write32(&dwc3->qusb_phy_pll->bias_ctrl_2, - QUSB2PHY_PLL_BIAS_CONTROL_2); - - tune_phy(dwc3, dwc3->qusb_phy_dig); - - /* PWR_CTRL1: Clear the power down bit to enable the PHY */ - clrbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); - - write32(&dwc3->qusb_phy_dig->debug_ctrl2, - DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); - - /* - * DEBUG_STAT5: wait for 160uS for PLL lock; - * vstatus[0] changes from 0 to 1. - */ - long lock_us = wait_us(160, read32(&dwc3->qusb_phy_dig->debug_stat5) & - VSTATUS_PLL_LOCK_STATUS_MASK); - if (!lock_us) - printk(BIOS_ERR, "ERROR: QUSB PHY PLL LOCK fails\n"); - else - printk(BIOS_DEBUG, "QUSB PHY initialized and locked in %ldus\n", - lock_us); -} - -static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], - int num) -{ - int i; - const struct qmp_phy_init_tbl *t = tbl; - - if (!t) - return; - - for (i = 0; i < num; i++, t++) - write32(t->address, t->val); -} - -static void ss_qmp_phy_init(struct usb_dwc3_cfg *dwc3) -{ - /* power up USB3 PHY */ - write32(&dwc3->qmp_pcs_reg->pcs_power_down_control, 0x01); - - /* Serdes configuration */ - qcom_qmp_phy_configure(dwc3->serdes_tbl, dwc3->serdes_tbl_num); - /* Tx, Rx, and PCS configurations */ - qcom_qmp_phy_configure(dwc3->tx_tbl, dwc3->tx_tbl_num); - qcom_qmp_phy_configure(dwc3->rx_tbl, dwc3->rx_tbl_num); - qcom_qmp_phy_configure(dwc3->pcs_tbl, dwc3->pcs_tbl_num); - - /* perform software reset of PCS/Serdes */ - write32(&dwc3->qmp_pcs_reg->pcs_sw_reset, 0x00); - /* start PCS/Serdes to operation mode */ - write32(&dwc3->qmp_pcs_reg->pcs_start_control, 0x03); - - /* - * Wait for PHY initialization to be done - * PCS_STATUS: wait for 1ms for PHY STATUS; - * SW can continuously check for PHYSTATUS = 1.b0. - */ - long lock_us = wait_us(1000, - !(read32(&dwc3->qmp_pcs_reg->pcs_ready_status) & - USB3_PCS_PHYSTATUS)); - if (!lock_us) - printk(BIOS_ERR, "ERROR: QMP PHY PLL LOCK fails:\n"); - else - printk(BIOS_DEBUG, "QMP PHY initialized and locked in %ldus\n", - lock_us); -} - -static void setup_dwc3(struct usb_dwc3 *dwc3) -{ - /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ - clrsetbits32(&dwc3->usb3pipectl, - DWC3_GUSB3PIPECTL_DELAYP1TRANS, - DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); - - /* - * Configure USB phy interface of DWC3 core. - * 1. Select UTMI+ PHY with 16-bit interface. - * 2. Set USBTRDTIM to the corresponding value - * according to the UTMI+ PHY interface. - */ - clrsetbits32(&dwc3->usb2phycfg, - (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | - DWC3_GUSB2PHYCFG_PHYIF_MASK), - (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | - DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); - - clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | - DWC3_GCTL_DISSCRAMBLE), - DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); - - /* configure controller in Host mode */ - clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), - DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); - printk(BIOS_SPEW, "Configure USB in Host mode\n"); -} - -/* Initialization of DWC3 Core and PHY */ -static void setup_usb_host(struct usb_dwc3_cfg *dwc3, - struct usb_board_data *board_data) -{ - dwc3->board_data = board_data; - - /* Clear core reset. */ - clock_reset_bcr(dwc3->usb3_bcr, 0); - - /* Clear QUSB PHY reset. */ - clock_reset_bcr(dwc3->qusb2phy_bcr, 0); - - /* Initialize QUSB PHY */ - hs_qusb_phy_init(dwc3); - - /* Clear QMP PHY resets. */ - clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 0); - clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 0); - - /* Initialize QMP PHY */ - ss_qmp_phy_init(dwc3); - - setup_dwc3(dwc3->usb_host_dwc3); - - printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); -} - -void setup_usb_host0(struct usb_board_data *board_data) -{ - printk(BIOS_INFO, "Setting up USB HOST0 controller.\n"); - setup_usb_host(&usb_port0, board_data); -} - -void setup_usb_host1(struct usb_board_data *board_data) -{ - printk(BIOS_INFO, "Setting up USB HOST1 controller.\n"); - setup_usb_host(&usb_port1, board_data); -} diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index 2606af4065..98bbc9481e 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -443,9 +443,6 @@ EOF QUALCOMM_QCS405) cpu_nice="Qualcomm QCS405"; socket_nice="—";; - QUALCOMM_SDM845) - cpu_nice="Qualcomm SDM845"; - socket_nice="—";; ROCKCHIP_RK3288) cpu_nice="Rockchip RK3288"; socket_nice="—";; diff --git a/util/qualcomm/scripts/cmm/debug_cb_845.cmm b/util/qualcomm/scripts/cmm/debug_cb_845.cmm deleted file mode 100644 index 696f1c0868..0000000000 --- a/util/qualcomm/scripts/cmm/debug_cb_845.cmm +++ /dev/null @@ -1,113 +0,0 @@ -;============================================================================ -;## SPDX-License-Identifier: GPL-2.0-only -;============================================================================ -; Name: -; debug_cb_845.cmm -; -; Description: -; Debug coreboot 845 front-end -;============================================================================ - -;============================================================================ -; CMM script variables -;============================================================================ - -LOCAL &TargetPkg - -GLOBAL &BBEntryAddr // Bootblock Entry -GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec -GLOBAL &VEREntryAddr // Verstage Entry -GLOBAL &ROMEntryAddr // Romstage Entry -GLOBAL &QCLEntryAddr // QCLstage Entry -GLOBAL &RAMEntryAddr // Ramstage Entry -GLOBAL &BL31EntryAddr // BL31 Entry -GLOBAL &DCEntryAddr // Depthcharge Entry -GLOBAL &KernelEntryAddr // Kernel Entry - -GLOBAL &PreRamConsoleAddr -GLOBAL &RamConsoleAddr -GLOBAL &PreRamCbfsCache -GLOBAL &VBoot2Work -GLOBAL &Stack -GLOBAL &Ttb -GLOBAL &Timestamp -GLOBAL &CbmemTop -GLOBAL &PostRamCbfsCache - -GLOBAL &CBTablePtr - -;============================================================================ - -;--------------------------------------------------- -; Entry point -;--------------------------------------------------- -ENTRY &ImageName - - // Later these can be parameterized - &TargetPkg="Sdm845Pkg" - - // These settings come from .../src/soc/qualcomm/sdm845/include/soc/memlayout.ld - &BBEntryAddr=0x14816000 - &VEREntryAddr=0x14680000 - &ROMEntryAddr=0x14680000 - &QCLEntryAddr=0x1485AC00 - &RAMEntryAddr=0x9F860000 - &BL31EntryAddr=0x06820000 - &DCEntryAddr=0xB0104800 - &KernelEntryAddr=0x90080000 - - &PreRamConsoleAddr=0x14836400 - &VBoot2Work=0x1482E000 - &Stack=0x14832000 - &Ttb=0x1481E000 - &Timestamp=0x14836000 - &PreRamCbfsCache=0x1483E400 - &CbmemTop=0x280000000 - &PostRamCbfsCache=0x9F800000 - // End of memlayout.ld settings - - // Common commands irrespective of &Mode - PATH - &CwDir=os.pwd() - PATH + &CwDir - - // position at top of coreboot tree - // find depth count for source loading - cd ..\..\..\.. - &srcpath=os.pwd() - - b.sel PROGRAM onchip - sys.u - - b.d /all - - go &BBEntryAddr - wait !run() - -;--------------------------------------------------- -; Setup area and log -;--------------------------------------------------- - area.clear - area.reset - area.create CB_Logs 1000. 8192. - area.select CB_Logs - - winclear - b.d /all - - if FILE.EXIST("C:\TEMP\WIN.CMM") - do C:\TEMP\WIN.CMM - - area.view CB_Logs - - PRINT %String "Source Path: &srcpath" - - symbol.sourcepath.setbasedir &srcpath\src - - // Make parsing simple, upper-case parameters - &ImageName=STRING.UPR("&ImageName") - PRINT "&ImageName" - - DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName - - enddo From 4e8a9c705398e269c6534dffc54c20f8009b3d76 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 11 Nov 2020 23:07:18 +0530 Subject: [PATCH 199/262] soc/intel/alderlake: Add PCH ID 0x5181 List of changes: 1. Add new PCH ID 0x5181 into device/pci_ids.h 2. Update new PCH ID into common lpc.c 3. Add new PCH ID description into report_platform.c TEST=Able to build and boot ADLRVP with new PCH ID. Change-Id: I4343b7343876eb40c2955f6f4dd99d6446852dc0 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/47474 Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 1 + src/soc/intel/alderlake/bootblock/report_platform.c | 1 + src/soc/intel/common/block/lpc/lpc.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 36c5dc6d03..675acc4a1b 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2926,6 +2926,7 @@ #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29 0x7a1d #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30 0x7a1e #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31 0x7a1f +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32 0x5181 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0 0x7a80 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1 0x7a81 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2 0x7a82 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 38e909c73d..f0d8f2bdc3 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -78,6 +78,7 @@ static struct { { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29, "Alderlake-P SKU" }, { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, "Alderlake-P SKU" }, { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, "Alderlake-P SKU" }, }; static struct { diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 28c030f032..d11aa10a8f 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -305,6 +305,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_29, PCI_DEVICE_ID_INTEL_ADP_S_ESPI_30, PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, 0 }; From 81547dd5460ad220e398c531b5d43fd9e8b90c73 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Wed, 11 Nov 2020 19:20:17 +0100 Subject: [PATCH 200/262] mb/*/Kconfig: Annotate closing endif with corresponding condition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It’s common to annotate the closing endif, so do it for these four files. Change-Id: Ia5d071e1f544c9dea5af9c6bc3c605d9a0c5c0f5 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/47477 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- src/mainboard/clevo/Kconfig | 2 +- src/mainboard/razer/Kconfig | 2 +- src/mainboard/system76/Kconfig | 2 +- src/mainboard/up/Kconfig | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/clevo/Kconfig b/src/mainboard/clevo/Kconfig index d5ae6c1b02..1c95d2b420 100644 --- a/src/mainboard/clevo/Kconfig +++ b/src/mainboard/clevo/Kconfig @@ -12,4 +12,4 @@ source "src/mainboard/clevo/*/Kconfig" config MAINBOARD_VENDOR default "Clevo" -endif +endif # VENDOR_CLEVO diff --git a/src/mainboard/razer/Kconfig b/src/mainboard/razer/Kconfig index 9d96888c7f..9f9c6fd4ee 100644 --- a/src/mainboard/razer/Kconfig +++ b/src/mainboard/razer/Kconfig @@ -12,4 +12,4 @@ source "src/mainboard/razer/*/Kconfig" config MAINBOARD_VENDOR default "RAZER" -endif +endif # VENDOR_RAZER diff --git a/src/mainboard/system76/Kconfig b/src/mainboard/system76/Kconfig index 785d117ad5..296f701e4c 100644 --- a/src/mainboard/system76/Kconfig +++ b/src/mainboard/system76/Kconfig @@ -12,4 +12,4 @@ source "src/mainboard/system76/*/Kconfig" config MAINBOARD_VENDOR default "System76" -endif +endif # VENDOR_SYSTEM76 diff --git a/src/mainboard/up/Kconfig b/src/mainboard/up/Kconfig index aa8eda66b5..fdb3e71a5b 100644 --- a/src/mainboard/up/Kconfig +++ b/src/mainboard/up/Kconfig @@ -12,4 +12,4 @@ source "src/mainboard/up/*/Kconfig" config MAINBOARD_VENDOR default "UP" -endif +endif # VENDOR_UP From b64db833d6db452c28e410f869f6527fd6971228 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Thu, 5 Nov 2020 10:41:26 +0100 Subject: [PATCH 201/262] drivers/i2c/rx6110sa: Add basic ACPI support This patch adds basic ACPI support for the RTC so that the OS is able to use this RTC via the ACPI interface. If the Linux kernel is able to find the RTC in ACPI scope, you should see the following lines in dmesg, where [n] is an enumerated number: rx6110 i2c-RX6110SA:00: rtc core: registered RX6110SA:00 as rtc[n] rtc rtc[n]: Update timer was detected Change-Id: I9b319e3088e6511592075b055f8fa3e2aedaa209 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/47235 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/drivers/i2c/rx6110sa/chip.h | 1 + src/drivers/i2c/rx6110sa/rx6110sa.c | 67 ++++++++++++++++++++++++++++- src/drivers/i2c/rx6110sa/rx6110sa.h | 4 ++ 3 files changed, 70 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/rx6110sa/chip.h b/src/drivers/i2c/rx6110sa/chip.h index 46ef7f1e3a..4df95806ac 100644 --- a/src/drivers/i2c/rx6110sa/chip.h +++ b/src/drivers/i2c/rx6110sa/chip.h @@ -3,6 +3,7 @@ #include "rx6110sa.h" struct drivers_i2c_rx6110sa_config { + unsigned int bus_speed; /* Bus clock in Hz (default 400 kHz)*/ /* The day (of the week) is indicated by 7 bits, bit 0 to bit 6. */ unsigned char user_weekday; /* User day of the week to set */ unsigned char user_day; /* User day to set */ diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index ca39bdb1bc..2b8b9b28f0 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -1,7 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include +#include #include +#include +#include #include #include #include @@ -163,11 +166,71 @@ static void rx6110sa_init(struct device *dev) rx6110sa_write(dev, CTRL_REG, reg); } +#if CONFIG(HAVE_ACPI_TABLES) +static void rx6110sa_fill_ssdt(const struct device *dev) +{ + struct drivers_i2c_rx6110sa_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + enum i2c_speed bus_speed; + + if (!scope) + return; + + switch (config->bus_speed) { + case I2C_SPEED_STANDARD: + case I2C_SPEED_FAST: + bus_speed = config->bus_speed; + break; + default: + printk(BIOS_INFO, "%s: Bus speed unsupported, fall back to %d kHz!\n", + dev_path(dev), I2C_SPEED_STANDARD / 1000); + bus_speed = I2C_SPEED_STANDARD; + break; + } + + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = bus_speed, + .resource = scope, + }; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", RX6110SA_HID_NAME); + acpigen_write_name_string("_DDN", RX6110SA_HID_DESC); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + + acpigen_write_resourcetemplate_footer(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), + dev->chip_ops->name, dev_path(dev)); +} + +static const char *rx6110sa_acpi_name(const struct device *dev) +{ + return RX6110SA_ACPI_NAME; +} +#endif + static struct device_operations rx6110sa_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = rx6110sa_init, - .final = rx6110sa_final + .final = rx6110sa_final, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = rx6110sa_acpi_name, + .acpi_fill_ssdt = rx6110sa_fill_ssdt, +#endif }; static void rx6110sa_enable(struct device *dev) diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.h b/src/drivers/i2c/rx6110sa/rx6110sa.h index 187bad424f..73f43b3a5b 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.h +++ b/src/drivers/i2c/rx6110sa/rx6110sa.h @@ -7,6 +7,10 @@ #define RX6110SA_SLAVE_ADR 0x32 #define RX6110SA_I2C_CONTROLLER 0 +#define RX6110SA_ACPI_NAME "ERX6" +#define RX6110SA_HID_NAME "RX6110SA" +#define RX6110SA_HID_DESC "Real Time Clock" + /* Register layout */ #define SECOND_REG 0x10 #define MINUTE_REG 0x11 From 04ebdd9710fc62d0ed3f1388e37125eafc80f0d9 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Thu, 5 Nov 2020 10:55:21 +0100 Subject: [PATCH 202/262] drivers/i2c/rx6110sa: Delete unused defines The defines for RX6110SA_SLAVE_ADR and RX6110SA_I2C_CONTROLLER are not used anymore and can be deleted. Change-Id: I3cddf7a9e2f757a22c729ae0f0ff767d55909b9c Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/47236 Tested-by: build bot (Jenkins) Tested-by: siemens-bot Reviewed-by: Mario Scheithauer --- src/drivers/i2c/rx6110sa/rx6110sa.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.h b/src/drivers/i2c/rx6110sa/rx6110sa.h index 73f43b3a5b..557a7489a1 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.h +++ b/src/drivers/i2c/rx6110sa/rx6110sa.h @@ -3,10 +3,6 @@ #ifndef _I2C_RX6110SA_H_ #define _I2C_RX6110SA_H_ -/* The address of this RTC is fixed. */ -#define RX6110SA_SLAVE_ADR 0x32 -#define RX6110SA_I2C_CONTROLLER 0 - #define RX6110SA_ACPI_NAME "ERX6" #define RX6110SA_HID_NAME "RX6110SA" #define RX6110SA_HID_DESC "Real Time Clock" From 83b262275c43a2ff29c9d9364f25483fd690b803 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 6 Nov 2020 11:50:55 +0100 Subject: [PATCH 203/262] soc/intel/xeon_sp: Use a common function to get the IIO HOB TESTED ocp/deltalake still boots. Change-Id: I69f336c1ff348b8e820340b84494929f2c58ce72 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47296 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/soc_util.c | 8 +------- src/soc/intel/xeon_sp/nb_acpi.c | 10 ++-------- src/soc/intel/xeon_sp/skx/soc_acpi.c | 6 ++---- src/soc/intel/xeon_sp/skx/soc_util.c | 15 ++------------- 4 files changed, 7 insertions(+), 32 deletions(-) diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 973d2588c5..d2d12d1eba 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -29,13 +29,7 @@ const struct SystemMemoryMapHob *get_system_memory_map(void) uint8_t get_iiostack_info(struct iiostack_resource *info) { - size_t hob_size; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob; - - hob = fsp_find_extension_hob_by_guid( - fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); + const IIO_UDS *hob = get_iio_uds(); // copy IIO Stack info from FSP HOB info->no_of_stacks = 0; diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 4a29c0868f..55c3d820ca 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -362,10 +362,7 @@ static unsigned long acpi_create_rmrr(unsigned long current) static unsigned long acpi_create_rhsa(unsigned long current) { - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); + const IIO_UDS *hob = get_iio_uds(); for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { IIO_RESOURCE_INSTANCE iio_resource = @@ -386,10 +383,7 @@ static unsigned long acpi_create_rhsa(unsigned long current) static unsigned long acpi_fill_dmar(unsigned long current) { - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); + const IIO_UDS *hob = get_iio_uds(); // DRHD for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) { diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 95563f5837..3ac46ffcfa 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -17,6 +17,7 @@ #include #include #include +#include /* TODO: Check if the common/acpi weak function can be used */ unsigned long acpi_fill_mcfg(unsigned long current) @@ -99,10 +100,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) void uncore_inject_dsdt(const struct device *device) { - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); + const IIO_UDS *hob = get_iio_uds(); /* Only add RTxx entries once. */ if (device->bus->secondary != 0) diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 469fd60b5f..af6dfcc341 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -57,13 +57,7 @@ const struct SystemMemoryMapHob *get_system_memory_map(void) uint8_t get_iiostack_info(struct iiostack_resource *info) { - size_t hob_size; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob; - - hob = fsp_find_extension_hob_by_guid( - fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); + const IIO_UDS *hob = get_iio_uds(); // copy IIO Stack info from FSP HOB info->no_of_stacks = 0; @@ -83,15 +77,10 @@ uint8_t get_iiostack_info(struct iiostack_resource *info) uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) { - size_t hob_size; - const IIO_UDS *hob; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = get_iio_uds(); assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK); - hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; } From 40ac196ba3f754872442662ec282ee033304292c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 22 Sep 2020 22:59:16 +0200 Subject: [PATCH 204/262] mb/clevo/l140cu: add CMOS layout and defaults MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add CMOS layout and defaults files and enable CMOS options in Kconfig. Test: changed loglevel setting, rebooted and checked the log. Change-Id: Ia1a27818b2d12fb7578189e5748b8073c8f928e3 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46311 Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/mainboard/clevo/cml-u/Kconfig | 2 + src/mainboard/clevo/cml-u/cmos.default | 3 ++ src/mainboard/clevo/cml-u/cmos.layout | 61 ++++++++++++++++++++++++++ 3 files changed, 66 insertions(+) create mode 100644 src/mainboard/clevo/cml-u/cmos.default create mode 100644 src/mainboard/clevo/cml-u/cmos.layout diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig index c08b321630..57c9f58f37 100644 --- a/src/mainboard/clevo/cml-u/Kconfig +++ b/src/mainboard/clevo/cml-u/Kconfig @@ -9,6 +9,8 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select HAVE_SMI_HANDLER select HAVE_SPD_IN_CBFS + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/clevo/cml-u/cmos.default b/src/mainboard/clevo/cml-u/cmos.default new file mode 100644 index 0000000000..f3330e5070 --- /dev/null +++ b/src/mainboard/clevo/cml-u/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable diff --git a/src/mainboard/clevo/cml-u/cmos.layout b/src/mainboard/clevo/cml-u/cmos.layout new file mode 100644 index 0000000000..45ddff109f --- /dev/null +++ b/src/mainboard/clevo/cml-u/cmos.layout @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# start-bit length config config-ID name +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: cpu +400 1 e 2 hyper_threading + +# ----------------------------------------------------------------- +# coreboot config options: southbridge +410 2 e 7 power_on_after_fail + +# ----------------------------------------------------------------- +# vboot nv area +800 128 r 0 vbnv + +# ----------------------------------------------------------------- +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 799 984 From c0de5843200e06f587f536eb60adc6bfee47c2aa Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 11 Nov 2020 21:38:27 +0100 Subject: [PATCH 205/262] mb/amd/mandolin/Kconfig: add help text for the EC blob Change-Id: If8d3ebdb9a41330312c26fb5796c07de1b87b3eb Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47480 Reviewed-by: Marshall Dawson Reviewed-by: Jason Glenesk Tested-by: build bot (Jenkins) --- src/mainboard/amd/mandolin/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index f4032d4e1d..099f7cbe3f 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -72,6 +72,9 @@ config MANDOLIN_MCHP_FW_FILE depends on MANDOLIN_HAVE_MCHP_FW default "3rdparty/blobs/mainboard/amd/mandolin/EC_mandolin.bin" if BOARD_AMD_MANDOLIN default "3rdparty/blobs/mainboard/amd/mandolin/EC_cereme.bin" if BOARD_AMD_CEREME + help + The EC firmware blob is usually the first 128kByte of the stock + firmware image. if !AMD_LPC_DEBUG_CARD choice From 88c16f6ee78a26a2c6ffe2dd3ee1b7fa75283b39 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 11 Nov 2020 23:46:58 +0100 Subject: [PATCH 206/262] mb/amd/mandolin/Kconfig: update help text for AMD_LPC_DEBUG_CARD The existing help text wasn't updated for Mandolin after it was copied from an older reference board and contained some information that doesn't apply to Mandolin. Change-Id: Ib34abb2ee8b289df5f7085957042fe00ad506ca9 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47481 Tested-by: build bot (Jenkins) Reviewed-by: Jason Glenesk Reviewed-by: Marshall Dawson --- src/mainboard/amd/mandolin/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 099f7cbe3f..dde7ac8bed 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -24,10 +24,10 @@ config AMD_LPC_DEBUG_CARD select PICASSO_LPC_IOMUX select SUPERIO_SMSC_SIO1036 help - AMD's debug card contains an SMSC SIO1036 device which provides - an I/O-based UART in the system. This feature is not compatible with - CONFIG_HUDSON_UART enabling the memory-mapped UART in the chipset. - Note that Kconfig does not currently enforce this restriction. + AMD's debug card contains an SMSC SIO1036 device which provides an + I/O-mapped UART in the system. This is mutually exclusive with + PICASSO_CONSOLE_UART which selects the SoC's integrated memory-mapped + UART for coreboot console output. config CBFS_SIZE hex From c7eebacbebcc6ba5cfaa321e7793e4e81f98415e Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 6 Nov 2020 12:25:28 +0100 Subject: [PATCH 207/262] soc/intel/xeon_sp: Tidy up adding MADT ioapic entries Add a helper function to print out debug info and add the MADT entry. Change-Id: I1a00f87c6edef530c5352929ee9279782be4b112 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47299 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Marc Jones --- src/soc/intel/xeon_sp/acpi.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index d33d1d0cea..5a77bf3b02 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -73,6 +73,16 @@ static unsigned long acpi_madt_irq_overrides(unsigned long current) return current; } +static unsigned long add_madt_ioapic(unsigned long current, int stack, int ioapic_id, + uint32_t ioapic_base, int gsi_base) +{ + printk(BIOS_DEBUG, "Adding MADT IOAPIC for stack: %d, ioapic_id: 0x%x, " + "ioapic_base: 0x%x, gsi_base: 0x%x\n", + stack, ioapic_id, ioapic_base, gsi_base); + return acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, ioapic_id, + ioapic_base, gsi_base); +} + unsigned long acpi_fill_madt(unsigned long current) { int cur_index; @@ -100,12 +110,8 @@ unsigned long acpi_fill_madt(unsigned long current) assert(cur_index < ARRAY_SIZE(gsi_bases)); int ioapic_id = ioapic_ids[cur_index]; int gsi_base = gsi_bases[cur_index]; - printk(BIOS_DEBUG, "Adding MADT IOAPIC for stack: %d, ioapic_id: 0x%x, " - "ioapic_base: 0x%x, gsi_base: 0x%x\n", - stack, ioapic_id, ri->IoApicBase, gsi_base); - current += acpi_create_madt_ioapic( - (acpi_madt_ioapic_t *)current, - ioapic_id, ri->IoApicBase, gsi_base); + current += add_madt_ioapic(current, stack, ioapic_id, ri->IoApicBase, + gsi_base); ++cur_index; /* @@ -117,13 +123,8 @@ unsigned long acpi_fill_madt(unsigned long current) assert(cur_index < ARRAY_SIZE(gsi_bases)); ioapic_id = ioapic_ids[cur_index]; gsi_base = gsi_bases[cur_index]; - printk(BIOS_DEBUG, "Adding MADT IOAPIC for stack: %d, ioapic_id: 0x%x, " - "ioapic_base: 0x%x, gsi_base: 0x%x\n", - stack, ioapic_id, - ri->IoApicBase + 0x1000, gsi_base); - current += acpi_create_madt_ioapic( - (acpi_madt_ioapic_t *)current, - ioapic_id, ri->IoApicBase + 0x1000, gsi_base); + current += add_madt_ioapic(current, stack, ioapic_id, + ri->IoApicBase + 0x1000, gsi_base); ++cur_index; } } From 5fd29317e830c3bb2052f7e69cfb1d493e6d425c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 13 Nov 2020 01:13:46 +0100 Subject: [PATCH 208/262] MAINTAINERS: add trailing slash to make gerrit add me as reviewer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The trailing slash is required to make gerrit add me on changes for the whole tree, not just for the directory itself, which obviously would only change if being deleted or renamed. This also fixes the behaviour for Felix Singer. Change-Id: I601aebd4335c7326deca0118725a6f25cec524a9 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/47547 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index ba88813509..9a31a3f646 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -212,7 +212,7 @@ CLEVO MAINBOARDS M: Felix Singer M: Michael Niewöhner S: Supported -F: src/mainboard/clevo +F: src/mainboard/clevo/ @@ -401,7 +401,7 @@ F: src/mainboard/supermicro/x10slm-f/ SUPERMICRO X11-LGA1151-SERIES M: Michael Niewöhner S: Maintained -F: src/mainboard/supermicro/x11-lga1151-series +F: src/mainboard/supermicro/x11-lga1151-series/ ################################################################################ # Architectures From 161de9f80fbb6ae84764fd28b3440f6e89059a35 Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Tue, 10 Nov 2020 16:32:14 +0800 Subject: [PATCH 209/262] mb/google/dedede/var/metaknight: Disable I2C port 3 Disable I2C port 3 for metaknight BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: Ic4a056d53a8c8abd04a9b786428da0986a255276 Signed-off-by: Tim Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/47389 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- .../dedede/variants/metaknight/overridetree.cb | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 404024b1d6..556a44f5eb 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -11,7 +11,7 @@ chip soc/intel/jasperlake #| I2C0 | Trackpad | #| I2C1 | Digitizer | #| I2C2 | Touchscreen | - #| I2C3 | Camera | + #| I2C3 | TBD | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -28,15 +28,22 @@ chip soc/intel/jasperlake .i2c[2] = { .speed = I2C_SPEED_FAST, }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, .i2c[4] = { .speed = I2C_SPEED_FAST, }, }" + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + device domain 0 on device pci 15.0 on end + device pci 15.3 off end # I2C 3 end end From 1f0e6e738436ace8ec9667d23c56fcfb746135a7 Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Tue, 10 Nov 2020 17:16:55 +0800 Subject: [PATCH 210/262] mb/google/dedede/var/metaknight: enable USB2 port for camera Enable USB2 port 5 for user facing camera. Enable USB2 port 6 for world facing camera. BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: Iecb7787d46eab7096dec9f838a16da101105e09a Signed-off-by: Tim Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/47391 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- .../variants/metaknight/overridetree.cb | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 556a44f5eb..d5903f6f8e 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -1,5 +1,9 @@ chip soc/intel/jasperlake + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # User Facing Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # World Facing Camera + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -43,6 +47,22 @@ chip soc/intel/jasperlake }" device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""User Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""World Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + end + end + end # USB xHCI device pci 15.0 on end device pci 15.3 off end # I2C 3 end From a879200843bb8d37658a8104d3583564de2b9dcc Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 10 Nov 2020 12:29:37 -0700 Subject: [PATCH 211/262] mb/google/dedede: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=emerge-dedede coreboot Change-Id: I9d8fa57ae0f554896a4a0722e3e89567676382d4 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47415 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/dedede/variants/boten/overridetree.cb | 4 ++-- .../google/dedede/variants/drawcia/overridetree.cb | 6 +++--- src/mainboard/google/dedede/variants/madoo/overridetree.cb | 2 +- .../google/dedede/variants/magolor/overridetree.cb | 6 +++--- .../google/dedede/variants/waddledee/overridetree.cb | 6 +++--- .../google/dedede/variants/waddledoo/overridetree.cb | 4 ++-- 6 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 4966aac491..d2540e3d15 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -108,7 +108,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" register "generic.wake" = "GPE0_DW0_03" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -131,7 +131,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 574ae38db0..45d0b32d62 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -171,7 +171,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" register "generic.reset_delay_ms" = "50" @@ -185,7 +185,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" register "generic.reset_delay_ms" = "120" @@ -199,7 +199,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""ELAN2513"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" register "generic.reset_delay_ms" = "20" diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb index c284f7a643..1be1012123 100644 --- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb @@ -113,7 +113,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 33b89d605b..d502c915d6 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -135,7 +135,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" register "generic.wake" = "GPE0_DW0_03" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -154,7 +154,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" register "generic.reset_delay_ms" = "120" @@ -169,7 +169,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""ELAN6915"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" register "generic.reset_delay_ms" = "20" diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb index b67b8702c6..d594dbdeb7 100644 --- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb @@ -78,7 +78,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" register "generic.wake" = "GPE0_DW0_03" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -89,7 +89,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""SIS6496"" register "generic.desc" = ""SIS Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" @@ -106,7 +106,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index c306b523ea..360f50adac 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -102,7 +102,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""SIS6496"" register "generic.desc" = ""SIS Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" @@ -119,7 +119,7 @@ chip soc/intel/jasperlake chip drivers/i2c/hid register "generic.hid" = ""ELAN9050"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" From 029e7361727bb940f4c184b7e825a0491b50a632 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 10 Nov 2020 13:41:31 -0700 Subject: [PATCH 212/262] mb/google/volteer: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ie7b82ea07ef97b2096d75229c445bd3a65cb3be0 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47416 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../google/volteer/variants/delbin/overridetree.cb | 2 +- .../google/volteer/variants/eldrid/overridetree.cb | 4 ++-- src/mainboard/google/volteer/variants/elemi/overridetree.cb | 2 +- .../google/volteer/variants/halvor/overridetree.cb | 4 ++-- .../google/volteer/variants/lindar/overridetree.cb | 2 +- .../google/volteer/variants/malefor/overridetree.cb | 2 +- .../google/volteer/variants/terrador/overridetree.cb | 6 +++--- src/mainboard/google/volteer/variants/todor/overridetree.cb | 6 +++--- .../google/volteer/variants/trondo/overridetree.cb | 4 ++-- .../google/volteer/variants/volteer/overridetree.cb | 4 ++-- .../google/volteer/variants/volteer2/overridetree.cb | 4 ++-- src/mainboard/google/volteer/variants/voxel/overridetree.cb | 4 ++-- 12 files changed, 22 insertions(+), 22 deletions(-) diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index e2beb039f9..5b9caa060e 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -119,7 +119,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN9008"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 91fbbea5d0..f9ab7c95d3 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -119,7 +119,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -136,7 +136,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 5ea48ad038..4afc795afd 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -138,7 +138,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index a786bddd09..568ca73c3b 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -49,7 +49,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -64,7 +64,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 87ca0a38cf..a318ccaac9 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -42,7 +42,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index c5c0180d2a..ec9bd67ca9 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -49,7 +49,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index efb2af822e..c3b5df7703 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -103,7 +103,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -118,7 +118,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -166,7 +166,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN2700"" register "generic.desc" = ""ELAN Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E15_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" register "generic.wake" = "GPE0_DW2_15" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x01" diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index fbf724f601..2c95b1635b 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -105,7 +105,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -120,7 +120,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -168,7 +168,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN2700"" register "generic.desc" = ""ELAN Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E15_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" register "generic.wake" = "GPE0_DW2_15" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x01" diff --git a/src/mainboard/google/volteer/variants/trondo/overridetree.cb b/src/mainboard/google/volteer/variants/trondo/overridetree.cb index e1db3d6df0..7169932ae4 100644 --- a/src/mainboard/google/volteer/variants/trondo/overridetree.cb +++ b/src/mainboard/google/volteer/variants/trondo/overridetree.cb @@ -6,7 +6,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -21,7 +21,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 75dbc57a95..f23ef76393 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -103,7 +103,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -124,7 +124,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 1cb0b52b03..e4da0e6252 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -150,7 +150,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -171,7 +171,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index ef5e0b7987..d2b1354722 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -104,7 +104,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" @@ -119,7 +119,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" From 86dc4b70724678d931fbce8a0286886539b0d94f Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 10 Nov 2020 13:46:26 -0700 Subject: [PATCH 213/262] mb/google/hatch: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I320198d56131cf54e0f73227479f69968719b2a7 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47417 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/akemi/overridetree.cb | 4 ++-- src/mainboard/google/hatch/variants/dooly/overridetree.cb | 2 +- src/mainboard/google/hatch/variants/dratini/overridetree.cb | 6 +++--- src/mainboard/google/hatch/variants/hatch/overridetree.cb | 2 +- src/mainboard/google/hatch/variants/jinlon/overridetree.cb | 6 +++--- src/mainboard/google/hatch/variants/kindred/overridetree.cb | 4 ++-- src/mainboard/google/hatch/variants/kohaku/overridetree.cb | 2 +- src/mainboard/google/hatch/variants/mushu/overridetree.cb | 2 +- .../google/hatch/variants/nightfury/overridetree.cb | 2 +- src/mainboard/google/hatch/variants/stryke/overridetree.cb | 2 +- 10 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 2d60271d01..8ae350c509 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -172,7 +172,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "generic.wake" = "GPE0_DW0_21" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -196,7 +196,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index 8ced613fde..6e23448747 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -315,7 +315,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""WDHT2002"" register "generic.desc" = ""WDT Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A20_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A20_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "100" diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index c5e2aeb2bd..6ec1a48add 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -83,7 +83,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "50" @@ -111,7 +111,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "120" @@ -127,7 +127,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""ELAN2513"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "20" diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 76f634f0d7..e13270f85f 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -94,7 +94,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index f042401b0c..750e068bb6 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -107,7 +107,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "50" @@ -135,7 +135,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "120" @@ -151,7 +151,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""ELAN2513"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "20" diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index c75b7ba8c5..c06f35b9cb 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -117,7 +117,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "generic.wake" = "GPE0_DW0_21" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -156,7 +156,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""ELAN9004"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "20" diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 1b91e8f5ed..740a7d86ff 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -154,7 +154,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "generic.probed" = "1" register "generic.wake" = "GPE0_DW0_21" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 4e4d3888bd..29b87e4ce2 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -114,7 +114,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index d6be1fb6fc..ff61d80906 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -205,7 +205,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""ELAN902C"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb index 536cd43de8..3611e582b3 100644 --- a/src/mainboard/google/hatch/variants/stryke/overridetree.cb +++ b/src/mainboard/google/hatch/variants/stryke/overridetree.cb @@ -172,7 +172,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" From ff630715cef7848f0595c5f4d2023389ba5c5295 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 10 Nov 2020 14:30:44 -0700 Subject: [PATCH 214/262] mb/google/deltaur: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I1773973f64bcc5ef6bd1856c5d8eb998bb6a4888 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47418 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/deltaur/variants/deltan/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb index 01935c549b..44cc835d1f 100644 --- a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb +++ b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb @@ -31,7 +31,7 @@ chip soc/intel/tigerlake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Cirque Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.wake" = "GPE0_DW1_07" register "hid_desc_reg_offset" = "0x20" From 62e957d0296c3f4ce7682300272f223796a782ee Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 10 Nov 2020 14:34:26 -0700 Subject: [PATCH 215/262] mb/google/drallion: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Iff00667377eecedcf0b83bcfc0bf50bd4c3411eb Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47419 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index f3ce6286be..90bd260207 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -359,7 +359,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" From 132e969ca86aa6343d9f388be0f8dc7d8251b1e4 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 10 Nov 2020 14:36:31 -0700 Subject: [PATCH 216/262] mb/google/zork: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I75a92616f11054993ff5a5bfefce5c3f4638c07c Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47420 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/zork/variants/berknip/overridetree.cb | 4 ++-- src/mainboard/google/zork/variants/dalboz/overridetree.cb | 6 +++--- src/mainboard/google/zork/variants/dirinboz/overridetree.cb | 2 +- src/mainboard/google/zork/variants/ezkinil/overridetree.cb | 4 ++-- src/mainboard/google/zork/variants/morphius/overridetree.cb | 4 ++-- src/mainboard/google/zork/variants/trembyle/overridetree.cb | 2 +- src/mainboard/google/zork/variants/vilboz/overridetree.cb | 4 ++-- src/mainboard/google/zork/variants/woomax/overridetree.cb | 2 +- 8 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 8f6aff2ede..602b5c79de 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -109,7 +109,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "generic.wake" = "GEVENT_22" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -145,7 +145,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "generic.enable_delay_ms" = "1" diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb index 67fa077f3d..d047211f30 100644 --- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -69,7 +69,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "45" @@ -81,7 +81,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "120" @@ -103,7 +103,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "generic.wake" = "GEVENT_22" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index f3be599780..efd1dfc1fa 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -74,7 +74,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "generic.enable_delay_ms" = "1" diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index 2537ee8fc4..6f4a38e241 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -92,7 +92,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "generic.wake" = "GEVENT_22" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -117,7 +117,7 @@ chip soc/amd/picasso register "generic.hid" = ""ELAN9004"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.probed" = "1" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "generic.enable_delay_ms" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index 4ac5f81798..9d3b7ee670 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -86,7 +86,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "generic.wake" = "GEVENT_22" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -95,7 +95,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "generic.enable_delay_ms" = "10" diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb index 90020ea89c..de38ab7887 100644 --- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -58,7 +58,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "generic.wake" = "GEVENT_22" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 2f3b4fcc4e..3b3bdd4c7e 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -100,7 +100,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "generic.enable_delay_ms" = "10" @@ -153,7 +153,7 @@ chip soc/amd/picasso chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "generic.wake" = "GEVENT_22" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index 0f0e856559..abbdd927c8 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -95,7 +95,7 @@ chip soc/amd/picasso register "generic.hid" = ""ELAN9008"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.probed" = "1" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "generic.enable_delay_ms" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" From 61a5391916c44997a9a35b0841952e1475b84e06 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 10 Nov 2020 14:37:38 -0700 Subject: [PATCH 217/262] mb/google/octopus: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ic334816712370da63471135da8dd598ab02d54ef Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47421 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../google/octopus/variants/ampton/overridetree.cb | 2 +- src/mainboard/google/octopus/variants/bloog/overridetree.cb | 4 ++-- src/mainboard/google/octopus/variants/bobba/overridetree.cb | 2 +- src/mainboard/google/octopus/variants/dood/overridetree.cb | 4 ++-- src/mainboard/google/octopus/variants/fleex/overridetree.cb | 6 +++--- src/mainboard/google/octopus/variants/foob/overridetree.cb | 6 +++--- src/mainboard/google/octopus/variants/garg/overridetree.cb | 4 ++-- src/mainboard/google/octopus/variants/lick/overridetree.cb | 2 +- src/mainboard/google/octopus/variants/meep/overridetree.cb | 4 ++-- .../google/octopus/variants/phaser/overridetree.cb | 4 ++-- 10 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/mainboard/google/octopus/variants/ampton/overridetree.cb b/src/mainboard/google/octopus/variants/ampton/overridetree.cb index 3d14bea71d..cfc5e8ac78 100644 --- a/src/mainboard/google/octopus/variants/ampton/overridetree.cb +++ b/src/mainboard/google/octopus/variants/ampton/overridetree.cb @@ -124,7 +124,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""GTCH7502"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "70" diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb index 6c2aa95747..7c22ce7a09 100644 --- a/src/mainboard/google/octopus/variants/bloog/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb @@ -127,7 +127,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "120" @@ -141,7 +141,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "50" diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 20c376a713..662e6af8d6 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -178,7 +178,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index 6e767dd7d3..465078f8c3 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -112,7 +112,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -147,7 +147,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""GTCH7502"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "50" diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 2fd554ff88..77cce86be7 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -135,7 +135,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""GXTP7288"" register "generic.desc" = ""Goodix Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_135_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -158,7 +158,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""WDHT0002"" register "generic.desc" = ""WDT Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "130" @@ -172,7 +172,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "50" diff --git a/src/mainboard/google/octopus/variants/foob/overridetree.cb b/src/mainboard/google/octopus/variants/foob/overridetree.cb index 4ec6fee1c9..4161090aa6 100644 --- a/src/mainboard/google/octopus/variants/foob/overridetree.cb +++ b/src/mainboard/google/octopus/variants/foob/overridetree.cb @@ -126,7 +126,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -137,7 +137,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -150,7 +150,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" diff --git a/src/mainboard/google/octopus/variants/garg/overridetree.cb b/src/mainboard/google/octopus/variants/garg/overridetree.cb index 971d0d8b7c..38e5cdd1ab 100644 --- a/src/mainboard/google/octopus/variants/garg/overridetree.cb +++ b/src/mainboard/google/octopus/variants/garg/overridetree.cb @@ -141,7 +141,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -176,7 +176,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "50" diff --git a/src/mainboard/google/octopus/variants/lick/overridetree.cb b/src/mainboard/google/octopus/variants/lick/overridetree.cb index af6711a5fc..e2b35cb598 100644 --- a/src/mainboard/google/octopus/variants/lick/overridetree.cb +++ b/src/mainboard/google/octopus/variants/lick/overridetree.cb @@ -104,7 +104,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index 8881c9d98f..a29d6fae7a 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -208,7 +208,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""WDHT0002"" register "generic.desc" = ""WDT Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "130" @@ -222,7 +222,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "50" diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index 9ce2a0b2cf..e25f8fa093 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -126,7 +126,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -149,7 +149,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" From b2f2bd1c82fb0b393d44c1672041e621cfeaf435 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 10 Nov 2020 14:53:29 -0700 Subject: [PATCH 218/262] mb/google/kahlee: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ib2f203b5f5eea5c25cfd4543f5ed9f15101b1735 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47422 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/kahlee/variants/nuwani/devicetree.cb | 6 +++--- src/mainboard/google/kahlee/variants/treeya/devicetree.cb | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb index d7772c442d..8c9f1cd47f 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb @@ -136,7 +136,7 @@ chip soc/amd/stoneyridge chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_5)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" register "generic.wake" = "7" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -147,7 +147,7 @@ chip soc/amd/stoneyridge chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" @@ -160,7 +160,7 @@ chip soc/amd/stoneyridge chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index 1cc3d437cc..132172e750 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -136,7 +136,7 @@ chip soc/amd/stoneyridge chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_5)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" register "generic.wake" = "7" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -147,7 +147,7 @@ chip soc/amd/stoneyridge chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" From c37e1e6d071cc9c64e99cffa4250e912f70e6ef0 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 10 Nov 2020 14:54:40 -0700 Subject: [PATCH 219/262] mb/google/poppy: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ida1b1d05b39e67a9eba3bfaecca37f38821a438b Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47423 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/poppy/variants/atlas/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/nami/devicetree.cb | 6 +++--- src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 3797fb0135..668e72dc21 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -292,7 +292,7 @@ chip soc/intel/skylake chip drivers/i2c/hid register "generic.hid" = ""ACPI0C50"" register "generic.desc" = ""ELAN Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A19_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A19_IRQ)" register "generic.wake" = "GPE0_DW0_23" # GPP_A23 register "hid_desc_reg_offset" = "0x01" device i2c 0x15 on end diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index d408f9ee93..42f810800a 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -320,7 +320,7 @@ chip soc/intel/skylake chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" register "generic.enable_delay_ms" = "45" @@ -332,7 +332,7 @@ chip soc/intel/skylake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" register "generic.reset_delay_ms" = "50" @@ -355,7 +355,7 @@ chip soc/intel/skylake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" register "generic.wake" = "GPE0_DW2_16" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index b7d171b6ff..3d91884d51 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -294,7 +294,7 @@ chip soc/intel/skylake chip drivers/i2c/hid register "generic.hid" = ""SYTS7813"" register "generic.desc" = ""Synaptics Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" register "generic.enable_delay_ms" = "45" From 3614270a7646191d17b2a2cc6009e3c0bb41d47a Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 10 Nov 2020 14:57:10 -0700 Subject: [PATCH 220/262] mb/google/reef: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ifc6dd5f6549e7501f350afe8456a9a8096edcc25 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47425 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/reef/variants/coral/devicetree.cb | 2 +- src/mainboard/google/reef/variants/snappy/devicetree.cb | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index fd456ebb54..649293138d 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -220,7 +220,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)" register "generic.wake" = "GPE0_DW1_15" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 1a007e6545..3be68ddb5c 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -236,7 +236,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""WDHT0002"" register "generic.desc" = ""WDT Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "generic.reset_delay_ms" = "130" @@ -250,7 +250,7 @@ chip soc/intel/apollolake chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "generic.reset_delay_ms" = "50" From e53dfe0cfba9a773079a7229b05ed4b4c5e9e3c4 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 20:53:29 +0100 Subject: [PATCH 221/262] sb/intel/lynxpoint/acpi: Clean up cosmetics MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use ASL 2.0 syntax where possible and uniformize code style to match the IASL disassembly. Some `Store` in gpio.asl change the binary if touched. Also remove outdated comment and remove `LynxPoint` from `serialio.asl`. Tested with BUILD_TIMELESS=1, Google Panther does not change. Change-Id: Ie0994fa546ff54ebb533afcc6205efb36da99a67 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46777 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../intel/lynxpoint/acpi/audio.asl | 4 +- .../intel/lynxpoint/acpi/globalnvs.asl | 44 ++--- src/southbridge/intel/lynxpoint/acpi/gpio.asl | 27 ++- src/southbridge/intel/lynxpoint/acpi/lpc.asl | 70 +++---- src/southbridge/intel/lynxpoint/acpi/pch.asl | 10 +- .../intel/lynxpoint/acpi/serialio.asl | 166 ++++++++-------- src/southbridge/intel/lynxpoint/acpi/usb.asl | 180 ++++++++---------- 7 files changed, 243 insertions(+), 258 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/audio.asl b/src/southbridge/intel/lynxpoint/acpi/audio.asl index 2bae304500..98cdac9a90 100644 --- a/src/southbridge/intel/lynxpoint/acpi/audio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/audio.asl @@ -8,8 +8,8 @@ Device (HDEF) { Name (_ADR, 0x001b0000) - Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H - Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP + Name (PRWH, Package (){ 0x0d, 3 }) // LPT-H + Name (PRWL, Package (){ 0x6d, 3 }) // LPT-LP Method (_PRW, 0) { // Power Resources for Wake If (\ISLP ()) { diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index ee2d8000bc..ccf9b087b3 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -11,7 +11,7 @@ Name (\PICM, 0) // IOAPIC/8259 * we have to fix it up in coreboot's ACPI creation phase. */ -External(NVSA) +External (NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0xf00) Field (GNVS, ByteAcc, NoLock, Preserve) { @@ -112,41 +112,41 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* Set flag to enable USB charging in S3 */ Method (S3UE) { - Store (One, \S3U0) - Store (One, \S3U1) + \S3U0 = 1 + \S3U1 = 1 } /* Set flag to disable USB charging in S3 */ Method (S3UD) { - Store (Zero, \S3U0) - Store (Zero, \S3U1) + \S3U0 = 0 + \S3U1 = 0 } /* Set flag to enable USB charging in S5 */ Method (S5UE) { - Store (One, \S5U0) - Store (One, \S5U1) + \S5U0 = 1 + \S5U1 = 1 } /* Set flag to disable USB charging in S5 */ Method (S5UD) { - Store (Zero, \S5U0) - Store (Zero, \S5U1) + \S5U0 = 0 + \S5U1 = 0 } /* Set flag to enable 3G module in S3 */ Method (S3GE) { - Store (One, \S33G) + \S33G = 1 } /* Set flag to disable 3G module in S3 */ Method (S3GD) { - Store (Zero, \S33G) + \S33G = 0 } External (\_TZ.SKIN) @@ -169,46 +169,46 @@ Method (TZUP) /* Update Fan 0 thresholds */ Method (F0UT, 2) { - Store (Arg0, \F0OF) - Store (Arg1, \F0ON) + \F0OF = Arg0 + \F0ON = Arg1 TZUP () } /* Update Fan 1 thresholds */ Method (F1UT, 2) { - Store (Arg0, \F1OF) - Store (Arg1, \F1ON) + \F1OF = Arg0 + \F1ON = Arg1 TZUP () } /* Update Fan 2 thresholds */ Method (F2UT, 2) { - Store (Arg0, \F2OF) - Store (Arg1, \F2ON) + \F2OF = Arg0 + \F2ON = Arg1 TZUP () } /* Update Fan 3 thresholds */ Method (F3UT, 2) { - Store (Arg0, \F3OF) - Store (Arg1, \F3ON) + \F3OF = Arg0 + \F3ON = Arg1 TZUP () } /* Update Fan 4 thresholds */ Method (F4UT, 2) { - Store (Arg0, \F4OF) - Store (Arg1, \F4ON) + \F4OF = Arg0 + \F4ON = Arg1 TZUP () } /* Update Temperature Sensor ID */ Method (TMPU, 1) { - Store (Arg0, \TMPS) + \TMPS = Arg0 TZUP () } diff --git a/src/southbridge/intel/lynxpoint/acpi/gpio.asl b/src/southbridge/intel/lynxpoint/acpi/gpio.asl index 7f30307cab..1a50968617 100644 --- a/src/southbridge/intel/lynxpoint/acpi/gpio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/gpio.asl @@ -7,7 +7,7 @@ Device (GPIO) Name (_CID, "INT33C7") Name (_UID, 1) - Name (RBUF, ResourceTemplate() + Name (RBUF, ResourceTemplate () { DWordIo (ResourceProducer, MinFixed, // IsMinFixed @@ -33,10 +33,9 @@ Device (GPIO) CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) CreateDwordField (^RBUF, ^BAR0._LEN, BLEN) - Store (DEFAULT_GPIOSIZE, BLEN) - Store (DEFAULT_GPIOBASE, BMIN) - Store (Subtract (Add (DEFAULT_GPIOBASE, - DEFAULT_GPIOSIZE), 1), BMAX) + BLEN = DEFAULT_GPIOSIZE + BMIN = DEFAULT_GPIOBASE + BMAX = DEFAULT_GPIOBASE + DEFAULT_GPIOSIZE - 1 Return (RBUF) } @@ -51,7 +50,7 @@ Device (GPIO) Method (GWAK, 1, NotSerialized) { // Local0 = GPIO Base Address - Store (And (GPBS, Not(0x1)), Local0) + Store (GPBS & ~1, Local0) // Local1 = BANK, Local2 = OFFSET Divide (Arg0, 32, Local2, Local1) @@ -61,7 +60,7 @@ Device (GPIO) // // Local3 = GPIOBASE + GPIO_OWN(BANK) - Store (Add (Local0, Multiply (Local1, 0x4)), Local3) + Store (Local0 + Local1 * 4, Local3) // GPIO_OWN(BANK) OperationRegion (IOWN, SystemIO, Local3, 4) @@ -70,14 +69,14 @@ Device (GPIO) } // GPIO_OWN[GPIO] = 0 (ACPI) - Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN) + Store (GOWN & ~(1 << Local2), GOWN) // // Set ROUTE to SCI // // Local3 = GPIOBASE + GPIO_ROUTE(BANK) - Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3) + Store (Local0 + 0x30 + Local1 * 4, Local3) // GPIO_ROUTE(BANK) OperationRegion (IROU, SystemIO, Local3, 4) @@ -86,14 +85,14 @@ Device (GPIO) } // GPIO_ROUTE[GPIO] = 0 (SCI) - Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU) + Store (GROU & ~(1 << Local2), GROU) // // Set GPnCONFIG to GPIO|INPUT|INVERT // // Local3 = GPIOBASE + GPnCONFIG0(GPIO) - Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3) + Store (Local0 + 0x100 + Arg0 * 8, Local3) // GPnCONFIG(GPIO) OperationRegion (GPNC, SystemIO, Local3, 8) @@ -110,8 +109,8 @@ Device (GPIO) ISEN, 1, // SENSE: 0=ENABLE 1=DISABLE } - Store (0x1, GMOD) // GPIO - Store (0x1, GIOS) // INPUT - Store (0x1, GINV) // INVERT + GMOD = 1 // GPIO + GIOS = 1 // INPUT + GINV = 1 // INVERT } } diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index 8410d7ab39..8f41e67b44 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -6,7 +6,7 @@ Device (LPCB) { Name (_ADR, 0x001f0000) - OperationRegion(LPC0, PCI_Config, 0x00, 0x100) + OperationRegion (LPC0, PCI_Config, 0, 0x100) Field (LPC0, AnyAcc, NoLock, Preserve) { Offset (0x02), @@ -37,8 +37,8 @@ Device (LPCB) Device (DMAC) // DMA Controller { - Name (_HID, EISAID("PNP0200")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("PNP0200")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x00, 0x00, 0x01, 0x20) IO (Decode16, 0x81, 0x81, 0x01, 0x11) @@ -50,21 +50,21 @@ Device (LPCB) Device (FWH) // Firmware Hub { - Name (_HID, EISAID("INT0800")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("INT0800")) + Name (_CRS, ResourceTemplate () { - Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) }) } Device (HPET) { - Name (_HID, EISAID("PNP0103")) + Name (_HID, EISAID ("PNP0103")) Name (_CID, 0x010CD041) - Name (BUF0, ResourceTemplate() + Name (BUF0, ResourceTemplate () { - Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) + Memory32Fixed (ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -72,7 +72,7 @@ Device (LPCB) If (HPTE) { // Note: Ancient versions of Windows don't want // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { + If (OSYS >= 2001) { Return (0xf) // Enable and show device } Else { Return (0xb) // Enable and don't show device @@ -86,16 +86,16 @@ Device (LPCB) { If (HPTE) { CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + If (HPAS == 1) { + HPT0 = CONFIG_HPET_ADDRESS + 0x1000 } - If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + If (HPAS == 2) { + HPT0 = CONFIG_HPET_ADDRESS + 0x2000 } - If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + If (HPAS == 3) { + HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } @@ -103,10 +103,10 @@ Device (LPCB) } } - Device(PIC) // 8259 Interrupt Controller + Device (PIC) // 8259 Interrupt Controller { - Name (_HID,EISAID("PNP0000")) - Name (_CRS, ResourceTemplate() + Name (_HID,EISAID ("PNP0000")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x20, 0x20, 0x01, 0x02) IO (Decode16, 0x24, 0x24, 0x01, 0x02) @@ -129,22 +129,22 @@ Device (LPCB) }) } - Device(MATH) // FPU + Device (MATH) // FPU { - Name (_HID, EISAID("PNP0C04")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("PNP0C04")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) - IRQNoFlags() { 13 } + IRQNoFlags () { 13 } }) } - Device(LDRC) // LPC device: Resource consumption + Device (LDRC) // LPC device: Resource consumption { - Name (_HID, EISAID("PNP0C02")) + Name (_HID, EISAID ("PNP0C02")) Name (_UID, 2) - Name (RBUF, ResourceTemplate() + Name (RBUF, ResourceTemplate () { IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO @@ -166,15 +166,15 @@ Device (LPCB) // LynxPoint-LP GPIO resources are defined in the // SerialIO GPIO device and LynxPoint-H GPIO resources // are defined here. - If (LNot (\ISLP ())) { + If (!\ISLP ()) { CreateByteField (^RBUF, ^GPR1._LEN, R1LN) CreateWordField (^RBUF, ^GPR1._MIN, R1MN) CreateWordField (^RBUF, ^GPR1._MAX, R1MX) // Update GPIO region length - Store (DEFAULT_GPIOBASE, R1MN) - Store (DEFAULT_GPIOBASE, R1MX) - Store (DEFAULT_GPIOSIZE, R1LN) + R1MN = DEFAULT_GPIOBASE + R1MX = DEFAULT_GPIOBASE + R1LN = DEFAULT_GPIOSIZE } Return (RBUF) } @@ -182,8 +182,8 @@ Device (LPCB) Device (RTC) // Real Time Clock { - Name (_HID, EISAID("PNP0B00")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("PNP0B00")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x70, 0x70, 1, 8) }) @@ -191,11 +191,11 @@ Device (LPCB) Device (TIMR) // Intel 8254 timer { - Name (_HID, EISAID("PNP0100")) - Name (_CRS, ResourceTemplate() { + Name (_HID, EISAID ("PNP0100")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x40, 0x40, 0x01, 0x04) IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags() {0} + IRQNoFlags () {0} }) } diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index a3c81887e7..cb5b823997 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -22,11 +22,11 @@ Scope (\) OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) Field (RCRB, DWordAcc, Lock, Preserve) { - Offset(0x3404), // High Performance Timer Configuration + Offset (0x3404), // High Performance Timer Configuration HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable - Offset(0x3418), // FD (Function Disable) + Offset (0x3418), // FD (Function Disable) , 1, // Reserved PCID, 1, // PCI bridge disable SA1D, 1, // SATA1 disable @@ -46,7 +46,7 @@ Scope (\) RP8D, 1, // Root Port 8 disable TTRD, 1, // Thermal sensor registers disable SA2D, 1, // SATA2 disable - Offset(0x3428), // FD2 (Function Disable 2) + Offset (0x3428), // FD2 (Function Disable 2) BDFD, 1, // Display BDF ME1D, 1, // ME Interface 1 disable ME2D, 1, // ME Interface 2 disable @@ -81,7 +81,7 @@ Scope (\) Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -90,7 +90,7 @@ Method (_OSC, 4) { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 164b623584..845949ce98 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -1,28 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -// Intel LynxPoint Serial IO Devices in ACPI Mode +// Intel Serial IO Devices in ACPI Mode // Serial IO Device BAR0 and BAR1 is 4KB #define SIO_BAR_LEN 0x1000 // This is defined in SSDT2 which is generated at boot based // on whether or not the device is enabled in ACPI mode. -External(\S0EN) -External(\S1EN) -External(\S2EN) -External(\S3EN) -External(\S4EN) -External(\S5EN) -External(\S6EN) -External(\S7EN) +External (\S0EN) +External (\S1EN) +External (\S2EN) +External (\S3EN) +External (\S4EN) +External (\S5EN) +External (\S6EN) +External (\S7EN) // Serial IO Resource Consumption for BAR1 Device (SIOR) { - Name (_HID, EISAID("PNP0C02")) + Name (_HID, EISAID ("PNP0C02")) Name (_UID, 4) - Name (RBUF, ResourceTemplate() + Name (RBUF, ResourceTemplate () { // Serial IO BAR1 (PCI config space) resources Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D0) // SDMA @@ -39,67 +39,67 @@ Device (SIOR) Method (_CRS, 0, NotSerialized) { // SDMA - If (LNotEqual (\S0B1, Zero)) { + If (\S0B1 != 0) { CreateDwordField (^RBUF, ^B1D0._BAS, B0AD) CreateDwordField (^RBUF, ^B1D0._LEN, B0LN) - Store (\S0B1, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S0B1 + B0LN = SIO_BAR_LEN } // I2C0 - If (LNotEqual (\S1B1, Zero)) { + If (\S1B1 != 0) { CreateDwordField (^RBUF, ^B1D1._BAS, B1AD) CreateDwordField (^RBUF, ^B1D1._LEN, B1LN) - Store (\S1B1, B1AD) - Store (SIO_BAR_LEN, B1LN) + B1AD = \S1B1 + B1LN = SIO_BAR_LEN } // I2C1 - If (LNotEqual (\S2B1, Zero)) { + If (\S2B1 != 0) { CreateDwordField (^RBUF, ^B1D2._BAS, B2AD) CreateDwordField (^RBUF, ^B1D2._LEN, B2LN) - Store (\S2B1, B2AD) - Store (SIO_BAR_LEN, B2LN) + B2AD = \S2B1 + B2LN = SIO_BAR_LEN } // SPI0 - If (LNotEqual (\S3B1, Zero)) { + If (\S3B1 != 0) { CreateDwordField (^RBUF, ^B1D3._BAS, B3AD) CreateDwordField (^RBUF, ^B1D3._LEN, B3LN) - Store (\S3B1, B3AD) - Store (SIO_BAR_LEN, B3LN) + B3AD = \S3B1 + B3LN = SIO_BAR_LEN } // SPI1 - If (LNotEqual (\S4B1, Zero)) { + If (\S4B1 != 0) { CreateDwordField (^RBUF, ^B1D4._BAS, B4AD) CreateDwordField (^RBUF, ^B1D4._LEN, B4LN) - Store (\S4B1, B4AD) - Store (SIO_BAR_LEN, B4LN) + B4AD = \S4B1 + B4LN = SIO_BAR_LEN } // UART0 - If (LNotEqual (\S5B1, Zero)) { + If (\S5B1 != 0) { CreateDwordField (^RBUF, ^B1D5._BAS, B5AD) CreateDwordField (^RBUF, ^B1D5._LEN, B5LN) - Store (\S5B1, B5AD) - Store (SIO_BAR_LEN, B5LN) + B5AD = \S5B1 + B5LN = SIO_BAR_LEN } // UART1 - If (LNotEqual (\S6B1, Zero)) { + If (\S6B1 != 0) { CreateDwordField (^RBUF, ^B1D6._BAS, B6AD) CreateDwordField (^RBUF, ^B1D6._LEN, B6LN) - Store (\S6B1, B6AD) - Store (SIO_BAR_LEN, B6LN) + B6AD = \S6B1 + B6LN = SIO_BAR_LEN } // SDIO - If (LNotEqual (\S7B1, Zero)) { + If (\S7B1 != 0) { CreateDwordField (^RBUF, ^B1D7._BAS, B7AD) CreateDwordField (^RBUF, ^B1D7._LEN, B7LN) - Store (\S7B1, B7AD) - Store (SIO_BAR_LEN, B7LN) + B7AD = \S7B1 + B7LN = SIO_BAR_LEN } Return (RBUF) @@ -122,11 +122,11 @@ Device (SDMA) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S0B0, Zero)) { + If (\S0B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S0B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S0B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -134,7 +134,7 @@ Device (SDMA) Method (_STA, 0, NotSerialized) { - If (LEqual (\S0EN, 0)) { + If (\S0EN == 0) { Return (0x0) } Else { Return (0xF) @@ -169,15 +169,15 @@ Device (I2C0) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S1B0, Zero)) { + If (\S1B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S1B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S1B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -186,7 +186,7 @@ Device (I2C0) Method (_STA, 0, NotSerialized) { - If (LEqual (\S1EN, 0)) { + If (\S1EN == 0) { Return (0x0) } Else { Return (0xF) @@ -204,21 +204,21 @@ Device (I2C0) // Put controller in D0 state Method (_PS0, 0, Serialized) { - And (^PSAT, 0xfffffffc, ^PSAT) - Store (^PSAT, Local0) // Read back after writing + ^PSAT &= 0xfffffffc + Local0 = ^PSAT // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used - And(Local0, Ones, Local0) + Local0 &= Ones } // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - Or (^PSAT, 0x00000003, ^PSAT) - Store (^PSAT, Local0) // Read back after writing + ^PSAT |= 0x00000003 + Local0 = ^PSAT // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used - And(Local0, Ones, Local0) + Local0 &= Ones } } @@ -249,15 +249,15 @@ Device (I2C1) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S2B0, Zero)) { + If (\S2B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S2B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S2B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -266,7 +266,7 @@ Device (I2C1) Method (_STA, 0, NotSerialized) { - If (LEqual (\S2EN, 0)) { + If (\S2EN == 0) { Return (0x0) } Else { Return (0xF) @@ -284,21 +284,21 @@ Device (I2C1) // Put controller in D0 state Method (_PS0, 0, Serialized) { - And (^PSAT, 0xfffffffc, ^PSAT) - Store (^PSAT, Local0) // Read back after writing + ^PSAT &= 0xfffffffc + Local0 = ^PSAT // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used - And(Local0, Ones, Local0) + Local0 &= Ones } // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - Or (^PSAT, 0x00000003, ^PSAT) - Store (^PSAT, Local0) // Read back after writing + ^PSAT |= 0x00000003 + Local0 = ^PSAT // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used - And(Local0, Ones, Local0) + Local0 &= Ones } } @@ -319,11 +319,11 @@ Device (SPI0) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S3B0, Zero)) { + If (\S3B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S3B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S3B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -331,7 +331,7 @@ Device (SPI0) Method (_STA, 0, NotSerialized) { - If (LEqual (\S3EN, 0)) { + If (\S3EN == 0) { Return (0x0) } Else { Return (0xF) @@ -363,15 +363,15 @@ Device (SPI1) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S4B0, Zero)) { + If (\S4B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S4B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S4B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -380,7 +380,7 @@ Device (SPI1) Method (_STA, 0, NotSerialized) { - If (LEqual (\S4EN, 0)) { + If (\S4EN == 0) { Return (0x0) } Else { Return (0xF) @@ -412,15 +412,15 @@ Device (UAR0) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S5B0, Zero)) { + If (\S5B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S5B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S5B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -429,7 +429,7 @@ Device (UAR0) Method (_STA, 0, NotSerialized) { - If (LEqual (\S5EN, 0)) { + If (\S5EN == 0) { Return (0x0) } Else { Return (0xF) @@ -454,11 +454,11 @@ Device (UAR1) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S6B0, Zero)) { + If (\S6B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S6B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S6B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -466,7 +466,7 @@ Device (UAR1) Method (_STA, 0, NotSerialized) { - If (LEqual (\S6EN, 0)) { + If (\S6EN == 0) { Return (0x0) } Else { Return (0xF) @@ -491,11 +491,11 @@ Device (SDIO) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S7B0, Zero)) { + If (\S7B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S7B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S7B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -503,7 +503,7 @@ Device (SDIO) Method (_STA, 0, NotSerialized) { - If (LEqual (\S7EN, 0)) { + If (\S7EN == 0) { Return (0x0) } Else { Return (0xF) diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index 4fd4a8ed37..e807398cb5 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -1,15 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Intel Cougar Point USB support */ - // EHCI Controller 0:1d.0 Device (EHCI) { - Name(_ADR, 0x001d0000) + Name (_ADR, 0x001d0000) - Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H - Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP + Name (PRWH, Package (){ 0x0d, 3 }) // LPT-H + Name (PRWL, Package (){ 0x6d, 3 }) // LPT-LP Method (_PRW, 0) { // Power Resources for Wake If (\ISLP ()) { @@ -21,19 +19,19 @@ Device (EHCI) // Leave USB ports on for to allow Wake from USB - Method(_S3D,0) // Highest D State in S3 State + Method (_S3D, 0) // Highest D State in S3 State { Return (2) } - Method(_S4D,0) // Highest D State in S4 State + Method (_S4D, 0) // Highest D State in S4 State { Return (2) } Device (HUB7) { - Name (_ADR, 0x00000000) + Name (_ADR, 0) Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 @@ -53,7 +51,7 @@ Device (XHCI) Name (PLSD, 5) // Port Link State - RxDetect Name (PLSP, 7) // Port Link State - Polling - OperationRegion (XPRT, PCI_Config, 0x00, 0x100) + OperationRegion (XPRT, PCI_Config, 0, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { Offset (0x0), @@ -81,8 +79,7 @@ Device (XHCI) // Clear status bits Method (LPCL, 0, Serialized) { - OperationRegion (XREG, SystemMemory, - ShiftLeft (^XMEM, 16), 0x600) + OperationRegion (XREG, SystemMemory, ^XMEM << 16, 0x600) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x510), // PORTSCNUSB3[0] @@ -96,32 +93,31 @@ Device (XHCI) } // Port Enabled/Disabled (Bit 1) - Name (PEDB, ShiftLeft (1, 1)) + Name (PEDB, 1 << 1) // Change Status (Bits 23:17) - Name (CHST, ShiftLeft (0x7f, 17)) + Name (CHST, 0x7f << 17) // Port 0 - And (PSC0, Not (PEDB), Local0) - Or (Local0, CHST, PSC0) + Local0 = PSC0 & ~PEDB + PSC0 = Local0 | CHST // Port 1 - And (PSC1, Not (PEDB), Local0) - Or (Local0, CHST, PSC1) + Local0 = PSC1 & ~PEDB + PSC1 = Local0 | CHST // Port 2 - And (PSC2, Not (PEDB), Local0) - Or (Local0, CHST, PSC2) + Local0 = PSC2 & ~PEDB + PSC2 = Local0 | CHST // Port 3 - And (PSC3, Not (PEDB), Local0) - Or (Local0, CHST, PSC3) + Local0 = PSC3 & ~PEDB + PSC3 = Local0 | CHST } Method (LPS0, 0, Serialized) { - OperationRegion (XREG, SystemMemory, - ShiftLeft (^XMEM, 16), 0x600) + OperationRegion (XREG, SystemMemory, ^XMEM << 16, 0x600) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x510), // PORTSCNUSB3 @@ -167,16 +163,14 @@ Device (XHCI) } // Wait for all powered ports to finish polling - Store (10, Local0) - While (LOr (LOr (LAnd (LEqual (PPR1, 1), LEqual (PLS1, PLSP)), - LAnd (LEqual (PPR2, 1), LEqual (PLS2, PLSP))), - LOr (LAnd (LEqual (PPR3, 1), LEqual (PLS3, PLSP)), - LAnd (LEqual (PPR4, 1), LEqual (PLS4, PLSP))))) + Local0 = 10 + While ((PPR1 == 1 && PLS1 == PLSP || PPR2 == 1 && PLS2 == PLSP) || + (PPR3 == 1 && PLS3 == PLSP || PPR4 == 1 && PLS4 == PLSP)) { - If (LEqual (Local0, 0)) { + If (Local0 == 0) { Break } - Decrement (Local0) + Local0-- Stall (10) } @@ -187,43 +181,37 @@ Device (XHCI) // 3) Write 1 to port status to clear // Local# indicate if port is reset - Store (0, Local1) - Store (0, Local2) - Store (0, Local3) - Store (0, Local4) + Local1 = 0 + Local2 = 0 + Local3 = 0 + Local4 = 0 - If (LAnd (LEqual (PLS1, PLSD), - LAnd (LEqual (CSC1, 0), LEqual (PPR1, 1)))) { - Store (1, WPR1) // Issue warm reset - Store (1, Local1) + If (PLS1 == PLSD && (CSC1 == 0 && PPR1 == 1)) { + WPR1 = 1 // Issue warm reset + Local1 = 1 } - If (LAnd (LEqual (PLS2, PLSD), - LAnd (LEqual (CSC2, 0), LEqual (PPR2, 1)))) { - Store (1, WPR2) // Issue warm reset - Store (1, Local2) + If (PLS2 == PLSD && (CSC2 == 0 && PPR2 == 1)) { + WPR2 = 1 // Issue warm reset + Local2 = 1 } - If (LAnd (LEqual (PLS3, PLSD), - LAnd (LEqual (CSC3, 0), LEqual (PPR3, 1)))) { - Store (1, WPR3) // Issue warm reset - Store (1, Local3) + If (PLS3 == PLSD && (CSC3 == 0 && PPR3 == 1)) { + WPR3 = 1 // Issue warm reset + Local3 = 1 } - If (LAnd (LEqual (PLS4, PLSD), - LAnd (LEqual (CSC4, 0), LEqual (PPR4, 1)))) { - Store (1, WPR4) // Issue warm reset - Store (1, Local4) + If (PLS4 == PLSD && (CSC4 == 0 && PPR4 == 1)) { + WPR4 = 1 // Issue warm reset + Local4 = 1 } // Poll for warm reset complete on all ports that were reset - Store (10, Local0) - While (LOr (LOr (LAnd (LEqual (Local1, 1), LEqual (WRC1, 0)), - LAnd (LEqual (Local2, 1), LEqual (WRC2, 0))), - LOr (LAnd (LEqual (Local3, 1), LEqual (WRC3, 0)), - LAnd (LEqual (Local4, 1), LEqual (WRC4, 0))))) + Local0 = 10 + While ((Local1 == 1 && WRC1 == 0 || Local2 == 1 && WRC2 == 0) || + (Local3 == 1 && WRC3 == 0 || Local4 == 1 && WRC4 == 0)) { - If (LEqual (Local0, 0)) { + If (Local0 == 0) { Break } - Decrement (Local0) + Local0-- Stall (10) } @@ -238,15 +226,14 @@ Device (XHCI) Method (_PS0, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { + If (^DVID == 0xFFFF) { Return () } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + If (^XMEM == 0xFFFF || ^XMEM == 0) { Return () } - OperationRegion (XREG, SystemMemory, - Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200) + OperationRegion (XREG, SystemMemory, (^XMEM << 16) + 0x8000, 0x200) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x0e0), // AUX Reset Control 1 @@ -263,30 +250,30 @@ Device (XHCI) } // If device is in D3, set back to D0 - Store (^D0D3, Local0) - if (LEqual (Local0, 3)) { - Store (0, ^D0D3) + Local0 = ^D0D3 + if (Local0 == 3) { + ^D0D3 = 0 } If (\ISLP ()) { // Clear PCI 0xB0[14:13] - Store (0, ^MB13) - Store (0, ^MB14) + ^MB13 = 0 + ^MB14 = 0 // Clear MMIO 0x816C[14,2] - Store (0, CLK0) - Store (0, CLK1) + CLK0 = 0 + CLK1 = 0 } // Set MMIO 0x8154[31] - Store (1, CLK2) + CLK2 = 1 If (\ISLP ()) { // Handle per-port reset if needed LPS0 () // Set MMIO 0x80e0[15] - Store (1, AX15) + AX15 = 1 } Return () @@ -294,15 +281,14 @@ Device (XHCI) Method (_PS3, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { + If (^DVID == 0xFFFF) { Return () } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + If (^XMEM == 0xFFFF || ^XMEM == 0) { Return () } - OperationRegion (XREG, SystemMemory, - Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200) + OperationRegion (XREG, SystemMemory, (^XMEM << 16) + 0x8000, 0x200) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x0e0), // AUX Reset Control 1 @@ -318,41 +304,41 @@ Device (XHCI) CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable } - Store (1, ^PMES) // Clear PME Status - Store (1, ^PMEE) // Enable PME + ^PMES = 1 // Clear PME Status + ^PMEE = 1 // Enable PME // If device is in D3, set back to D0 - Store (^D0D3, Local0) - if (LEqual (Local0, 3)) { - Store (0, ^D0D3) + Local0 = ^D0D3 + if (Local0 == 3) { + ^D0D3 = 0 } If (\ISLP ()) { // Set PCI 0xB0[14:13] - Store (1, ^MB13) - Store (1, ^MB14) + ^MB13 = 1 + ^MB14 = 1 // Set MMIO 0x816C[14,2] - Store (1, CLK0) - Store (1, CLK1) + CLK0 = 1 + CLK1 = 1 } // Clear MMIO 0x8154[31] - Store (0, CLK2) + CLK2 = 0 If (\ISLP ()) { // Clear MMIO 0x80e0[15] - Store (0, AX15) + AX15 = 0 } // Put device in D3 - Store (3, ^D0D3) + ^D0D3 = 3 Return () } - Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H - Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP + Name (PRWH, Package (){ 0x0d, 3 }) // LPT-H + Name (PRWL, Package (){ 0x6d, 3 }) // LPT-LP Method (_PRW, 0) { // Power Resources for Wake If (\ISLP ()) { @@ -364,33 +350,33 @@ Device (XHCI) // Leave USB ports on for to allow Wake from USB - Method(_S3D,0) // Highest D State in S3 State + Method (_S3D, 0) // Highest D State in S3 State { Return (3) } - Method(_S4D,0) // Highest D State in S4 State + Method (_S4D, 0) // Highest D State in S4 State { Return (3) } Device (HUB7) { - Name (_ADR, 0x00000000) + Name (_ADR, 0) // GPLD: Generate Port Location Data (PLD) Method (GPLD, 1, Serialized) { - Name (PCKG, Package (0x01) { + Name (PCKG, Package () { Buffer (0x10) {} }) - // REV: Revision 0x02 for ACPI 5.0 - CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) - Store (0x02, REV) + // REV: Revision 2 for ACPI 5.0 + CreateField (DerefOf (PCKG [0]), 0, 7, REV) + REV = 2 // VISI: Port visibility to user per port - CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) - Store (Arg0, VISI) + CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI) + VISI = Arg0 Return (PCKG) } From 56d37fbe6f65d6c92a082d30baf13e79331dcebd Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 21:11:58 +0100 Subject: [PATCH 222/262] soc/intel/broadwell/pch/acpi: Clean up cosmetics MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use ASL 2.0 syntax where possible and uniformize code style to match the IASL disassembly. Some `Store` in gpio.asl change the binary if touched. Tested with BUILD_TIMELESS=1, Google Buddy does not change. Change-Id: Ic13c081fd7ee2212d851cc14263c1e2fd8970072 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46778 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/pch/acpi/adsp.asl | 8 +- src/soc/intel/broadwell/pch/acpi/ehci.asl | 9 +- .../intel/broadwell/pch/acpi/globalnvs.asl | 14 +- src/soc/intel/broadwell/pch/acpi/gpio.asl | 27 ++- src/soc/intel/broadwell/pch/acpi/lpc.asl | 62 +++--- src/soc/intel/broadwell/pch/acpi/pch.asl | 8 +- src/soc/intel/broadwell/pch/acpi/serialio.asl | 144 +++++++------- src/soc/intel/broadwell/pch/acpi/xhci.asl | 176 ++++++++---------- 8 files changed, 217 insertions(+), 231 deletions(-) diff --git a/src/soc/intel/broadwell/pch/acpi/adsp.asl b/src/soc/intel/broadwell/pch/acpi/adsp.asl index 435db4d404..51dd38cd3f 100644 --- a/src/soc/intel/broadwell/pch/acpi/adsp.asl +++ b/src/soc/intel/broadwell/pch/acpi/adsp.asl @@ -25,11 +25,11 @@ Device (ADSP) Method (_CRS, 0, NotSerialized) { // Update BAR address and length if set in NVS - If (LNotEqual (\S8B0, Zero)) { + If (\S8B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B8A0) CreateDwordField (^RBUF, ^BAR1._BAS, B8A1) - Store (\S8B0, B8A0) - Store (\S8B1, B8A1) + B8A0 = \S8B0 + B8A1 = \S8B1 } Return (RBUF) @@ -37,7 +37,7 @@ Device (ADSP) Method (_STA, 0, NotSerialized) { - If (LEqual (\S8EN, 0)) { + If (\S8EN == 0) { Return (0x0) } Else { Return (0xF) diff --git a/src/soc/intel/broadwell/pch/acpi/ehci.asl b/src/soc/intel/broadwell/pch/acpi/ehci.asl index c02bc1a179..632b19fc10 100644 --- a/src/soc/intel/broadwell/pch/acpi/ehci.asl +++ b/src/soc/intel/broadwell/pch/acpi/ehci.asl @@ -4,26 +4,25 @@ Device (EHCI) { - Name(_ADR, 0x001d0000) + Name (_ADR, 0x001d0000) Name (_PRW, Package(){ 0x6d, 3 }) // Leave USB ports on for to allow Wake from USB - Method(_S3D,0) // Highest D State in S3 State + Method (_S3D, 0) // Highest D State in S3 State { Return (2) } - Method(_S4D,0) // Highest D State in S4 State + Method (_S4D, 0) // Highest D State in S4 State { Return (2) } Device (HUB7) { - Name (_ADR, 0x00000000) + Name (_ADR, 0) - // How many are there? Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 Device (PRT3) { Name (_ADR, 3) } // USB Port 2 diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl index 15f69dd09f..06ca564548 100644 --- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl @@ -11,7 +11,7 @@ Name (\PICM, 0) // IOAPIC/8259 * we have to fix it up in coreboot's ACPI creation phase. */ -External(NVSA) +External (NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { @@ -87,35 +87,35 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* Set flag to enable USB charging in S3 */ Method (S3UE) { - Store (One, \S3U0) + \S3U0 = 1 } /* Set flag to disable USB charging in S3 */ Method (S3UD) { - Store (Zero, \S3U0) + \S3U0 = 0 } /* Set flag to enable USB charging in S5 */ Method (S5UE) { - Store (One, \S5U0) + \S5U0 = 1 } /* Set flag to disable USB charging in S5 */ Method (S5UD) { - Store (Zero, \S5U0) + \S5U0 = 0 } /* Set flag to enable 3G module in S3 */ Method (S3GE) { - Store (One, \S33G) + \S33G = 1 } /* Set flag to disable 3G module in S3 */ Method (S3GD) { - Store (Zero, \S33G) + \S33G = 0 } diff --git a/src/soc/intel/broadwell/pch/acpi/gpio.asl b/src/soc/intel/broadwell/pch/acpi/gpio.asl index cfe0aed0b2..6b20f2784d 100644 --- a/src/soc/intel/broadwell/pch/acpi/gpio.asl +++ b/src/soc/intel/broadwell/pch/acpi/gpio.asl @@ -15,7 +15,7 @@ Device (GPIO) } Name (_UID, 1) - Name (RBUF, ResourceTemplate() + Name (RBUF, ResourceTemplate () { DWordIo (ResourceProducer, MinFixed, // IsMinFixed @@ -41,10 +41,9 @@ Device (GPIO) CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) CreateDwordField (^RBUF, ^BAR0._LEN, BLEN) - Store (GPIO_BASE_SIZE, BLEN) - Store (GPIO_BASE_ADDRESS, BMIN) - Store (Subtract (Add (GPIO_BASE_ADDRESS, - GPIO_BASE_SIZE), 1), BMAX) + BLEN = GPIO_BASE_SIZE + BMIN = GPIO_BASE_ADDRESS + BMAX = GPIO_BASE_ADDRESS + GPIO_BASE_SIZE - 1 Return (RBUF) } @@ -59,7 +58,7 @@ Device (GPIO) Method (GWAK, 1, Serialized) { // Local0 = GPIO Base Address - Store (And (GPBS, Not(0x1)), Local0) + Store (GPBS & ~1, Local0) // Local1 = BANK, Local2 = OFFSET Divide (Arg0, 32, Local2, Local1) @@ -69,7 +68,7 @@ Device (GPIO) // // Local3 = GPIOBASE + GPIO_OWN(BANK) - Store (Add (Local0, Multiply (Local1, 0x4)), Local3) + Store (Local0 + Local1 * 4, Local3) // GPIO_OWN(BANK) OperationRegion (IOWN, SystemIO, Local3, 4) @@ -78,14 +77,14 @@ Device (GPIO) } // GPIO_OWN[GPIO] = 0 (ACPI) - Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN) + Store (GOWN & ~(1 << Local2), GOWN) // // Set ROUTE to SCI // // Local3 = GPIOBASE + GPIO_ROUTE(BANK) - Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3) + Store (Local0 + 0x30 + Local1 * 4, Local3) // GPIO_ROUTE(BANK) OperationRegion (IROU, SystemIO, Local3, 4) @@ -94,14 +93,14 @@ Device (GPIO) } // GPIO_ROUTE[GPIO] = 0 (SCI) - Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU) + Store (GROU & ~(1 << Local2), GROU) // // Set GPnCONFIG to GPIO|INPUT|INVERT // // Local3 = GPIOBASE + GPnCONFIG0(GPIO) - Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3) + Store (Local0 + 0x100 + Arg0 * 8, Local3) // GPnCONFIG(GPIO) OperationRegion (GPNC, SystemIO, Local3, 8) @@ -118,8 +117,8 @@ Device (GPIO) ISEN, 1, // SENSE: 0=ENABLE 1=DISABLE } - Store (0x1, GMOD) // GPIO - Store (0x1, GIOS) // INPUT - Store (0x1, GINV) // INVERT + GMOD = 1 // GPIO + GIOS = 1 // INPUT + GINV = 1 // INVERT } } diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl index 0af85e62cc..ae54ce3c23 100644 --- a/src/soc/intel/broadwell/pch/acpi/lpc.asl +++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl @@ -6,7 +6,7 @@ Device (LPCB) { Name (_ADR, 0x001f0000) - OperationRegion(LPC0, PCI_Config, 0x00, 0x100) + OperationRegion (LPC0, PCI_Config, 0, 0x100) Field (LPC0, AnyAcc, NoLock, Preserve) { Offset (0x02), @@ -37,8 +37,8 @@ Device (LPCB) Device (DMAC) // DMA Controller { - Name (_HID, EISAID("PNP0200")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("PNP0200")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x00, 0x00, 0x01, 0x20) IO (Decode16, 0x81, 0x81, 0x01, 0x11) @@ -50,21 +50,21 @@ Device (LPCB) Device (FWH) // Firmware Hub { - Name (_HID, EISAID("INT0800")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("INT0800")) + Name (_CRS, ResourceTemplate () { - Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) }) } Device (HPET) { - Name (_HID, EISAID("PNP0103")) + Name (_HID, EISAID ("PNP0103")) Name (_CID, 0x010CD041) - Name (BUF0, ResourceTemplate() + Name (BUF0, ResourceTemplate () { - Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) + Memory32Fixed (ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -72,7 +72,7 @@ Device (LPCB) If (HPTE) { // Note: Ancient versions of Windows don't want // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { + If (OSYS >= 2001) { Return (0xf) // Enable and show device } Else { Return (0xb) // Enable and don't show device @@ -86,16 +86,16 @@ Device (LPCB) { If (HPTE) { CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + If (HPAS == 1) { + HPT0 = CONFIG_HPET_ADDRESS + 0x1000 } - If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + If (HPAS == 2) { + HPT0 = CONFIG_HPET_ADDRESS + 0x2000 } - If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + If (HPAS == 3) { + HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } @@ -103,10 +103,10 @@ Device (LPCB) } } - Device(PIC) // 8259 Interrupt Controller + Device (PIC) // 8259 Interrupt Controller { - Name (_HID,EISAID("PNP0000")) - Name (_CRS, ResourceTemplate() + Name (_HID,EISAID ("PNP0000")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x20, 0x20, 0x01, 0x02) IO (Decode16, 0x24, 0x24, 0x01, 0x02) @@ -129,22 +129,22 @@ Device (LPCB) }) } - Device(MATH) // FPU + Device (MATH) // FPU { - Name (_HID, EISAID("PNP0C04")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("PNP0C04")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) - IRQNoFlags() { 13 } + IRQNoFlags () { 13 } }) } - Device(LDRC) // LPC device: Resource consumption + Device (LDRC) // LPC device: Resource consumption { - Name (_HID, EISAID("PNP0C02")) + Name (_HID, EISAID ("PNP0C02")) Name (_UID, 2) - Name (RBUF, ResourceTemplate() + Name (RBUF, ResourceTemplate () { IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO @@ -166,8 +166,8 @@ Device (LPCB) Device (RTC) // Real Time Clock { - Name (_HID, EISAID("PNP0B00")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("PNP0B00")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x70, 0x70, 1, 8) }) @@ -175,11 +175,11 @@ Device (LPCB) Device (TIMR) // Intel 8254 timer { - Name (_HID, EISAID("PNP0100")) - Name (_CRS, ResourceTemplate() { + Name (_HID, EISAID ("PNP0100")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x40, 0x40, 0x01, 0x04) IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags() {0} + IRQNoFlags () {0} }) } diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl index 7b57859672..d68fa60bbf 100644 --- a/src/soc/intel/broadwell/pch/acpi/pch.asl +++ b/src/soc/intel/broadwell/pch/acpi/pch.asl @@ -29,8 +29,8 @@ Scope (\) */ Method (ISWP) { - And (\_SB.PCI0.LPCB.PDID, 0xfff0, Local0) - If (LEqual (Local0, 0x9cc0)) { + Local0 = \_SB.PCI0.LPCB.PDID & 0xfff0 + If (Local0 == 0x9cc0) { Return (1) } Else { Return (0) @@ -68,7 +68,7 @@ Scope (\) Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -77,7 +77,7 @@ Method (_OSC, 4) { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index 218ddc3b40..91fa75831c 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -11,21 +11,21 @@ Method (LPD0, 2, Serialized) { // PCI mode devices will be handled by OS PCI bus driver - If (LEqual (Arg1, 0)) { + If (Arg1 == 0) { Return } - OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4) + OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) Field (SPRT, DWordAcc, NoLock, Preserve) { SPCS, 32 } - And (SPCS, 0xFFFFFFFC, SPCS) - Store (SPCS, Local0) // Read back after writing + SPCS &= 0xFFFFFFFC + Local0 = SPCS // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used - And(Local0, Ones, Local0) + Local0 &= Ones } // Put SerialIO device in D3 state @@ -34,30 +34,30 @@ Method (LPD0, 2, Serialized) Method (LPD3, 2, Serialized) { // PCI mode devices will be handled by OS PCI bus driver - If (LEqual (Arg1, 0)) { + If (Arg1 == 0) { Return } - OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4) + OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) Field (SPRT, DWordAcc, NoLock, Preserve) { SPCS, 32 } - Or (SPCS, 0x3, SPCS) - Store (SPCS, Local0) // Read back after writing + SPCS |= 0x3 + Local0 = SPCS // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used - And(Local0, Ones, Local0) + Local0 &= Ones } // Serial IO Resource Consumption for BAR1 Device (SIOR) { - Name (_HID, EISAID("PNP0C02")) + Name (_HID, EISAID ("PNP0C02")) Name (_UID, 4) - Name (RBUF, ResourceTemplate() + Name (RBUF, ResourceTemplate () { // Serial IO BAR1 (PCI config space) resources Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D0) // SDMA @@ -74,67 +74,67 @@ Device (SIOR) Method (_CRS, 0, NotSerialized) { // SDMA - If (LNotEqual (\S0B1, Zero)) { + If (\S0B1 != 0) { CreateDwordField (^RBUF, ^B1D0._BAS, B0AD) CreateDwordField (^RBUF, ^B1D0._LEN, B0LN) - Store (\S0B1, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S0B1 + B0LN = SIO_BAR_LEN } // I2C0 - If (LNotEqual (\S1B1, Zero)) { + If (\S1B1 != 0) { CreateDwordField (^RBUF, ^B1D1._BAS, B1AD) CreateDwordField (^RBUF, ^B1D1._LEN, B1LN) - Store (\S1B1, B1AD) - Store (SIO_BAR_LEN, B1LN) + B1AD = \S1B1 + B1LN = SIO_BAR_LEN } // I2C1 - If (LNotEqual (\S2B1, Zero)) { + If (\S2B1 != 0) { CreateDwordField (^RBUF, ^B1D2._BAS, B2AD) CreateDwordField (^RBUF, ^B1D2._LEN, B2LN) - Store (\S2B1, B2AD) - Store (SIO_BAR_LEN, B2LN) + B2AD = \S2B1 + B2LN = SIO_BAR_LEN } // SPI0 - If (LNotEqual (\S3B1, Zero)) { + If (\S3B1 != 0) { CreateDwordField (^RBUF, ^B1D3._BAS, B3AD) CreateDwordField (^RBUF, ^B1D3._LEN, B3LN) - Store (\S3B1, B3AD) - Store (SIO_BAR_LEN, B3LN) + B3AD = \S3B1 + B3LN = SIO_BAR_LEN } // SPI1 - If (LNotEqual (\S4B1, Zero)) { + If (\S4B1 != 0) { CreateDwordField (^RBUF, ^B1D4._BAS, B4AD) CreateDwordField (^RBUF, ^B1D4._LEN, B4LN) - Store (\S4B1, B4AD) - Store (SIO_BAR_LEN, B4LN) + B4AD = \S4B1 + B4LN = SIO_BAR_LEN } // UART0 - If (LNotEqual (\S5B1, Zero)) { + If (\S5B1 != 0) { CreateDwordField (^RBUF, ^B1D5._BAS, B5AD) CreateDwordField (^RBUF, ^B1D5._LEN, B5LN) - Store (\S5B1, B5AD) - Store (SIO_BAR_LEN, B5LN) + B5AD = \S5B1 + B5LN = SIO_BAR_LEN } // UART1 - If (LNotEqual (\S6B1, Zero)) { + If (\S6B1 != 0) { CreateDwordField (^RBUF, ^B1D6._BAS, B6AD) CreateDwordField (^RBUF, ^B1D6._LEN, B6LN) - Store (\S6B1, B6AD) - Store (SIO_BAR_LEN, B6LN) + B6AD = \S6B1 + B6LN = SIO_BAR_LEN } // SDIO - If (LNotEqual (\S7B1, Zero)) { + If (\S7B1 != 0) { CreateDwordField (^RBUF, ^B1D7._BAS, B7AD) CreateDwordField (^RBUF, ^B1D7._LEN, B7LN) - Store (\S7B1, B7AD) - Store (SIO_BAR_LEN, B7LN) + B7AD = \S7B1 + B7LN = SIO_BAR_LEN } Return (RBUF) @@ -158,11 +158,11 @@ Device (SDMA) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S0B0, Zero)) { + If (\S0B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S0B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S0B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -170,7 +170,7 @@ Device (SDMA) Method (_STA, 0, NotSerialized) { - If (LEqual (\S0EN, 0)) { + If (\S0EN == 0) { Return (0x0) } Else { Return (0xF) @@ -214,15 +214,15 @@ Device (I2C0) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S1B0, Zero)) { + If (\S1B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S1B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S1B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -231,7 +231,7 @@ Device (I2C0) Method (_STA, 0, NotSerialized) { - If (LEqual (\S1EN, 0)) { + If (\S1EN == 0) { Return (0x0) } Else { Return (0xF) @@ -285,15 +285,15 @@ Device (I2C1) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S2B0, Zero)) { + If (\S2B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S2B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S2B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -302,7 +302,7 @@ Device (I2C1) Method (_STA, 0, NotSerialized) { - If (LEqual (\S2EN, 0)) { + If (\S2EN == 0) { Return (0x0) } Else { Return (0xF) @@ -346,11 +346,11 @@ Device (SPI0) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S3B0, Zero)) { + If (\S3B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S3B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S3B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -358,7 +358,7 @@ Device (SPI0) Method (_STA, 0, NotSerialized) { - If (LEqual (\S3EN, 0)) { + If (\S3EN == 0) { Return (0x0) } Else { Return (0xF) @@ -409,15 +409,15 @@ Device (SPI1) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S4B0, Zero)) { + If (\S4B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S4B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S4B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -426,7 +426,7 @@ Device (SPI1) Method (_STA, 0, NotSerialized) { - If (LEqual (\S4EN, 0)) { + If (\S4EN == 0) { Return (0x0) } Else { Return (0xF) @@ -477,15 +477,15 @@ Device (UAR0) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S5B0, Zero)) { + If (\S5B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S5B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S5B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -494,7 +494,7 @@ Device (UAR0) Method (_STA, 0, NotSerialized) { - If (LEqual (\S5EN, 0)) { + If (\S5EN == 0) { Return (0x0) } Else { Return (0xF) @@ -538,11 +538,11 @@ Device (UAR1) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S6B0, Zero)) { + If (\S6B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S6B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S6B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -550,7 +550,7 @@ Device (UAR1) Method (_STA, 0, NotSerialized) { - If (LEqual (\S6EN, 0)) { + If (\S6EN == 0) { Return (0x0) } Else { Return (0xF) @@ -595,11 +595,11 @@ Device (SDIO) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S7B0, Zero)) { + If (\S7B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S7B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S7B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -607,7 +607,7 @@ Device (SDIO) Method (_STA, 0, NotSerialized) { - If (LEqual (\S7EN, 0)) { + If (\S7EN == 0) { Return (0x0) } Else { Return (0xF) diff --git a/src/soc/intel/broadwell/pch/acpi/xhci.asl b/src/soc/intel/broadwell/pch/acpi/xhci.asl index 22e3cbceaf..4bdd3103f1 100644 --- a/src/soc/intel/broadwell/pch/acpi/xhci.asl +++ b/src/soc/intel/broadwell/pch/acpi/xhci.asl @@ -9,7 +9,7 @@ Device (XHCI) Name (PLSD, 5) // Port Link State - RxDetect Name (PLSP, 7) // Port Link State - Polling - OperationRegion (XPRT, PCI_Config, 0x00, 0x100) + OperationRegion (XPRT, PCI_Config, 0, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { Offset (0x0), @@ -45,8 +45,7 @@ Device (XHCI) // Clear status bits Method (LPCL, 0, Serialized) { - OperationRegion (XREG, SystemMemory, - ShiftLeft (^XMEM, 16), 0x600) + OperationRegion (XREG, SystemMemory, ^XMEM << 16, 0x600) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x510), // PORTSCNUSB3[0] @@ -60,32 +59,31 @@ Device (XHCI) } // Port Enabled/Disabled (Bit 1) - Name (PEDB, ShiftLeft (1, 1)) + Name (PEDB, 1 << 1) // Change Status (Bits 23:17) - Name (CHST, ShiftLeft (0x7f, 17)) + Name (CHST, 0x7f << 17) // Port 0 - And (PSC0, Not (PEDB), Local0) - Or (Local0, CHST, PSC0) + Local0 = PSC0 & ~PEDB + PSC0 = Local0 | CHST // Port 1 - And (PSC1, Not (PEDB), Local0) - Or (Local0, CHST, PSC1) + Local0 = PSC1 & ~PEDB + PSC1 = Local0 | CHST // Port 2 - And (PSC2, Not (PEDB), Local0) - Or (Local0, CHST, PSC2) + Local0 = PSC2 & ~PEDB + PSC2 = Local0 | CHST // Port 3 - And (PSC3, Not (PEDB), Local0) - Or (Local0, CHST, PSC3) + Local0 = PSC3 & ~PEDB + PSC3 = Local0 | CHST } Method (LPS0, 0, Serialized) { - OperationRegion (XREG, SystemMemory, - ShiftLeft (^XMEM, 16), 0x600) + OperationRegion (XREG, SystemMemory, ^XMEM << 16, 0x600) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x510), // PORTSCNUSB3 @@ -131,16 +129,14 @@ Device (XHCI) } // Wait for all powered ports to finish polling - Store (10, Local0) - While (LOr (LOr (LAnd (LEqual (PPR1, 1), LEqual (PLS1, PLSP)), - LAnd (LEqual (PPR2, 1), LEqual (PLS2, PLSP))), - LOr (LAnd (LEqual (PPR3, 1), LEqual (PLS3, PLSP)), - LAnd (LEqual (PPR4, 1), LEqual (PLS4, PLSP))))) + Local0 = 10 + While ((PPR1 == 1 && PLS1 == PLSP || PPR2 == 1 && PLS2 == PLSP) || + (PPR3 == 1 && PLS3 == PLSP || PPR4 == 1 && PLS4 == PLSP)) { - If (LEqual (Local0, 0)) { + If (Local0 == 0) { Break } - Decrement (Local0) + Local0-- Stall (10) } @@ -151,43 +147,37 @@ Device (XHCI) // 3) Write 1 to port status to clear // Local# indicate if port is reset - Store (0, Local1) - Store (0, Local2) - Store (0, Local3) - Store (0, Local4) + Local1 = 0 + Local2 = 0 + Local3 = 0 + Local4 = 0 - If (LAnd (LEqual (PLS1, PLSD), - LAnd (LEqual (CSC1, 0), LEqual (PPR1, 1)))) { - Store (1, WPR1) // Issue warm reset - Store (1, Local1) + If (PLS1 == PLSD && (CSC1 == 0 && PPR1 == 1)) { + WPR1 = 1 // Issue warm reset + Local1 = 1 } - If (LAnd (LEqual (PLS2, PLSD), - LAnd (LEqual (CSC2, 0), LEqual (PPR2, 1)))) { - Store (1, WPR2) // Issue warm reset - Store (1, Local2) + If (PLS2 == PLSD && (CSC2 == 0 && PPR2 == 1)) { + WPR2 = 1 // Issue warm reset + Local2 = 1 } - If (LAnd (LEqual (PLS3, PLSD), - LAnd (LEqual (CSC3, 0), LEqual (PPR3, 1)))) { - Store (1, WPR3) // Issue warm reset - Store (1, Local3) + If (PLS3 == PLSD && (CSC3 == 0 && PPR3 == 1)) { + WPR3 = 1 // Issue warm reset + Local3 = 1 } - If (LAnd (LEqual (PLS4, PLSD), - LAnd (LEqual (CSC4, 0), LEqual (PPR4, 1)))) { - Store (1, WPR4) // Issue warm reset - Store (1, Local4) + If (PLS4 == PLSD && (CSC4 == 0 && PPR4 == 1)) { + WPR4 = 1 // Issue warm reset + Local4 = 1 } // Poll for warm reset complete on all ports that were reset - Store (10, Local0) - While (LOr (LOr (LAnd (LEqual (Local1, 1), LEqual (WRC1, 0)), - LAnd (LEqual (Local2, 1), LEqual (WRC2, 0))), - LOr (LAnd (LEqual (Local3, 1), LEqual (WRC3, 0)), - LAnd (LEqual (Local4, 1), LEqual (WRC4, 0))))) + Local0 = 10 + While ((Local1 == 1 && WRC1 == 0 || Local2 == 1 && WRC2 == 0) || + (Local3 == 1 && WRC3 == 0 || Local4 == 1 && WRC4 == 0)) { - If (LEqual (Local0, 0)) { + If (Local0 == 0) { Break } - Decrement (Local0) + Local0-- Stall (10) } @@ -202,15 +192,14 @@ Device (XHCI) Method (_PS0, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { + If (^DVID == 0xFFFF) { Return () } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + If (^XMEM == 0xFFFF || ^XMEM == 0) { Return () } - OperationRegion (XREG, SystemMemory, - Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200) + OperationRegion (XREG, SystemMemory, (^XMEM << 16) + 0x8000, 0x200) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x0e0), // AUX Reset Control 1 @@ -227,34 +216,34 @@ Device (XHCI) } // If device is in D3, set back to D0 - Store (^D0D3, Local0) - if (LEqual (Local0, 3)) { - Store (0, ^D0D3) + Local0 = ^D0D3 + if (Local0 == 3) { + ^D0D3 = 0 } - if (LNot (\ISWP())) { + If (!\ISWP()) { // Clear PCI 0xB0[14:13] - Store (0, ^MB13) - Store (0, ^MB14) + ^MB13 = 0 + ^MB14 = 0 // Clear MMIO 0x816C[14,2] - Store (0, CLK0) - Store (0, CLK1) + CLK0 = 0 + CLK1 = 0 // Set MMIO 0x8154[31] - Store (1, CLK2) + CLK2 = 1 // Handle per-port reset if needed LPS0 () // Set MMIO 0x80e0[15] - Store (1, AX15) + AX15 = 1 // Clear PCI CFG offset 0x40[11] - Store (0, ^SWAI) + ^SWAI = 0 // Clear PCI CFG offset 0x44[13:12] - Store (0, ^SAIP) + ^SAIP = 0 } Return () @@ -262,15 +251,14 @@ Device (XHCI) Method (_PS3, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { + If (^DVID == 0xFFFF) { Return () } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + If (^XMEM == 0xFFFF || ^XMEM == 0) { Return () } - OperationRegion (XREG, SystemMemory, - Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200) + OperationRegion (XREG, SystemMemory, (^XMEM << 16) + 0x8000, 0x200) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x0e0), // AUX Reset Control 1 @@ -286,74 +274,74 @@ Device (XHCI) CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable } - Store (1, ^PMES) // Clear PME Status - Store (1, ^PMEE) // Enable PME + ^PMES = 1 // Clear PME Status + ^PMEE = 1 // Enable PME // If device is in D3, set back to D0 - Store (^D0D3, Local0) - if (LEqual (Local0, 3)) { - Store (0, ^D0D3) + Local0 = ^D0D3 + if (Local0 == 3) { + ^D0D3 = 0 } - if (LNot (\ISWP())) { + If (!\ISWP()) { // Set PCI 0xB0[14:13] - Store (1, ^MB13) - Store (1, ^MB14) + ^MB13 = 1 + ^MB14 = 1 // Set MMIO 0x816C[14,2] - Store (1, CLK0) - Store (1, CLK1) + CLK0 = 1 + CLK1 = 1 // Clear MMIO 0x8154[31] - Store (0, CLK2) + CLK2 = 0 // Clear MMIO 0x80e0[15] - Store (0, AX15) + AX15 = 0 // Set PCI CFG offset 0x40[11] - Store (1, ^SWAI) + ^SWAI = 1 // Set PCI CFG offset 0x44[13:12] - Store (1, ^SAIP) + ^SAIP = 1 } // Put device in D3 - Store (3, ^D0D3) + ^D0D3 = 3 Return () } - Name (_PRW, Package(){ 0x6d, 3 }) + Name (_PRW, Package (){ 0x6d, 3 }) // Leave USB ports on for to allow Wake from USB - Method(_S3D,0) // Highest D State in S3 State + Method (_S3D, 0) // Highest D State in S3 State { Return (3) } - Method(_S4D,0) // Highest D State in S4 State + Method (_S4D, 0) // Highest D State in S4 State { Return (3) } Device (HUB7) { - Name (_ADR, 0x00000000) + Name (_ADR, 0) // GPLD: Generate Port Location Data (PLD) Method (GPLD, 1, Serialized) { - Name (PCKG, Package (0x01) { + Name (PCKG, Package () { Buffer (0x10) {} }) - // REV: Revision 0x02 for ACPI 5.0 - CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) - Store (0x02, REV) + // REV: Revision 2 for ACPI 5.0 + CreateField (DerefOf (PCKG [0]), 0, 7, REV) + REV = 2 // VISI: Port visibility to user per port - CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) - Store (Arg0, VISI) + CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI) + VISI = Arg0 Return (PCKG) } From 98ea6a3f94adc9d33c52283683b423e2ced8af61 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 21:13:36 +0100 Subject: [PATCH 223/262] soc/intel/broadwell/pch/acpi/hda.asl: Rename to `audio.asl` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is merely to ease diffing Lynx Point and Broadwell ASL code. Tested with BUILD_TIMELESS=1, Google Buddy does not change. Change-Id: I9f6ab98388d2a2915a48377ebe9e724cfee4b95f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46779 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/pch/acpi/{hda.asl => audio.asl} | 0 src/soc/intel/broadwell/pch/acpi/pch.asl | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename src/soc/intel/broadwell/pch/acpi/{hda.asl => audio.asl} (100%) diff --git a/src/soc/intel/broadwell/pch/acpi/hda.asl b/src/soc/intel/broadwell/pch/acpi/audio.asl similarity index 100% rename from src/soc/intel/broadwell/pch/acpi/hda.asl rename to src/soc/intel/broadwell/pch/acpi/audio.asl diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl index d68fa60bbf..b7d6838f51 100644 --- a/src/soc/intel/broadwell/pch/acpi/pch.asl +++ b/src/soc/intel/broadwell/pch/acpi/pch.asl @@ -39,7 +39,7 @@ Scope (\) } // High Definition Audio (Azalia) 0:1b.0 -#include "hda.asl" +#include "audio.asl" // ADSP/SST 0:13.0 #include "adsp.asl" From 59ea8ef9e1e97e85211d284f35f29fa913d86270 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 21:28:09 +0100 Subject: [PATCH 224/262] sb/intel/lynxpoint/acpi: Statically define _PRW values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order for ACPI deduplication to be reproducible, the `ISLP` method needs to disappear. Replace the _PRW methods with a name and a macro. Change-Id: Id0a46965b66f1a70e8f8868af01a535207c9f5c7 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46780 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../intel/lynxpoint/acpi/audio.asl | 12 +--------- src/southbridge/intel/lynxpoint/acpi/pch.asl | 6 +++++ src/southbridge/intel/lynxpoint/acpi/usb.asl | 22 ++----------------- 3 files changed, 9 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/audio.asl b/src/southbridge/intel/lynxpoint/acpi/audio.asl index 98cdac9a90..43f2150b62 100644 --- a/src/southbridge/intel/lynxpoint/acpi/audio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/audio.asl @@ -7,15 +7,5 @@ Device (HDEF) { Name (_ADR, 0x001b0000) - - Name (PRWH, Package (){ 0x0d, 3 }) // LPT-H - Name (PRWL, Package (){ 0x6d, 3 }) // LPT-LP - - Method (_PRW, 0) { // Power Resources for Wake - If (\ISLP ()) { - Return (PRWL) - } Else { - Return (PRWH) - } - } + Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 }) } diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index cb5b823997..e683c752ce 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -2,6 +2,12 @@ /* Intel Lynx Point PCH support */ +#if CONFIG(INTEL_LYNXPOINT_LP) +#define DEFAULT_PRW_VALUE 0x6d +#else +#define DEFAULT_PRW_VALUE 0x0d +#endif + Scope (\) { // Return TRUE if chipset is LynxPoint-LP diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index e807398cb5..fbb7090819 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -6,16 +6,7 @@ Device (EHCI) { Name (_ADR, 0x001d0000) - Name (PRWH, Package (){ 0x0d, 3 }) // LPT-H - Name (PRWL, Package (){ 0x6d, 3 }) // LPT-LP - - Method (_PRW, 0) { // Power Resources for Wake - If (\ISLP ()) { - Return (PRWL) - } Else { - Return (PRWH) - } - } + Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 }) // Leave USB ports on for to allow Wake from USB @@ -337,16 +328,7 @@ Device (XHCI) Return () } - Name (PRWH, Package (){ 0x0d, 3 }) // LPT-H - Name (PRWL, Package (){ 0x6d, 3 }) // LPT-LP - - Method (_PRW, 0) { // Power Resources for Wake - If (\ISLP ()) { - Return (PRWL) - } Else { - Return (PRWH) - } - } + Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 }) // Leave USB ports on for to allow Wake from USB From e15dc9eb1e4aa8ae87e398fb0d6eb895f4bb86d5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 21:37:01 +0100 Subject: [PATCH 225/262] sb/intel/lynxpoint/acpi/lpc.asl: Simplify GPIOBASE resource MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LynxPoint-LP handles GPIOs differently, and LynxPoint-H has the same GPIO kind as previous-generation PCHs, such as Cougar Point. Remove some unneeded logic from `_CRS` and declare the GPIOBASE resource statically. The preprocessor allows later ACPI deduplication to remain reproducible. Change-Id: If771d5b6c3a1623da7d015ed50199877615409b2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46781 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/acpi/lpc.asl | 21 ++++++-------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index 8f41e67b44..a823b7084b 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -157,25 +157,16 @@ Device (LPCB) IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0xff) - // GPIO region may be 128 bytes or 4096 bytes - IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR1) +#if !CONFIG(INTEL_LYNXPOINT_LP) + // LynxPoint-LP GPIO resources are defined in the + // SerialIO GPIO device and LynxPoint-H GPIO resources + // are defined here. + IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) +#endif }) Method (_CRS, 0, NotSerialized) { - // LynxPoint-LP GPIO resources are defined in the - // SerialIO GPIO device and LynxPoint-H GPIO resources - // are defined here. - If (!\ISLP ()) { - CreateByteField (^RBUF, ^GPR1._LEN, R1LN) - CreateWordField (^RBUF, ^GPR1._MIN, R1MN) - CreateWordField (^RBUF, ^GPR1._MAX, R1MX) - - // Update GPIO region length - R1MN = DEFAULT_GPIOBASE - R1MX = DEFAULT_GPIOBASE - R1LN = DEFAULT_GPIOSIZE - } Return (RBUF) } } From a82f06cb8fd5899a37b6b73ec682e8058f42a93e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 22:50:08 +0100 Subject: [PATCH 226/262] sb/intel/lynxpoint/acpi: Split USB into EHCI and xHCI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: I0ce8f1e4aaa86d2f7607fec9214dc64d1f530c88 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46782 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/acpi/ehci.asl | 34 +++++++++++++++++++ src/southbridge/intel/lynxpoint/acpi/pch.asl | 7 ++-- .../lynxpoint/acpi/{usb.asl => xhci.asl} | 33 ------------------ 3 files changed, 39 insertions(+), 35 deletions(-) create mode 100644 src/southbridge/intel/lynxpoint/acpi/ehci.asl rename src/southbridge/intel/lynxpoint/acpi/{usb.asl => xhci.asl} (91%) diff --git a/src/southbridge/intel/lynxpoint/acpi/ehci.asl b/src/southbridge/intel/lynxpoint/acpi/ehci.asl new file mode 100644 index 0000000000..2a54304a2c --- /dev/null +++ b/src/southbridge/intel/lynxpoint/acpi/ehci.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// EHCI Controller 0:1d.0 + +Device (EHCI) +{ + Name (_ADR, 0x001d0000) + + Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 }) + + // Leave USB ports on for to allow Wake from USB + + Method (_S3D, 0) // Highest D State in S3 State + { + Return (2) + } + + Method (_S4D, 0) // Highest D State in S4 State + { + Return (2) + } + + Device (HUB7) + { + Name (_ADR, 0) + + Device (PRT1) { Name (_ADR, 1) } // USB Port 0 + Device (PRT2) { Name (_ADR, 2) } // USB Port 1 + Device (PRT3) { Name (_ADR, 3) } // USB Port 2 + Device (PRT4) { Name (_ADR, 4) } // USB Port 3 + Device (PRT5) { Name (_ADR, 5) } // USB Port 4 + Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + } +} diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index e683c752ce..40d206d3dd 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -67,8 +67,11 @@ Scope (\) // PCI Express Ports 0:1c.x #include -// USB 0:1d.0 and 0:1a.0 -#include "usb.asl" +// USB EHCI 0:1d.0 and 0:1a.0 +#include "ehci.asl" + +// USB XHCI 0:14.0 +#include "xhci.asl" // LPC Bridge 0:1f.0 #include "lpc.asl" diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl similarity index 91% rename from src/southbridge/intel/lynxpoint/acpi/usb.asl rename to src/southbridge/intel/lynxpoint/acpi/xhci.asl index fbb7090819..65f1869e10 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl @@ -1,38 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -// EHCI Controller 0:1d.0 - -Device (EHCI) -{ - Name (_ADR, 0x001d0000) - - Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 }) - - // Leave USB ports on for to allow Wake from USB - - Method (_S3D, 0) // Highest D State in S3 State - { - Return (2) - } - - Method (_S4D, 0) // Highest D State in S4 State - { - Return (2) - } - - Device (HUB7) - { - Name (_ADR, 0) - - Device (PRT1) { Name (_ADR, 1) } // USB Port 0 - Device (PRT2) { Name (_ADR, 2) } // USB Port 1 - Device (PRT3) { Name (_ADR, 3) } // USB Port 2 - Device (PRT4) { Name (_ADR, 4) } // USB Port 3 - Device (PRT5) { Name (_ADR, 5) } // USB Port 4 - Device (PRT6) { Name (_ADR, 6) } // USB Port 5 - } -} - // XHCI Controller 0:14.0 Device (XHCI) From 1fa487e1b32f94a8c009962365c00e0c19294647 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 22:53:06 +0100 Subject: [PATCH 227/262] sb/intel/lynxpoint/acpi/gpio.asl: Serialize GWAK method MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 576b7c7 (broadwell: gpio.asl: Make GWAK method serialized) made GWAK serialized for Broadwell. This commit follows suit on Lynx Point. The reason to serialize this method is because it creates named objects which depend on input parameters, and thus cannot be created elsewhere. Change-Id: I892700df3bba079e3280008f619017e3954d5a06 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46783 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/acpi/gpio.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/gpio.asl b/src/southbridge/intel/lynxpoint/acpi/gpio.asl index 1a50968617..358bdec26d 100644 --- a/src/southbridge/intel/lynxpoint/acpi/gpio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/gpio.asl @@ -47,7 +47,7 @@ Device (GPIO) // GWAK: Setup GPIO as ACPI GPE for Wake // Arg0: GPIO Number - Method (GWAK, 1, NotSerialized) + Method (GWAK, 1, Serialized) { // Local0 = GPIO Base Address Store (GPBS & ~1, Local0) From fe91192bf5f20e0d6f7f05d5b1166bd215614a99 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 23:08:04 +0100 Subject: [PATCH 228/262] haswell/lynxpoint: Drop remaining uses of `ISLP` method MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's no need to dynamically differentiate between traditional and Low Power platforms at runtime, and doing so makes code reuse more complex. Change-Id: Id40f2f5f41db00487af9115eabee8874c2399030 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46785 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/acpi/ctdp.asl | 14 ++--- src/southbridge/intel/lynxpoint/acpi/pch.asl | 6 --- src/southbridge/intel/lynxpoint/acpi/xhci.asl | 54 ++++++++++--------- 3 files changed, 35 insertions(+), 39 deletions(-) diff --git a/src/northbridge/intel/haswell/acpi/ctdp.asl b/src/northbridge/intel/haswell/acpi/ctdp.asl index 84c0f2f20a..47b794012c 100644 --- a/src/northbridge/intel/haswell/acpi/ctdp.asl +++ b/src/northbridge/intel/haswell/acpi/ctdp.asl @@ -79,13 +79,13 @@ Scope (\_SB.PCI0.MCHC) /* Calculate PL2 based on chip type */ Method (CPL2, 1, NotSerialized) { - If (\ISLP ()) { - /* Haswell ULT PL2 = 25W */ - Return (25 * 8) - } Else { - /* Haswell Mobile PL2 = 1.25 * PL1 */ - Return ((Arg0 * 125) / 100) - } +#if CONFIG(INTEL_LYNXPOINT_LP) + /* Haswell ULT PL2 = 25W */ + Return (25 * 8) +#else + /* Haswell Mobile PL2 = 1.25 * PL1 */ + Return ((Arg0 * 125) / 100) +#endif } /* Set Config TDP Down */ diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index 40d206d3dd..6829cff2c1 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -10,12 +10,6 @@ Scope (\) { - // Return TRUE if chipset is LynxPoint-LP - Method (ISLP, 0, NotSerialized) - { - Return (CONFIG(INTEL_LYNXPOINT_LP)) - } - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. OperationRegion (IO_T, SystemIO, 0x800, 0x10) Field (IO_T, ByteAcc, NoLock, Preserve) diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl index 65f1869e10..fbeb56200a 100644 --- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl +++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl @@ -213,26 +213,27 @@ Device (XHCI) ^D0D3 = 0 } - If (\ISLP ()) { - // Clear PCI 0xB0[14:13] - ^MB13 = 0 - ^MB14 = 0 +#if CONFIG(INTEL_LYNXPOINT_LP) + // Clear PCI 0xB0[14:13] + ^MB13 = 0 + ^MB14 = 0 - // Clear MMIO 0x816C[14,2] - CLK0 = 0 - CLK1 = 0 - } + // Clear MMIO 0x816C[14,2] + CLK0 = 0 + CLK1 = 0 // Set MMIO 0x8154[31] CLK2 = 1 - If (\ISLP ()) { - // Handle per-port reset if needed - LPS0 () + // Handle per-port reset if needed + LPS0 () - // Set MMIO 0x80e0[15] - AX15 = 1 - } + // Set MMIO 0x80e0[15] + AX15 = 1 +#else + // Set MMIO 0x8154[31] + CLK2 = 1 +#endif Return () } @@ -271,23 +272,24 @@ Device (XHCI) ^D0D3 = 0 } - If (\ISLP ()) { - // Set PCI 0xB0[14:13] - ^MB13 = 1 - ^MB14 = 1 +#if CONFIG(INTEL_LYNXPOINT_LP) + // Set PCI 0xB0[14:13] + ^MB13 = 1 + ^MB14 = 1 - // Set MMIO 0x816C[14,2] - CLK0 = 1 - CLK1 = 1 - } + // Set MMIO 0x816C[14,2] + CLK0 = 1 + CLK1 = 1 // Clear MMIO 0x8154[31] CLK2 = 0 - If (\ISLP ()) { - // Clear MMIO 0x80e0[15] - AX15 = 0 - } + // Clear MMIO 0x80e0[15] + AX15 = 0 +#else + // Clear MMIO 0x8154[31] + CLK2 = 0 +#endif // Put device in D3 ^D0D3 = 3 From 2f2ac4d814e03fd079a0db1dea24743ba7a8cca0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 23:01:54 +0100 Subject: [PATCH 229/262] sb/intel/lynxpoint/acpi/pch.asl: Drop unused FD definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These Function Disable definitions have been copied from Cougar Point, are not used by any mainboard, and may be incorrect. So, remove them. Change-Id: I36f732bce22ec33aab42beababe54c4d88e0205b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46784 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/acpi/pch.asl | 26 -------------------- 1 file changed, 26 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index 6829cff2c1..a878dc274d 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -26,32 +26,6 @@ Scope (\) HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable - Offset (0x3418), // FD (Function Disable) - , 1, // Reserved - PCID, 1, // PCI bridge disable - SA1D, 1, // SATA1 disable - SMBD, 1, // SMBUS disable - HDAD, 1, // Azalia disable - , 8, // Reserved - EH2D, 1, // EHCI #2 disable - LPBD, 1, // LPC bridge disable - EH1D, 1, // EHCI #1 disable - RP1D, 1, // Root Port 1 disable - RP2D, 1, // Root Port 2 disable - RP3D, 1, // Root Port 3 disable - RP4D, 1, // Root Port 4 disable - RP5D, 1, // Root Port 5 disable - RP6D, 1, // Root Port 6 disable - RP7D, 1, // Root Port 7 disable - RP8D, 1, // Root Port 8 disable - TTRD, 1, // Thermal sensor registers disable - SA2D, 1, // SATA2 disable - Offset (0x3428), // FD2 (Function Disable 2) - BDFD, 1, // Display BDF - ME1D, 1, // ME Interface 1 disable - ME2D, 1, // ME Interface 2 disable - IDRD, 1, // IDE redirect disable - KTCT, 1, // Keyboard Text redirect disable } } From f11e2d06167614950d337525a2cff3cfcc33b4a2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 23:13:54 +0100 Subject: [PATCH 230/262] soc/intel/broadwell/acpi: Rename `systemagent.asl` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename it to `hostbridge.asl`, which is what Haswell uses. Change-Id: I6f97fc5c9459fe6b66dcfcf51900c751beda0ebe Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46786 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/google/auron/dsdt.asl | 2 +- src/mainboard/google/jecht/dsdt.asl | 2 +- src/mainboard/intel/wtm2/dsdt.asl | 2 +- src/mainboard/purism/librem_bdw/dsdt.asl | 2 +- .../intel/broadwell/acpi/{systemagent.asl => hostbridge.asl} | 0 5 files changed, 4 insertions(+), 4 deletions(-) rename src/soc/intel/broadwell/acpi/{systemagent.asl => hostbridge.asl} (100%) diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index a61a669411..9da89ef439 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include + #include #include #include } diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index 6af99b4a77..05754ca5c0 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include + #include #include } } diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index c842e8b7f8..7d58eb6930 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include + #include #include } } diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index a4b5bd8ca8..3c0041e2f3 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -21,7 +21,7 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include + #include #include } } diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/soc/intel/broadwell/acpi/hostbridge.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/systemagent.asl rename to src/soc/intel/broadwell/acpi/hostbridge.asl From 66e21d2d28576cd205afb1c5ed336222267a0dca Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 23:39:10 +0100 Subject: [PATCH 231/262] nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's no need to perform manual shifting and masking when ACPI allows one to painlessly describe bitfields of a register. The now-unused DVEN definition will be dropped in a follow-up, alongside other definitions. Change-Id: Iab6972c78c1114c8e3dfee28320ae233421ff154 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46787 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/acpi/peg.asl | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/haswell/acpi/peg.asl b/src/northbridge/intel/haswell/acpi/peg.asl index 8dac128b8a..c63f3f9169 100644 --- a/src/northbridge/intel/haswell/acpi/peg.asl +++ b/src/northbridge/intel/haswell/acpi/peg.asl @@ -1,12 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +Field (\_SB.PCI0.MCHC.MCHP, DWordAcc, NoLock, Preserve) +{ + Offset (0x54), + , 1, + P2EN, 1, + P1EN, 1, + P0EN, 1, +} + Device (PEGP) { Name (_ADR, 0x00010000) Method (_STA) { - Return (((\_SB.PCI0.MCHC.DVEN >> 3) & 1) * 0xf) + Return (P0EN * 0xf) } Device (DEV0) @@ -21,7 +30,7 @@ Device (PEG1) Method (_STA) { - Return (((\_SB.PCI0.MCHC.DVEN >> 2) & 1) * 0xf) + Return (P1EN * 0xf) } Device (DEV0) @@ -36,7 +45,7 @@ Device (PEG2) Method (_STA) { - Return (((\_SB.PCI0.MCHC.DVEN >> 1) & 1) * 0xf) + Return (P2EN * 0xf) } Device (DEV0) From e339f9505bbf24ba41c37e4277456acad255d09a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 23:17:25 +0100 Subject: [PATCH 232/262] nb/intel/haswell/acpi/hostbridge.asl: Drop unused registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are not used anywhere and are not present on Broadwell. Change-Id: I2d1359286ac719cb5daefc955d5c6085e2949c1f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46788 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../intel/haswell/acpi/hostbridge.asl | 61 ------------------- 1 file changed, 61 deletions(-) diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index dc3a36fc95..f0cb86bd26 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -12,71 +12,10 @@ Device (MCHC) OperationRegion (MCHP, PCI_Config, 0x00, 0x100) Field (MCHP, DWordAcc, NoLock, Preserve) { - Offset (0x40), // EPBAR - EPEN, 1, // Enable - , 11, // - EPBR, 27, // EPBAR - - Offset (0x48), // MCHBAR - MHEN, 1, // Enable - , 14, // - MHBR, 24, // MCHBAR - Offset (0x54), - DVEN, 32, - Offset (0x60), // PCIe BAR - PXEN, 1, // Enable - PXSZ, 2, // BAR size - , 23, // - PXBR, 13, // PCIe BAR - - Offset (0x68), // DMIBAR - DMEN, 1, // Enable - , 11, // - DMBR, 27, // DMIBAR - Offset (0x70), // ME Base Address MEBA, 64, - - // ... - - Offset (0x80), // PAM0 - , 4, - PM0H, 2, - , 2, - Offset (0x81), // PAM1 - PM1L, 2, - , 2, - PM1H, 2, - , 2, - Offset (0x82), // PAM2 - PM2L, 2, - , 2, - PM2H, 2, - , 2, - Offset (0x83), // PAM3 - PM3L, 2, - , 2, - PM3H, 2, - , 2, - Offset (0x84), // PAM4 - PM4L, 2, - , 2, - PM4H, 2, - , 2, - Offset (0x85), // PAM5 - PM5L, 2, - , 2, - PM5H, 2, - , 2, - Offset (0x86), // PAM6 - PM6L, 2, - , 2, - PM6H, 2, - , 2, - Offset (0xa0), // Top of Used Memory TOM, 64, - Offset (0xbc), // Top of Low Used Memory TLUD, 32, } From 79e3a1f8a5c50d27948cb05310989b4e28f3f74c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 23:44:30 +0100 Subject: [PATCH 233/262] nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested with BUILD_TIMELESS=1, Google Wolf remains identical. Change-Id: I710581156937b042ba4cf5948c65d0795ad37bbf Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46789 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/asrock/b85m_pro4/dsdt.asl | 2 +- src/mainboard/asrock/h81m-hds/dsdt.asl | 2 +- src/mainboard/google/beltino/dsdt.asl | 2 +- src/mainboard/google/slippy/dsdt.asl | 2 +- src/mainboard/intel/baskingridge/dsdt.asl | 2 +- src/mainboard/lenovo/t440p/dsdt.asl | 2 +- src/mainboard/supermicro/x10slm-f/dsdt.asl | 2 +- .../intel/haswell/acpi/haswell.asl | 35 ------------------- .../intel/haswell/acpi/hostbridge.asl | 35 +++++++++++++++++++ 9 files changed, 42 insertions(+), 42 deletions(-) delete mode 100644 src/northbridge/intel/haswell/acpi/haswell.asl diff --git a/src/mainboard/asrock/b85m_pro4/dsdt.asl b/src/mainboard/asrock/b85m_pro4/dsdt.asl index ea6dde65c1..bba5c2e593 100644 --- a/src/mainboard/asrock/b85m_pro4/dsdt.asl +++ b/src/mainboard/asrock/b85m_pro4/dsdt.asl @@ -20,7 +20,7 @@ DefinitionBlock( Device (\_SB.PCI0) { - #include + #include #include #include } diff --git a/src/mainboard/asrock/h81m-hds/dsdt.asl b/src/mainboard/asrock/h81m-hds/dsdt.asl index dd55ba8bbd..d3e7ba17d0 100644 --- a/src/mainboard/asrock/h81m-hds/dsdt.asl +++ b/src/mainboard/asrock/h81m-hds/dsdt.asl @@ -20,7 +20,7 @@ DefinitionBlock( { Device (PCI0) { - #include + #include #include #include } diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl index 07a1d03fca..45442db902 100644 --- a/src/mainboard/google/beltino/dsdt.asl +++ b/src/mainboard/google/beltino/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include + #include #include } } diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl index 71b7863ac2..8ca683dcb2 100644 --- a/src/mainboard/google/slippy/dsdt.asl +++ b/src/mainboard/google/slippy/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include + #include #include #include diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index 7fdd69bc60..5971917f9d 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include + #include #include #include diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl index 426d8017ed..9a54673ec8 100644 --- a/src/mainboard/lenovo/t440p/dsdt.asl +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -24,7 +24,7 @@ DefinitionBlock( Device (\_SB.PCI0) { - #include + #include #include #include } diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl index 08a26ab088..f8e9884f3f 100644 --- a/src/mainboard/supermicro/x10slm-f/dsdt.asl +++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl @@ -19,7 +19,7 @@ DefinitionBlock( Device (\_SB.PCI0) { - #include + #include #include #include } diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl deleted file mode 100644 index 57344abc1d..0000000000 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "../haswell.h" -#include "hostbridge.asl" -#include "peg.asl" -#include - -/* PCI Device Resource Consumption */ -Device (PDRC) -{ - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 1) - - Name (PDRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) - Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) - Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) - Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH - Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH - Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH - -#if CONFIG(CHROMEOS_RAMOOPS) - Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) -#endif - }) - - // Current Resource Settings - Method (_CRS, 0, Serialized) - { - Return (PDRS) - } -} diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index f0cb86bd26..3e617ecbb9 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include "../haswell.h" +#include + Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI @@ -167,3 +170,35 @@ Method (_CRS, 0, Serialized) /* Configurable TDP */ #include "ctdp.asl" + +/* PCI Express Graphics */ +#include "peg.asl" + +/* PCI Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 1) + + Name (PDRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) + Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) + Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) + Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH + Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH + Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH + +#if CONFIG(CHROMEOS_RAMOOPS) + Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) +#endif + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) + { + Return (PDRS) + } +} From 90f6a31bc2765f989475a30be81b9c075a6fd692 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 26 Oct 2020 00:01:13 +0100 Subject: [PATCH 234/262] nb/intel/haswell/acpi: Move PEG and CTDP includes downwards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change is just to align with Broadwell. Change-Id: I25a481503f5df79502f5ae60c87e7dacb781adad Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46790 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/acpi/hostbridge.asl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 3e617ecbb9..35246b3bc6 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -168,12 +168,6 @@ Method (_CRS, 0, Serialized) Return (MCRS) } -/* Configurable TDP */ -#include "ctdp.asl" - -/* PCI Express Graphics */ -#include "peg.asl" - /* PCI Device Resource Consumption */ Device (PDRC) { @@ -202,3 +196,9 @@ Device (PDRC) Return (PDRS) } } + +/* Configurable TDP */ +#include "ctdp.asl" + +/* PCI Express Graphics */ +#include "peg.asl" From c29d8e046804cc922d84feb092caa9d6088f7b2b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 26 Oct 2020 00:02:31 +0100 Subject: [PATCH 235/262] nb/intel/haswell/acpi: Do not add PEG devices for LP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Haswell Low Power variants do not have PEG at all. Change-Id: Ia5577104b00bfc8713b54c3c43f8dcdd3bc367df Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46791 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/acpi/hostbridge.asl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 35246b3bc6..28a33d842c 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -200,5 +200,7 @@ Device (PDRC) /* Configurable TDP */ #include "ctdp.asl" +#if !CONFIG(INTEL_LYNXPOINT_LP) /* PCI Express Graphics */ #include "peg.asl" +#endif From a472e33634b7c9709fccb3c60d1d21b2c75e1347 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 26 Oct 2020 00:08:47 +0100 Subject: [PATCH 236/262] broadwell: Factor out `acpi_fill_madt` function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is identical for all Broadwell mainboards, thus deduplicate it. Change-Id: I74559fbe42e44aa4d15ced5d88f6c15a1bf5203b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46792 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/google/auron/acpi_tables.c | 13 ------------- src/mainboard/google/jecht/acpi_tables.c | 13 ------------- src/mainboard/intel/wtm2/acpi_tables.c | 13 ------------- src/mainboard/purism/librem_bdw/acpi_tables.c | 13 ------------- src/soc/intel/broadwell/acpi.c | 9 ++++++++- src/soc/intel/broadwell/include/soc/acpi.h | 1 - 6 files changed, 8 insertions(+), 54 deletions(-) diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index 10dc637f01..970ec9d5cf 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -24,18 +23,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->flvl = 1; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - return acpi_madt_irq_overrides(current); -} - void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_MOBILE; diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index f824cd8f72..580c0b6532 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include @@ -25,18 +24,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->flvl = 1; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - return acpi_madt_irq_overrides(current); -} - void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_MOBILE; diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 62eb09aff6..53c8926fb6 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include @@ -23,18 +22,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->tmax = MAX_TEMPERATURE; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - return acpi_madt_irq_overrides(current); -} - void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_MOBILE; diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c index ca6f64b089..df3d15e965 100644 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ b/src/mainboard/purism/librem_bdw/acpi_tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include @@ -10,15 +9,3 @@ void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); } - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - return acpi_madt_irq_overrides(current); -} diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 1b4db1dae6..3d5e74ae5c 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -496,12 +497,18 @@ unsigned long northbridge_write_acpi_tables(const struct device *const dev, return current; } -unsigned long acpi_madt_irq_overrides(unsigned long current) +unsigned long acpi_fill_madt(unsigned long current) { int sci = acpi_sci_irq(); acpi_madt_irqoverride_t *irqovr; uint16_t flags = MP_IRQ_TRIGGER_LEVEL; + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2, IO_APIC_ADDR, 0); + /* INT_SRC_OVR */ irqovr = (void *)current; current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index 0bf63a495e..39d6cb4692 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -12,7 +12,6 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -unsigned long acpi_madt_irq_overrides(unsigned long current); unsigned long northbridge_write_acpi_tables(const struct device *dev, unsigned long current, struct acpi_rsdp *rsdp); #endif From a0426267e330c60aa74528a06a0e130efe2ad32f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 26 Oct 2020 00:17:52 +0100 Subject: [PATCH 237/262] broadwell: Flatten `acpi_init_gnvs` function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of relying on mainboards to call it, do like Lynx Point. Change-Id: Idb7457e0734e19d0a26f0762079e273b6e740475 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46793 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/google/auron/acpi_tables.c | 2 -- src/mainboard/google/jecht/acpi_tables.c | 2 -- src/mainboard/intel/wtm2/acpi_tables.c | 2 -- src/mainboard/purism/librem_bdw/acpi_tables.c | 1 - src/soc/intel/broadwell/acpi.c | 25 ------------------- src/soc/intel/broadwell/pch/lpc.c | 25 +++++++++++++++++++ 6 files changed, 25 insertions(+), 32 deletions(-) diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index 970ec9d5cf..5284cef29f 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -8,8 +8,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 580c0b6532..1197c0ca1c 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -9,8 +9,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 53c8926fb6..21a94bca8d 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -9,8 +9,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c index df3d15e965..e127a56a26 100644 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ b/src/mainboard/purism/librem_bdw/acpi_tables.c @@ -7,5 +7,4 @@ void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); } diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 3d5e74ae5c..7366642c62 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -148,31 +148,6 @@ static int get_cores_per_package(void) return cores; } -void acpi_init_gnvs(struct global_nvs *gnvs) -{ - /* Set unknown wake source */ - gnvs->pm1i = -1; - - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 2111913a0e..73b83e4e09 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include #include @@ -621,6 +623,29 @@ static void southcluster_inject_dsdt(const struct device *device) if (gnvs) { acpi_create_gnvs(gnvs); + + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + +#if CONFIG(CONSOLE_CBMEM) + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); +#endif + + if (CONFIG(CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } + } + /* And tell SMI about it */ apm_control(APM_CNT_GNVS_UPDATE); From 3bd017356a7766c4884e55a28ca481c8a9110ceb Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 26 Oct 2020 00:27:09 +0100 Subject: [PATCH 238/262] soc/intel/broadwell: Relocate CPU files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ib2ddce78db21db9c8deac632a77ecd71eb9887c2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46794 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/Makefile.inc | 24 +-------------- src/soc/intel/broadwell/cpu/Makefile.inc | 29 +++++++++++++++++++ .../{bootblock/cpu.c => cpu/bootblock.c} | 0 src/soc/intel/broadwell/{ => cpu}/cpu.c | 0 .../{romstage/cpu.c => cpu/romstage.c} | 0 .../intel/broadwell/{ => cpu}/smmrelocate.c | 0 src/soc/intel/broadwell/{ => cpu}/tsc_freq.c | 0 src/soc/intel/broadwell/romstage/Makefile.inc | 2 -- 8 files changed, 30 insertions(+), 25 deletions(-) create mode 100644 src/soc/intel/broadwell/cpu/Makefile.inc rename src/soc/intel/broadwell/{bootblock/cpu.c => cpu/bootblock.c} (100%) rename src/soc/intel/broadwell/{ => cpu}/cpu.c (100%) rename src/soc/intel/broadwell/{romstage/cpu.c => cpu/romstage.c} (100%) rename src/soc/intel/broadwell/{ => cpu}/smmrelocate.c (100%) rename src/soc/intel/broadwell/{ => cpu}/tsc_freq.c (100%) diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index ce1dd9cbf6..dc6bd93c34 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,24 +1,13 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm -subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/intel/microcode -subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/intel/common +subdirs-y += cpu subdirs-y += pch -bootblock-y += bootblock/cpu.c bootblock-y += bootblock/systemagent.c -bootblock-y += ../../../cpu/intel/car/bootblock.c -bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S -bootblock-y += ../../../cpu/x86/early_reset.S ramstage-y += acpi.c -ramstage-y += cpu.c ramstage-y += finalize.c ramstage-y += gma.c ramstage-y += memmap.c @@ -29,18 +18,7 @@ ramstage-y += pei_data.c romstage-y += pei_data.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c -ramstage-y += smmrelocate.c ramstage-y += systemagent.c -bootblock-y += tsc_freq.c -ramstage-y += tsc_freq.c -romstage-y += tsc_freq.c -smm-y += tsc_freq.c -postcar-y += tsc_freq.c -verstage-y += tsc_freq.c - -postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S - -cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin CPPFLAGS_common += -Isrc/soc/intel/broadwell/include diff --git a/src/soc/intel/broadwell/cpu/Makefile.inc b/src/soc/intel/broadwell/cpu/Makefile.inc new file mode 100644 index 0000000000..e9f46376af --- /dev/null +++ b/src/soc/intel/broadwell/cpu/Makefile.inc @@ -0,0 +1,29 @@ +subdirs-y += ../../../../cpu/x86/lapic +subdirs-y += ../../../../cpu/x86/mtrr +subdirs-y += ../../../../cpu/x86/smm +subdirs-y += ../../../../cpu/x86/tsc +subdirs-y += ../../../../cpu/intel/microcode +subdirs-y += ../../../../cpu/intel/turbo +subdirs-y += ../../../../cpu/intel/common + +bootblock-y += bootblock.c +bootblock-y += ../../../../cpu/intel/car/bootblock.c +bootblock-y += ../../../../cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../../../../cpu/x86/early_reset.S + +romstage-y += romstage.c +romstage-y += ../../../../cpu/intel/car/romstage.c + +postcar-y += ../../../../cpu/intel/car/non-evict/exit_car.S + +ramstage-y += cpu.c +ramstage-y += smmrelocate.c + +bootblock-y += tsc_freq.c +ramstage-y += tsc_freq.c +romstage-y += tsc_freq.c +smm-y += tsc_freq.c +postcar-y += tsc_freq.c +verstage-y += tsc_freq.c + +cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/cpu/bootblock.c similarity index 100% rename from src/soc/intel/broadwell/bootblock/cpu.c rename to src/soc/intel/broadwell/cpu/bootblock.c diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu/cpu.c similarity index 100% rename from src/soc/intel/broadwell/cpu.c rename to src/soc/intel/broadwell/cpu/cpu.c diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/cpu/romstage.c similarity index 100% rename from src/soc/intel/broadwell/romstage/cpu.c rename to src/soc/intel/broadwell/cpu/romstage.c diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/cpu/smmrelocate.c similarity index 100% rename from src/soc/intel/broadwell/smmrelocate.c rename to src/soc/intel/broadwell/cpu/smmrelocate.c diff --git a/src/soc/intel/broadwell/tsc_freq.c b/src/soc/intel/broadwell/cpu/tsc_freq.c similarity index 100% rename from src/soc/intel/broadwell/tsc_freq.c rename to src/soc/intel/broadwell/cpu/tsc_freq.c diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index b77e7a579d..65cb9adee5 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,5 +1,3 @@ -romstage-y += ../../../../cpu/intel/car/romstage.c -romstage-y += cpu.c romstage-y += raminit.c romstage-y += report_platform.c romstage-y += romstage.c From 1500dd081b386db9b03ff78e74831cf6c9f88ba7 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 26 Oct 2020 00:32:42 +0100 Subject: [PATCH 239/262] soc/intel/broadwell: Flatten northbridge folder structure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Having folders for bootblock and romstage is no longer necessary. Change-Id: I7d1f4063de6a1a1ff9ee7478e94f889a50102054 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46795 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/Makefile.inc | 9 ++++++--- .../broadwell/{bootblock/systemagent.c => bootblock.c} | 0 .../broadwell/{romstage/systemagent.c => early_init.c} | 0 src/soc/intel/broadwell/{romstage => }/raminit.c | 0 src/soc/intel/broadwell/{romstage => }/report_platform.c | 0 src/soc/intel/broadwell/{romstage => }/romstage.c | 0 src/soc/intel/broadwell/romstage/Makefile.inc | 4 ---- 7 files changed, 6 insertions(+), 7 deletions(-) rename src/soc/intel/broadwell/{bootblock/systemagent.c => bootblock.c} (100%) rename src/soc/intel/broadwell/{romstage/systemagent.c => early_init.c} (100%) rename src/soc/intel/broadwell/{romstage => }/raminit.c (100%) rename src/soc/intel/broadwell/{romstage => }/report_platform.c (100%) rename src/soc/intel/broadwell/{romstage => }/romstage.c (100%) delete mode 100644 src/soc/intel/broadwell/romstage/Makefile.inc diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index dc6bd93c34..7ee69908f8 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,11 +1,14 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) -subdirs-y += romstage - subdirs-y += cpu subdirs-y += pch -bootblock-y += bootblock/systemagent.c +bootblock-y += bootblock.c + +romstage-y += early_init.c +romstage-y += raminit.c +romstage-y += report_platform.c +romstage-y += romstage.c ramstage-y += acpi.c ramstage-y += finalize.c diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock.c similarity index 100% rename from src/soc/intel/broadwell/bootblock/systemagent.c rename to src/soc/intel/broadwell/bootblock.c diff --git a/src/soc/intel/broadwell/romstage/systemagent.c b/src/soc/intel/broadwell/early_init.c similarity index 100% rename from src/soc/intel/broadwell/romstage/systemagent.c rename to src/soc/intel/broadwell/early_init.c diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/raminit.c similarity index 100% rename from src/soc/intel/broadwell/romstage/raminit.c rename to src/soc/intel/broadwell/raminit.c diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/report_platform.c similarity index 100% rename from src/soc/intel/broadwell/romstage/report_platform.c rename to src/soc/intel/broadwell/report_platform.c diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage.c similarity index 100% rename from src/soc/intel/broadwell/romstage/romstage.c rename to src/soc/intel/broadwell/romstage.c diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc deleted file mode 100644 index 65cb9adee5..0000000000 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -romstage-y += raminit.c -romstage-y += report_platform.c -romstage-y += romstage.c -romstage-y += systemagent.c From ed222f12ec367aa2fdf55c9516dd9eafd64303aa Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 26 Oct 2020 00:40:46 +0100 Subject: [PATCH 240/262] soc/intel/broadwell: Split up acpi.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ie9c57b6f5c226cee8797027941fa03e69de52923 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46796 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/acpi.c | 396 ----------------------- src/soc/intel/broadwell/cpu/Makefile.inc | 1 + src/soc/intel/broadwell/cpu/acpi.c | 395 ++++++++++++++++++++++ src/soc/intel/broadwell/pch/Makefile.inc | 1 + src/soc/intel/broadwell/pch/acpi.c | 55 ++++ 5 files changed, 452 insertions(+), 396 deletions(-) create mode 100644 src/soc/intel/broadwell/cpu/acpi.c create mode 100644 src/soc/intel/broadwell/pch/acpi.c diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 7366642c62..9b5ac9ef7e 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -26,128 +26,6 @@ #include #include -/* - * List of supported C-states in this processor. Only the ULT parts support C8, - * C9, and C10. - */ -enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ - C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ - NUM_C_STATES -}; - -#define MWAIT_RES(state, sub_state) \ - { \ - .addrl = (((state) << 4) | (sub_state)), \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ - } - -static acpi_cstate_t cstate_map[NUM_C_STATES] = { - [C_STATE_C0] = { }, - [C_STATE_C1] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 0), - }, - [C_STATE_C1E] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 1), - }, - [C_STATE_C3] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = 900, - .resource = MWAIT_RES(1, 0), - }, - [C_STATE_C6_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 800, - .resource = MWAIT_RES(2, 0), - }, - [C_STATE_C6_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 800, - .resource = MWAIT_RES(2, 1), - }, - [C_STATE_C7_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 0), - }, - [C_STATE_C7_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 1), - }, - [C_STATE_C7S_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 2), - }, - [C_STATE_C7S_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 3), - }, - [C_STATE_C8] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(3), - .power = 600, - .resource = MWAIT_RES(4, 0), - }, - [C_STATE_C9] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(4), - .power = 500, - .resource = MWAIT_RES(5, 0), - }, - [C_STATE_C10] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(5), - .power = 400, - .resource = MWAIT_RES(6, 0), - }, -}; - -static int cstate_set_s0ix[3] = { - C_STATE_C1E, - C_STATE_C7S_LONG_LAT, - C_STATE_C10 -}; - -static int cstate_set_non_s0ix[3] = { - C_STATE_C1E, - C_STATE_C3, - C_STATE_C7S_LONG_LAT -}; - -static int get_cores_per_package(void) -{ - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; - - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; - - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, @@ -155,252 +33,6 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static acpi_tstate_t tss_table_fine[] = { - { 100, 1000, 0, 0x00, 0 }, - { 94, 940, 0, 0x1f, 0 }, - { 88, 880, 0, 0x1e, 0 }, - { 82, 820, 0, 0x1d, 0 }, - { 75, 760, 0, 0x1c, 0 }, - { 69, 700, 0, 0x1b, 0 }, - { 63, 640, 0, 0x1a, 0 }, - { 57, 580, 0, 0x19, 0 }, - { 50, 520, 0, 0x18, 0 }, - { 44, 460, 0, 0x17, 0 }, - { 38, 400, 0, 0x16, 0 }, - { 32, 340, 0, 0x15, 0 }, - { 25, 280, 0, 0x14, 0 }, - { 19, 220, 0, 0x13, 0 }, - { 13, 160, 0, 0x12, 0 }, -}; - -static acpi_tstate_t tss_table_coarse[] = { - { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1f, 0 }, - { 75, 750, 0, 0x1e, 0 }, - { 63, 625, 0, 0x1d, 0 }, - { 50, 500, 0, 0x1c, 0 }, - { 38, 375, 0, 0x1b, 0 }, - { 25, 250, 0, 0x1a, 0 }, - { 13, 125, 0, 0x19, 0 }, -}; - -static void generate_T_state_entries(int core, int cores_per_package) -{ - /* Indicate SW_ALL coordination for T-states */ - acpigen_write_TSD_package(core, cores_per_package, SW_ALL); - - /* Indicate FFixedHW so OS will use MSR */ - acpigen_write_empty_PTC(); - - /* Set a T-state limit that can be modified in NVS */ - acpigen_write_TPC("\\TLVL"); - - /* - * CPUID.(EAX=6):EAX[5] indicates support - * for extended throttle levels. - */ - if (cpuid_eax(6) & (1 << 5)) - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_fine), tss_table_fine); - else - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_coarse), tss_table_coarse); -} - -static void generate_C_state_entries(void) -{ - acpi_cstate_t map[3]; - int *set; - int i; - - config_t *config = config_of_soc(); - - if (config->s0ix_enable) - set = cstate_set_s0ix; - else - set = cstate_set_non_s0ix; - - for (i = 0; i < 3; i++) { - memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); - map[i].ctype = i + 1; - } - - /* Generate C-state tables */ - acpigen_write_CST_package(map, ARRAY_SIZE(map)); -} - -static int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; - - return (int)power; -} - -static void generate_P_state_entries(int core, int cores_per_package) -{ - int ratio_min, ratio_max, ratio_turbo, ratio_step; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; - msr_t msr; - - /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) - coord_type = SW_ANY; - else - coord_type = HW_ALL; - - /* Get bus ratio limits and calculate clock speeds */ - msr = rdmsr(MSR_PLATFORM_INFO); - ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - - /* Determine if this CPU has configurable TDP */ - if (cpu_config_tdp_levels()) { - /* Set max ratio to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - ratio_max = msr.lo & 0xff; - } else { - /* Max Non-Turbo Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; - } - clock_max = ratio_max * CPU_BCLK; - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - msr = rdmsr(MSR_PKG_POWER_SKU); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with no limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = PSS_RATIO_STEP; - num_entries = (ratio_max - ratio_min) / ratio_step; - while (num_entries > PSS_MAX_ENTRIES-1) { - ratio_step <<= 1; - num_entries >>= 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - ratio_turbo = msr.lo & 0xff; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_turbo << 8, /*control*/ - ratio_turbo << 8); /*status*/ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - } - - /* First regular entry is max non-turbo ratio */ - acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_max << 8, /*control*/ - ratio_max << 8); /*status*/ - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - - /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * CPU_BCLK; - - acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio << 8, /*control*/ - ratio << 8); /*status*/ - } - - /* Fix package length */ - acpigen_pop_len(); -} - -void generate_cpu_entries(const struct device *device) -{ - int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; - int totalcores = dev_count_cpu(); - int cores_per_package = get_cores_per_package(); - int numcpus = totalcores/cores_per_package; - - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); - - for (cpuID = 1; cpuID <= numcpus; cpuID++) { - for (coreID = 1; coreID <= cores_per_package; coreID++) { - if (coreID > 1) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_SB.CPUx */ - acpigen_write_processor( - (cpuID - 1) * cores_per_package+coreID - 1, - pcontrol_blk, plen); - - /* Generate P-state tables */ - generate_P_state_entries( - coreID - 1, cores_per_package); - - /* Generate C-state tables */ - generate_C_state_entries(); - - /* Generate T-state tables */ - generate_T_state_entries( - cpuID - 1, cores_per_package); - - acpigen_pop_len(); - } - } - - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, cores_per_package); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(cores_per_package); -} - static unsigned long acpi_fill_dmar(unsigned long current) { struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); @@ -471,31 +103,3 @@ unsigned long northbridge_write_acpi_tables(const struct device *const dev, return current; } - -unsigned long acpi_fill_madt(unsigned long current) -{ - int sci = acpi_sci_irq(); - acpi_madt_irqoverride_t *irqovr; - uint16_t flags = MP_IRQ_TRIGGER_LEVEL; - - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); - - if (sci >= 20) - flags |= MP_IRQ_POLARITY_LOW; - else - flags |= MP_IRQ_POLARITY_HIGH; - - /* SCI */ - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags); - - return current; -} diff --git a/src/soc/intel/broadwell/cpu/Makefile.inc b/src/soc/intel/broadwell/cpu/Makefile.inc index e9f46376af..803696a1f0 100644 --- a/src/soc/intel/broadwell/cpu/Makefile.inc +++ b/src/soc/intel/broadwell/cpu/Makefile.inc @@ -16,6 +16,7 @@ romstage-y += ../../../../cpu/intel/car/romstage.c postcar-y += ../../../../cpu/intel/car/non-evict/exit_car.S +ramstage-y += acpi.c ramstage-y += cpu.c ramstage-y += smmrelocate.c diff --git a/src/soc/intel/broadwell/cpu/acpi.c b/src/soc/intel/broadwell/cpu/acpi.c new file mode 100644 index 0000000000..ec3d588a44 --- /dev/null +++ b/src/soc/intel/broadwell/cpu/acpi.c @@ -0,0 +1,395 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * List of supported C-states in this processor. Only the ULT parts support C8, + * C9, and C10. + */ +enum { + C_STATE_C0, /* 0 */ + C_STATE_C1, /* 1 */ + C_STATE_C1E, /* 2 */ + C_STATE_C3, /* 3 */ + C_STATE_C6_SHORT_LAT, /* 4 */ + C_STATE_C6_LONG_LAT, /* 5 */ + C_STATE_C7_SHORT_LAT, /* 6 */ + C_STATE_C7_LONG_LAT, /* 7 */ + C_STATE_C7S_SHORT_LAT, /* 8 */ + C_STATE_C7S_LONG_LAT, /* 9 */ + C_STATE_C8, /* 10 */ + C_STATE_C9, /* 11 */ + C_STATE_C10, /* 12 */ + NUM_C_STATES +}; + +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +static acpi_cstate_t cstate_map[NUM_C_STATES] = { + [C_STATE_C0] = { }, + [C_STATE_C1] = { + .latency = 0, + .power = 1000, + .resource = MWAIT_RES(0, 0), + }, + [C_STATE_C1E] = { + .latency = 0, + .power = 1000, + .resource = MWAIT_RES(0, 1), + }, + [C_STATE_C3] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = 900, + .resource = MWAIT_RES(1, 0), + }, + [C_STATE_C6_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 800, + .resource = MWAIT_RES(2, 0), + }, + [C_STATE_C6_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 800, + .resource = MWAIT_RES(2, 1), + }, + [C_STATE_C7_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 700, + .resource = MWAIT_RES(3, 0), + }, + [C_STATE_C7_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 700, + .resource = MWAIT_RES(3, 1), + }, + [C_STATE_C7S_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 700, + .resource = MWAIT_RES(3, 2), + }, + [C_STATE_C7S_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 700, + .resource = MWAIT_RES(3, 3), + }, + [C_STATE_C8] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(3), + .power = 600, + .resource = MWAIT_RES(4, 0), + }, + [C_STATE_C9] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(4), + .power = 500, + .resource = MWAIT_RES(5, 0), + }, + [C_STATE_C10] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(5), + .power = 400, + .resource = MWAIT_RES(6, 0), + }, +}; + +static int cstate_set_s0ix[3] = { + C_STATE_C1E, + C_STATE_C7S_LONG_LAT, + C_STATE_C10 +}; + +static int cstate_set_non_s0ix[3] = { + C_STATE_C1E, + C_STATE_C3, + C_STATE_C7S_LONG_LAT +}; + +static int get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +static acpi_tstate_t tss_table_fine[] = { + { 100, 1000, 0, 0x00, 0 }, + { 94, 940, 0, 0x1f, 0 }, + { 88, 880, 0, 0x1e, 0 }, + { 82, 820, 0, 0x1d, 0 }, + { 75, 760, 0, 0x1c, 0 }, + { 69, 700, 0, 0x1b, 0 }, + { 63, 640, 0, 0x1a, 0 }, + { 57, 580, 0, 0x19, 0 }, + { 50, 520, 0, 0x18, 0 }, + { 44, 460, 0, 0x17, 0 }, + { 38, 400, 0, 0x16, 0 }, + { 32, 340, 0, 0x15, 0 }, + { 25, 280, 0, 0x14, 0 }, + { 19, 220, 0, 0x13, 0 }, + { 13, 160, 0, 0x12, 0 }, +}; + +static acpi_tstate_t tss_table_coarse[] = { + { 100, 1000, 0, 0x00, 0 }, + { 88, 875, 0, 0x1f, 0 }, + { 75, 750, 0, 0x1e, 0 }, + { 63, 625, 0, 0x1d, 0 }, + { 50, 500, 0, 0x1c, 0 }, + { 38, 375, 0, 0x1b, 0 }, + { 25, 250, 0, 0x1a, 0 }, + { 13, 125, 0, 0x19, 0 }, +}; + +static void generate_T_state_entries(int core, int cores_per_package) +{ + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + acpigen_write_empty_PTC(); + + /* Set a T-state limit that can be modified in NVS */ + acpigen_write_TPC("\\TLVL"); + + /* + * CPUID.(EAX=6):EAX[5] indicates support + * for extended throttle levels. + */ + if (cpuid_eax(6) & (1 << 5)) + acpigen_write_TSS_package( + ARRAY_SIZE(tss_table_fine), tss_table_fine); + else + acpigen_write_TSS_package( + ARRAY_SIZE(tss_table_coarse), tss_table_coarse); +} + +static void generate_C_state_entries(void) +{ + acpi_cstate_t map[3]; + int *set; + int i; + + config_t *config = config_of_soc(); + + if (config->s0ix_enable) + set = cstate_set_s0ix; + else + set = cstate_set_non_s0ix; + + for (i = 0; i < 3; i++) { + memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i].ctype = i + 1; + } + + /* Generate C-state tables */ + acpigen_write_CST_package(map, ARRAY_SIZE(map)); +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + + return (int)power; +} + +static void generate_P_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) + coord_type = SW_ANY; + else + coord_type = HW_ALL; + + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ + + /* Determine if this CPU has configurable TDP */ + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + clock_max = ratio_max * CPU_BCLK; + + /* Calculate CPU TDP in mW */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + msr = rdmsr(MSR_PKG_POWER_SKU); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = (ratio_max - ratio_min) / ratio_step; + while (num_entries > PSS_MAX_ENTRIES-1) { + ratio_step <<= 1; + num_entries >>= 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /*MHz*/ + power_max, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio_turbo << 8, /*control*/ + ratio_turbo << 8); /*status*/ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /*MHz*/ + power_max, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio_max << 8, /*control*/ + ratio_max << 8); /*status*/ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * CPU_BCLK; + + acpigen_write_PSS_package( + clock, /*MHz*/ + power, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio << 8, /*control*/ + ratio << 8); /*status*/ + } + + /* Fix package length */ + acpigen_pop_len(); +} + +void generate_cpu_entries(const struct device *device) +{ + int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; + int totalcores = dev_count_cpu(); + int cores_per_package = get_cores_per_package(); + int numcpus = totalcores/cores_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); + + for (cpuID = 1; cpuID <= numcpus; cpuID++) { + for (coreID = 1; coreID <= cores_per_package; coreID++) { + if (coreID > 1) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_SB.CPUx */ + acpigen_write_processor( + (cpuID - 1) * cores_per_package+coreID - 1, + pcontrol_blk, plen); + + /* Generate P-state tables */ + generate_P_state_entries( + coreID - 1, cores_per_package); + + /* Generate C-state tables */ + generate_C_state_entries(); + + /* Generate T-state tables */ + generate_T_state_entries( + cpuID - 1, cores_per_package); + + acpigen_pop_len(); + } + } + + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, cores_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_processor_cnot(cores_per_package); +} diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc index 1c196136c4..119534fccd 100644 --- a/src/soc/intel/broadwell/pch/Makefile.inc +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -1,5 +1,6 @@ bootblock-y += bootblock.c +ramstage-y += acpi.c ramstage-y += adsp.c romstage-y += early_pch.c ramstage-$(CONFIG_ELOG) += elog.c diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c new file mode 100644 index 0000000000..712bb46f8a --- /dev/null +++ b/src/soc/intel/broadwell/pch/acpi.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +unsigned long acpi_fill_madt(unsigned long current) +{ + int sci = acpi_sci_irq(); + acpi_madt_irqoverride_t *irqovr; + uint16_t flags = MP_IRQ_TRIGGER_LEVEL; + + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); + + if (sci >= 20) + flags |= MP_IRQ_POLARITY_LOW; + else + flags |= MP_IRQ_POLARITY_HIGH; + + /* SCI */ + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags); + + return current; +} From 50650427dc3a0b144a3a06a9936d8c85819dc059 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 13 Nov 2020 12:32:55 +0100 Subject: [PATCH 241/262] mb/clevo/cml-u: Fix up comment style MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Idefc15fec1d62d68d88e91c76f59e1a60a3996b6 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47564 Reviewed-by: Michael Niewöhner Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c b/src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c index 4b0ddd4823..46651e8c16 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c +++ b/src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c @@ -6,6 +6,6 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) { /* Configure pads prior to SiliconInit() in case there's any - * dependencies during hardware initialization. */ + dependencies during hardware initialization. */ cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } From 33b92efa5168ab8687b6bbc5c653ba8913d4e8a4 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 13 Nov 2020 12:34:47 +0100 Subject: [PATCH 242/262] mb/supermicro/x11-lga1151-series: Fix up comment style MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I5b6191d2b5f6fd6d127934eda56e3c24181b0c4c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47565 Reviewed-by: Michael Niewöhner Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/mainboard/supermicro/x11-lga1151-series/ramstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c index 5de606d807..9262e2ec1d 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c +++ b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c @@ -6,6 +6,6 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) { /* Configure pads prior to SiliconInit() in case there's any - * dependencies during hardware initialization. */ + dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } From a262fc6b0761350066a5b2b086ce67447ac40a20 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 12 Nov 2020 14:37:41 +0100 Subject: [PATCH 243/262] soc/amd/common/block/include: make include guards more uniform TEST=Timeless build doesn't change for Mandolin and Gardenia. Change-Id: I5d3ae1459c333658f4c86388f1822d92ca13c658 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47514 Tested-by: build bot (Jenkins) Reviewed-by: Jeremy Soller Reviewed-by: Martin Roth Reviewed-by: Jason Glenesk Reviewed-by: Marshall Dawson --- src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/acpi.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/acpimmio.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/acpimmio_map.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/agesawrapper.h | 6 +++--- .../amd/common/block/include/amdblocks/agesawrapper_call.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/alink.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/amd_pci_util.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/biosram.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/car.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/chip.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/dimm_spd.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/espi.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/gpio_banks.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/hda.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/image.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/lpc.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/psp.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/reset.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/s3_resume.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/sata.h | 6 +++--- src/soc/amd/common/block/include/amdblocks/spi.h | 6 +++--- 23 files changed, 69 insertions(+), 69 deletions(-) diff --git a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h index 6933a08f11..54223233db 100644 --- a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h +++ b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __CALLOUTS_AMD_AGESA_H__ -#define __CALLOUTS_AMD_AGESA_H__ +#ifndef __AMD_BLOCK_CALLOUTS_AGESA_H__ +#define __AMD_BLOCK_CALLOUTS_AGESA_H__ #include #include @@ -69,4 +69,4 @@ typedef struct { extern const BIOS_CALLOUT_STRUCT BiosCallouts[]; extern const int BiosCalloutsLen; -#endif /* __CALLOUTS_AMD_AGESA_H__ */ +#endif /* __AMD_BLOCK_CALLOUTS_AGESA_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index b6244cb70d..7a9206d009 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMDBLOCKS_ACPI_H__ -#define __AMDBLOCKS_ACPI_H__ +#ifndef __AMD_BLOCK_ACPI_H__ +#define __AMD_BLOCK_ACPI_H__ #include #include @@ -44,4 +44,4 @@ void set_pm1cnt_s5(void); void acpi_enable_sci(void); void acpi_disable_sci(void); -#endif /* __AMDBLOCKS_ACPI_H__ */ +#endif /* __AMD_BLOCK_ACPI_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 2775b52116..6d96fcd550 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __AMDBLOCKS_ACPIMMIO_H__ -#define __AMDBLOCKS_ACPIMMIO_H__ +#ifndef __AMD_BLOCK_ACPIMMIO_H__ +#define __AMD_BLOCK_ACPIMMIO_H__ #include #include @@ -508,4 +508,4 @@ static inline void aoac_write8(uint8_t reg, uint8_t value) write8(acpimmio_aoac + reg, value); } -#endif /* __AMDBLOCKS_ACPIMMIO_H__ */ +#endif /* __AMD_BLOCK_ACPIMMIO_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 758a55622e..0e80ff404c 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __AMDBLOCKS_ACPIMMIO_MAP_H__ -#define __AMDBLOCKS_ACPIMMIO_MAP_H__ +#ifndef __AMD_BLOCK_ACPIMMIO_MAP_H__ +#define __AMD_BLOCK_ACPIMMIO_MAP_H__ /* * The following AcpiMmio register block mapping represents definitions @@ -132,4 +132,4 @@ #endif -#endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */ +#endif /* __AMD_BLOCK_ACPIMMIO_MAP_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h index f30fba39b1..85505d1c1c 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AGESAWRAPPER_H__ -#define __AGESAWRAPPER_H__ +#ifndef __AMD_BLOCK_AGESAWRAPPER_H__ +#define __AMD_BLOCK_AGESAWRAPPER_H__ #include @@ -39,4 +39,4 @@ void SetNbMidParams(GNB_MID_CONFIGURATION *params); void set_board_env_params(GNB_ENV_CONFIGURATION *params); void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly); -#endif /* __AGESAWRAPPER_H__ */ +#endif /* __AMD_BLOCK_AGESAWRAPPER_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h index dea70bbb00..7174f5e70b 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AGESAWRAPPER_CALL_H__ -#define __AGESAWRAPPER_CALL_H__ +#ifndef __AMD_BLOCK_AGESAWRAPPER_CALL_H__ +#define __AMD_BLOCK_AGESAWRAPPER_CALL_H__ #include #include @@ -41,4 +41,4 @@ static inline u32 do_agesawrapper(AGESA_STRUCT_NAME func, const char *name) return (u32)ret; } -#endif /* __AGESAWRAPPER_CALL_H__ */ +#endif /* __AMD_BLOCK_AGESAWRAPPER_CALL_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/alink.h b/src/soc/amd/common/block/include/amdblocks/alink.h index bfb17244c1..be1917c932 100644 --- a/src/soc/amd/common/block/include/amdblocks/alink.h +++ b/src/soc/amd/common/block/include/amdblocks/alink.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMDBLOCKS_ALINK_H__ -#define __AMDBLOCKS_ALINK_H__ +#ifndef __AMD_BLOCK_ALINK_H__ +#define __AMD_BLOCK_ALINK_H__ #include @@ -32,4 +32,4 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); void alink_ax_indx(u32 space /* c or p? */, u32 axindc, u32 mask, u32 val); -#endif /* __AMDBLOCKS_ALINK_H__ */ +#endif /* __AMD_BLOCK_ALINK_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h index 255ebd65c6..067ff98367 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMDBLOCKS_PCI_MMCONF_H__ -#define __AMDBLOCKS_PCI_MMCONF_H__ +#ifndef __AMD_BLOCK_PCI_MMCONF_H__ +#define __AMD_BLOCK_PCI_MMCONF_H__ void enable_pci_mmconf(void); -#endif +#endif /* __AMD_BLOCK_PCI_MMCONF_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index 764078ff54..a37c1fdb23 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_PCI_UTIL_H__ -#define __AMD_PCI_UTIL_H__ +#ifndef __AMD_BLOCK_PCI_UTIL_H__ +#define __AMD_BLOCK_PCI_UTIL_H__ #include #include @@ -31,4 +31,4 @@ void write_pci_cfg_irqs(void); void write_pci_int_table(void); const struct irq_idx_name *sb_get_apic_reg_association(size_t *size); -#endif /* __AMD_PCI_UTIL_H__ */ +#endif /* __AMD_BLOCK_PCI_UTIL_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h index 226fc173d4..a7a73e0353 100644 --- a/src/soc/amd/common/block/include/amdblocks/biosram.h +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMDBLOCKS_BIOSRAM_H__ -#define __AMDBLOCKS_BIOSRAM_H__ +#ifndef __AMD_BLOCK_BIOSRAM_H__ +#define __AMD_BLOCK_BIOSRAM_H__ #include @@ -26,4 +26,4 @@ uint32_t get_uma_size(void); /* Returns the saved UMA base */ uint64_t get_uma_base(void); -#endif +#endif /* __AMD_BLOCK_BIOSRAM_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/car.h b/src/soc/amd/common/block/include/amdblocks/car.h index f5a20fb140..055f294625 100644 --- a/src/soc/amd/common/block/include/amdblocks/car.h +++ b/src/soc/amd/common/block/include/amdblocks/car.h @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_CAR_H__ -#define __AMD_CAR_H__ +#ifndef __AMD_BLOCK_CAR_H__ +#define __AMD_BLOCK_CAR_H__ #include void ap_teardown_car(uint32_t flags); -#endif /* __AMD_CAR_H__ */ +#endif /* __AMD_BLOCK_CAR_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/chip.h b/src/soc/amd/common/block/include/amdblocks/chip.h index d15046463b..87944212bd 100644 --- a/src/soc/amd/common/block/include/amdblocks/chip.h +++ b/src/soc/amd/common/block/include/amdblocks/chip.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMDBLOCKS_CHIP_H__ -#define __AMDBLOCKS_CHIP_H__ +#ifndef __AMD_BLOCK_CHIP_H__ +#define __AMD_BLOCK_CHIP_H__ #include #include @@ -28,4 +28,4 @@ struct soc_amd_common_config { */ const struct soc_amd_common_config *soc_get_common_config(void); -#endif +#endif /* __AMD_BLOCK_CHIP_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h index 1556da13d4..5bfb4942f2 100644 --- a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h +++ b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __DIMMSPD_H__ -#define __DIMMSPD_H__ +#ifndef __AMD_BLOCK_DIMM_SPD_H__ +#define __AMD_BLOCK_DIMM_SPD_H__ #include #include @@ -15,4 +15,4 @@ int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len); int sb_read_spd(uint8_t spdAddress, char *buf, size_t len); -#endif +#endif /* __AMD_BLOCK_DIMM_SPD_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 2bfef890cc..c2d822e545 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMDBLOCKS_ESPI_H__ -#define __AMDBLOCKS_ESPI_H__ +#ifndef __AMD_BLOCK_ESPI_H__ +#define __AMD_BLOCK_ESPI_H__ #include #include @@ -118,4 +118,4 @@ void espi_update_static_bar(uintptr_t bar); */ int espi_setup(void); -#endif /* __AMDBLOCKS_ESPI_H__ */ +#endif /* __AMD_BLOCK_ESPI_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index d5ef5d2bd3..4b2bfddac1 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMDBLOCK_GPIO_BANKS_H__ -#define __AMDBLOCK_GPIO_BANKS_H__ +#ifndef __AMD_BLOCK_GPIO_BANKS_H__ +#define __AMD_BLOCK_GPIO_BANKS_H__ #include @@ -361,4 +361,4 @@ void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) /* May be implemented by soc to handle special cases */ void soc_gpio_hook(uint8_t gpio, uint8_t mux); -#endif /* __AMDBLOCK_GPIO_BANKS_H__ */ +#endif /* __AMD_BLOCK_GPIO_BANKS_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/hda.h b/src/soc/amd/common/block/include/amdblocks/hda.h index ee6d6fbf7a..55feb6b434 100644 --- a/src/soc/amd/common/block/include/amdblocks/hda.h +++ b/src/soc/amd/common/block/include/amdblocks/hda.h @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMDBLOCKS_HDA_H__ -#define __AMDBLOCKS_HDA_H__ +#ifndef __AMD_BLOCK_HDA_H__ +#define __AMD_BLOCK_HDA_H__ #include /* SoC callback to add any quirks to HDA device node in SSDT. */ void hda_soc_ssdt_quirks(const struct device *dev); -#endif /* __AMDBLOCKS_HDA_H__ */ +#endif /* __AMD_BLOCK_HDA_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/image.h b/src/soc/amd/common/block/include/amdblocks/image.h index 17f1d224c1..92d4002b81 100644 --- a/src/soc/amd/common/block/include/amdblocks/image.h +++ b/src/soc/amd/common/block/include/amdblocks/image.h @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_IMAGE_H__ -#define __AMD_IMAGE_H__ +#ifndef __AMD_BLOCK_IMAGE_H__ +#define __AMD_BLOCK_IMAGE_H__ #include void *amd_find_image(const void *start_address, const void *end_address, uint32_t alignment, const char name[8]); -#endif /* __AMD_IMAGE_H__ */ +#endif /* __AMD_BLOCK_IMAGE_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 7412e7bb1b..1b69a5b398 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMDBLOCKS_LPC_H__ -#define __AMDBLOCKS_LPC_H__ +#ifndef __AMD_BLOCK_LPC_H__ +#define __AMD_BLOCK_LPC_H__ #include @@ -198,4 +198,4 @@ void lpc_set_spibase(uint32_t base); /* Enable SPI ROM (SPI_ROM_ENABLE, SPI_ROM_ALT_ENABLE) */ void lpc_enable_spi_rom(uint32_t enable); -#endif /* __AMDBLOCKS_LPC_H__ */ +#endif /* __AMD_BLOCK_LPC_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index ca820bf31e..f509a5a4df 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_PSP_H__ -#define __AMD_PSP_H__ +#ifndef __AMD_BLOCK_PSP_H__ +#define __AMD_BLOCK_PSP_H__ /* Get the mailbox base address - specific to family of device. */ void *soc_get_mbox_address(void); @@ -74,4 +74,4 @@ void psp_notify_sx_info(u8 sleep_type); int psp_load_named_blob(enum psp_blob_type type, const char *name); -#endif /* __AMD_PSP_H__ */ +#endif /* __AMD_BLOCK_PSP_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/reset.h b/src/soc/amd/common/block/include/amdblocks/reset.h index 6f272ad85e..7912bd2d45 100644 --- a/src/soc/amd/common/block/include/amdblocks/reset.h +++ b/src/soc/amd/common/block/include/amdblocks/reset.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_RESET_H__ -#define __AMD_RESET_H__ +#ifndef __AMD_BLOCK_RESET_H__ +#define __AMD_BLOCK_RESET_H__ #include #include @@ -26,4 +26,4 @@ static inline __noreturn void cold_reset(void) halt(); } -#endif /* __AMD_RESET_H__ */ +#endif /* __AMD_BLOCK_RESET_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/s3_resume.h b/src/soc/amd/common/block/include/amdblocks/s3_resume.h index 305ed04806..6931a5f5cd 100644 --- a/src/soc/amd/common/block/include/amdblocks/s3_resume.h +++ b/src/soc/amd/common/block/include/amdblocks/s3_resume.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_S3_RESUME_H__ -#define __AMD_S3_RESUME_H__ +#ifndef __AMD_BLOCK_S3_RESUME_H__ +#define __AMD_BLOCK_S3_RESUME_H__ #include @@ -9,4 +9,4 @@ AGESA_STATUS OemInitResume(S3_DATA_BLOCK *dataBlock); AGESA_STATUS OemS3LateRestore(S3_DATA_BLOCK *dataBlock); AGESA_STATUS OemS3Save(S3_DATA_BLOCK *dataBlock); -#endif /* __AMD_S3_RESUME_H__ */ +#endif /* __AMD_BLOCK_S3_RESUME_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/sata.h b/src/soc/amd/common/block/include/amdblocks/sata.h index 2ce6ec04ad..945b9cd0b4 100644 --- a/src/soc/amd/common/block/include/amdblocks/sata.h +++ b/src/soc/amd/common/block/include/amdblocks/sata.h @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMDBLOCKS_SATA_H__ -#define __AMDBLOCKS_SATA_H__ +#ifndef __AMD_BLOCK_SATA_H__ +#define __AMD_BLOCK_SATA_H__ #include void soc_enable_sata_features(struct device *dev); -#endif /* __AMDBLOCKS_SATA_H__ */ +#endif /* __AMD_BLOCK_SATA_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index b0080dae8e..18940a32fc 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMDBLOCKS_SPI_H__ -#define __AMDBLOCKS_SPI_H__ +#ifndef __AMD_BLOCK_SPI_H__ +#define __AMD_BLOCK_SPI_H__ #include @@ -108,4 +108,4 @@ void spi_write8(uint8_t reg, uint8_t val); void spi_write16(uint8_t reg, uint16_t val); void spi_write32(uint8_t reg, uint32_t val); -#endif /* __AMDBLOCKS_SPI_H__ */ +#endif /* __AMD_BLOCK_SPI_H__ */ From 16433c9c9295e90a3e18c75e42bdb80a059df3b3 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 12 Nov 2020 14:48:54 +0100 Subject: [PATCH 244/262] soc/amd: factor out _SOC_DEV macro into common block TEST=Timeless build doesn't change for Mandolin and Gardenia. Change-Id: I1aef68459569536207697bfca407145a7b5334f4 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47515 Tested-by: build bot (Jenkins) Reviewed-by: Jeremy Soller Reviewed-by: Martin Roth Reviewed-by: Jason Glenesk Reviewed-by: Marshall Dawson --- .../amd/common/block/include/amdblocks/pci_devs.h | 15 +++++++++++++++ src/soc/amd/picasso/include/soc/pci_devs.h | 8 +------- src/soc/amd/stoneyridge/include/soc/pci_devs.h | 8 +------- 3 files changed, 17 insertions(+), 14 deletions(-) create mode 100644 src/soc/amd/common/block/include/amdblocks/pci_devs.h diff --git a/src/soc/amd/common/block/include/amdblocks/pci_devs.h b/src/soc/amd/common/block/include/amdblocks/pci_devs.h new file mode 100644 index 0000000000..8a38ac15d7 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/pci_devs.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __AMD_BLOCK_PCI_DEVS_H__ +#define __AMD_BLOCK_PCI_DEVS_H__ + +#include + +#if !defined(__SIMPLE_DEVICE__) +#include +#define _SOC_DEV(slot, func) pcidev_on_root(slot, func) +#else +#define _SOC_DEV(slot, func) PCI_DEV(0, slot, func) +#endif + +#endif /* __AMD_BLOCK_PCI_DEVS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 27334f1462..83c0bcc7e3 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -4,13 +4,7 @@ #define __PI_PICASSO_PCI_DEVS_H__ #include - -#if !defined(__SIMPLE_DEVICE__) -#include -#define _SOC_DEV(slot, func) pcidev_on_root(slot, func) -#else -#define _SOC_DEV(slot, func) PCI_DEV(0, slot, func) -#endif +#include /* GNB Root Complex */ #define GNB_DEV 0x0 diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 316f532d0e..03a12336f7 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -4,13 +4,7 @@ #define __PI_STONEYRIDGE_PCI_DEVS_H__ #include - -#if !defined(__SIMPLE_DEVICE__) -#include -#define _SOC_DEV(slot, func) pcidev_on_root(slot, func) -#else -#define _SOC_DEV(slot, func) PCI_DEV(0, slot, func) -#endif +#include /* GNB Root Complex */ #define GNB_DEV 0x0 From 9fe0615eccc254901fa83043f7db23e84c4a3511 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 11 Nov 2020 10:26:11 +0100 Subject: [PATCH 245/262] Doc/relnotes/4.13: Add several relevant changes While some of these have little impact, they are worth mentioning here. Change-Id: Idbf629ae77b8918ff1d93edb7b6c4669bbbe17df Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47444 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../releases/coreboot-4.13-relnotes.md | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index ddbea81c2c..139fa20865 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -13,6 +13,27 @@ Update this document with changes that should be in the release notes. Significant changes ------------------- +### Native refcode implementation for Bay Trail + +Bay Trail no longer needs a refcode binary to function properly. The refcode +was reimplemented as coreboot code, which should be functionally equivalent. +Thus, coreboot only needs to run the MRC.bin to successfully boot Bay Trail. + +### Unusual config files to build test more code + +There's some new highly-unusual config files, whose only purpose is to coerce +Jenkins into build-testing several disabled-by-default coreboot config options. +This prevents them from silently decaying over time because of build failures. + +### Initial support for Intel Trusted eXecution Technology + +coreboot now supports enabling Intel TXT. Though it's not feature-complete yet, +the code allows successfully launching tboot, a Measured Launch Environment. It +was tested on Haswell using an Asrock B85M Pro4 mainboard with TPM 2.0 on LPC. +Though support for other platforms is still not ready, it is being worked on. +The Haswell MRC.bin needs to be patched so as to enable DPR. Given that the MRC +binary cannot be redistributed, the best long-term solution is to replace it. + ### Hidden PCI devices This new functionality takes advantage of the existing 'hidden' keyword in the From 12cfcd90dd328a7cf015d0da69dbdaf0719fa290 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 13 Nov 2020 17:26:50 +0100 Subject: [PATCH 246/262] mb/hp/folio_9480m: Update northbridge ACPI filename MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix build errors, since `haswell.asl` was dropped in commit 79e3a1f8a5 (nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl`) Change-Id: Iaec5de2d74dd81c58a581bb511ba6a63629141aa Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47575 Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/hp/folio_9480m/dsdt.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/hp/folio_9480m/dsdt.asl b/src/mainboard/hp/folio_9480m/dsdt.asl index f030e72471..b5343726ff 100644 --- a/src/mainboard/hp/folio_9480m/dsdt.asl +++ b/src/mainboard/hp/folio_9480m/dsdt.asl @@ -20,7 +20,7 @@ DefinitionBlock( Device (\_SB.PCI0) { - #include + #include #include #include } From 5df952bc2bcf97f884e9e6fbeabc8d64233590b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 2 Oct 2020 17:57:47 +0200 Subject: [PATCH 247/262] soc/intel/common: add Kconfig to enable/disable the ACPI PM timer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, the ACPI PM timer state gets set in devicetree by the option PmTimerDisabled. However, it is not board design dependent. Thus, add a user-selectable Kconfig option. Disabling the PM ACPI Timer is only valid when PM Timer emulation is supported and is only possible, when there is a hardware PM Timer (APL does not have one for example). SoCs, where the hardware PM Timer can be disabled must select `PM_ACPI_TIMER_OPTIONAL`. This new Kconfig gets used in the follow-up commits of this series. Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45952 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/common/block/pmc/Kconfig | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index 5cb2bea1d9..b420865c92 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -43,3 +43,25 @@ config PMC_LOW_POWER_MODE_PROGRAM help Enable this for PMC devices to perform registers programming to ensure low power in active idle scenario. + +config PM_ACPI_TIMER_OPTIONAL + bool + default n + help + This needs to be selected by SoCs, where the hardware PM Timer + can be disabled, to show the ACPI PM Timer Kconfig in menuconfig. + +if PM_ACPI_TIMER_OPTIONAL + +config USE_PM_ACPI_TIMER + bool "Enable ACPI PM timer" + default y + help + This should be disabled for devices running on battery since + it can draw much power. Further, it must be disabled, if S0ix + is enabled. + + Disabling this option also stops the hardware TCO timer and makes + the TCO watchdog unavailable. + +endif # PM_ACPI_TIMER_OPTIONAL From 8a64ad09a100adf478d65e42e4cc10a18ccc2d16 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 2 Oct 2020 19:10:39 +0200 Subject: [PATCH 248/262] soc/intel/{skl,cnl}: drop duplicate PM ACPI timer disabling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit FSP already disables the PM ACPI timer, when EnableTcoTimer=0. Test: clevo/l140cu and supermicro/x11ssm-f have the PM ACPI timer disable bit set when EnableTcoTimer=0. Change-Id: If370d3acf87ae6d1d7c64bf27228877cdd92ab2d Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45954 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/cannonlake/Kconfig | 1 - src/soc/intel/cannonlake/finalize.c | 13 ------------- src/soc/intel/skylake/Kconfig | 1 - src/soc/intel/skylake/finalize.c | 10 ---------- 4 files changed, 25 deletions(-) diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 2b862e7e86..d61435aaa6 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -98,7 +98,6 @@ config CPU_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_0 select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK - select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 3fe00ba8cc..8387bb86f7 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -56,21 +56,8 @@ static void pch_finalize(void) */ pch_thermal_configuration(); - /* - * Disable ACPI PM timer based on dt policy - * - * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. - * Disabling ACPI PM timer also switches off TCO - * - * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is - * just required to get to chip config. PCH_DEV_PMC is hidden by this - * point and hence removed from the root bus. pcidev_path_on_root thus - * returns NULL for PCH_DEV_PMC device. - */ config = config_of_soc(); pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) - pmc_disable_acpi_timer(); if (config->s0ix_enable && config->cppmvric2_adsposcdis) { /* Enable Audio DSP OSC qualification for S0ix */ diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 20b302db14..f71beaed52 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -43,7 +43,6 @@ config CPU_SPECIFIC_OPTIONS select REG_SCRIPT select SA_ENABLE_DPR select PMC_GLOBAL_RESET_ENABLE_LOCK - select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 6b8576a593..f8b36a48bd 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -62,16 +62,6 @@ static void pch_finalize_script(struct device *dev) */ pch_thermal_configuration(); - /* - * Disable ACPI PM timer based on dt policy - * - * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. - * Disabling ACPI PM timer also switches off TCO - */ - - if (config->PmTimerDisabled) - pmc_disable_acpi_timer(); - /* we should disable Heci1 based on the devicetree policy */ if (config->HeciEnabled == 0) pch_disable_heci(); From a1843d8411d3caebd0600421c2b6a4c6b0588c19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 2 Oct 2020 18:28:22 +0200 Subject: [PATCH 249/262] soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and set the FSP option for PM ACPI timer enablement from its value instead of using the old devicetree option. Also drop the obsolete devicetree option from soc code and from the mainboards and add a corresponding Kconfig entry instead. Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955 Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/51nb/x210/devicetree.cb | 1 - src/mainboard/asrock/h110m/devicetree.cb | 1 - src/mainboard/facebook/monolith/Kconfig | 3 +++ src/mainboard/facebook/monolith/devicetree.cb | 1 - src/mainboard/google/eve/Kconfig | 3 +++ src/mainboard/google/eve/devicetree.cb | 1 - src/mainboard/google/fizz/Kconfig | 4 ++++ src/mainboard/google/fizz/variants/baseboard/devicetree.cb | 1 - src/mainboard/google/glados/Kconfig | 3 +++ src/mainboard/google/glados/devicetree.cb | 1 - src/mainboard/google/hatch/Kconfig | 3 +++ src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 -- src/mainboard/google/poppy/Kconfig | 4 ++++ src/mainboard/google/poppy/variants/atlas/devicetree.cb | 1 - src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 1 - src/mainboard/google/poppy/variants/nami/devicetree.cb | 1 - src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 1 - src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 1 - src/mainboard/google/poppy/variants/rammus/devicetree.cb | 1 - src/mainboard/google/poppy/variants/soraka/devicetree.cb | 1 - src/mainboard/intel/kblrvp/Kconfig | 5 +++++ src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb | 1 - src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb | 1 - src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb | 3 --- src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb | 1 - src/mainboard/intel/kunimitsu/Kconfig | 4 ++++ src/mainboard/intel/kunimitsu/devicetree.cb | 1 - src/mainboard/intel/saddlebrook/devicetree.cb | 1 - src/mainboard/libretrend/lt1000/Kconfig | 3 +++ src/mainboard/libretrend/lt1000/devicetree.cb | 1 - src/mainboard/protectli/vault_kbl/Kconfig | 3 +++ src/mainboard/protectli/vault_kbl/devicetree.cb | 1 - src/mainboard/purism/librem_skl/devicetree.cb | 1 - src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 1 - src/soc/intel/cannonlake/Kconfig | 1 + src/soc/intel/cannonlake/chip.h | 2 -- src/soc/intel/cannonlake/fsp_params.c | 5 ++--- src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/chip.c | 3 ++- src/soc/intel/skylake/chip.h | 1 - 40 files changed, 41 insertions(+), 34 deletions(-) diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 561bd6f54b..49e2964f45 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -55,7 +55,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "0" register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 57acd33570..909c050412 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -24,7 +24,6 @@ chip soc/intel/skylake # FSP Configuration register "PrimaryDisplay" = "Display_PEG" register "SaGv" = "SaGv_Enabled" - register "PmTimerDisabled" = "0" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 92c02a799e..ddbc27ef91 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -92,4 +92,7 @@ config VBOOT_ALWAYS_ALLOW_UDC def_bool y depends on VBOOT && !CHROMEOS +config USE_PM_ACPI_TIMER + default n + endif diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 15ab7efb71..974d00e41a 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" - register "PmTimerDisabled" = "1" register "HeciEnabled" = "0" register "SataSalpSupport" = "1" diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index f7e82959ce..9316c7f213 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -76,4 +76,7 @@ config INCLUDE_NHLT_BLOBS config UART_FOR_CONSOLE int default 2 + +config USE_PM_ACPI_TIMER + default n endif diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 519e53ba6c..6c1144b736 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -51,7 +51,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 48d04e791b..a21df378ef 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -96,4 +96,8 @@ config INCLUDE_NHLT_BLOBS_KARMA config UART_FOR_CONSOLE int default 2 + +config USE_PM_ACPI_TIMER + default n + endif # BOARD_GOOGLE_BASEBOARD_FIZZ diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 703ef5b775..22935f4520 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -82,7 +82,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" register "SendVrMbxCmd" = "1" # IMVP8 workaround # Intersil VR c-state issue workaround diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 50e56ce9e7..144fe97b8b 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -86,4 +86,7 @@ config CONSOLE_SERIAL bool default n +config USE_PM_ACPI_TIMER + default n + endif diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 2dfb71f2c0..ba3f204d09 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -50,7 +50,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "4" # 4s register "PmConfigSlpSusMinAssert" = "3" # 4s register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" # Enable Root port 1 register "PcieRpEnable[0]" = "1" diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 1e132ed0fd..4d7d5ec990 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -186,4 +186,7 @@ config VBOOT select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_EARLY_EC_SYNC +config USE_PM_ACPI_TIMER + default n + endif # BOARD_GOOGLE_HATCH_COMMON diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 01c0d234f9..31f6652401 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -53,8 +53,6 @@ chip soc/intel/cannonlake # putting it under register "common_soc_config" in overridetree.cb file. register "common_soc_config.pch_thermal_trip" = "77" - register "PmTimerDisabled" = "1" - # Select CPU PL2/PL4 config register "cpu_pl2_4_cfg" = "baseline" diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index bda2ca0a18..d8b90bcdc3 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -214,4 +214,8 @@ config VBOOT config UART_FOR_CONSOLE int default 2 + +config USE_PM_ACPI_TIMER + default n + endif # BOARD_GOOGLE_BASEBOARD_POPPY diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 668e72dc21..2f230faf3f 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -57,7 +57,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 7, diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 0b3d6c0346..ed846f61e2 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -47,7 +47,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 42f810800a..5117c545f1 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -46,7 +46,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" # Intersil VR c-state issue workaround # send VR mailbox command for IA/GT/SA rails diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 3d91884d51..b1340f8058 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -47,7 +47,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" # VR Slew rate setting for improving audible noise register "AcousticNoiseMitigation" = "1" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index ab1588af80..2d077c29fc 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -52,7 +52,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 7, diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 2334a179df..2a916fc1df 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -57,7 +57,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index c69875597d..a3ee45c809 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -47,7 +47,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index f1db3dac3f..5dccdaed93 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -84,4 +84,9 @@ config DIMM_SPD_SIZE config UART_FOR_CONSOLE int default 2 + +config USE_PM_ACPI_TIMER + default n if BOARD_INTEL_KBLRVP3 + default n if BOARD_INTEL_KBLRVP7 + endif diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index fbf08cde3f..782f3dc524 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -3,7 +3,6 @@ chip soc/intel/skylake # FSP Configuration register "DspEnable" = "0" register "ScsEmmcHs400Enabled" = "0" - register "PmTimerDisabled" = "0" register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 0754c0735e..397155b789 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -8,7 +8,6 @@ chip soc/intel/skylake # FSP Configuration register "DspEnable" = "1" - register "PmTimerDisabled" = "1" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 11f9c01501..e649ed72e7 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -12,9 +12,6 @@ chip soc/intel/skylake # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen2_dec" = "0x000c0201" - # FSP Configuration - register "PmTimerDisabled" = "1" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 78552fcdd5..115e338199 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -6,7 +6,6 @@ chip soc/intel/skylake # FSP Configuration register "ScsEmmcHs400Enabled" = "0" - register "PmTimerDisabled" = "0" register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 6e745d947a..b9b7d5a394 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -60,4 +60,8 @@ config INCLUDE_NHLT_BLOBS config UART_FOR_CONSOLE int default 2 + +config USE_PM_ACPI_TIMER + default n + endif diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 07afb7bd1b..85586cb137 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -27,7 +27,6 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" - register "PmTimerDisabled" = "1" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 5c64326e3e..0da097fa4a 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -21,7 +21,6 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" - register "PmTimerDisabled" = "0" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s diff --git a/src/mainboard/libretrend/lt1000/Kconfig b/src/mainboard/libretrend/lt1000/Kconfig index 9c4223ae4b..bfd532a85a 100644 --- a/src/mainboard/libretrend/lt1000/Kconfig +++ b/src/mainboard/libretrend/lt1000/Kconfig @@ -44,4 +44,7 @@ config CBFS_SIZE hex default 0x600000 +config USE_PM_ACPI_TIMER + default n + endif diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 911690f053..f6e73c6bd6 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -55,7 +55,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------------+-------+ diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig index 518bb6dca5..7cf80e0a91 100644 --- a/src/mainboard/protectli/vault_kbl/Kconfig +++ b/src/mainboard/protectli/vault_kbl/Kconfig @@ -51,4 +51,7 @@ config CBFS_SIZE hex default 0x600000 +config USE_PM_ACPI_TIMER + default n + endif diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index e6e748a247..d8e68a2373 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -40,7 +40,6 @@ chip soc/intel/skylake register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "1" - register "PmTimerDisabled" = "1" register "SaGv" = "SaGv_Enabled" register "IslVrCmd" = "2" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 2c73280148..b796fbbc9c 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -61,7 +61,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "0" # EC/KBC requires continuous mode register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 4f8ceb6815..15ea78538e 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -41,7 +41,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "0" register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d61435aaa6..7b9b88be61 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -97,6 +97,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select REG_SCRIPT + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index dc24e9bd8f..2a52627be7 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -273,8 +273,6 @@ struct soc_intel_cannonlake_config { /* Enable C6 DRAM */ uint8_t enable_c6dram; - uint8_t PmTimerDisabled; - /* * SLP_S3 Minimum Assertion Width Policy * 1 = 60us diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index fe7641f27b..9b28d3d795 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -248,6 +248,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); + params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER); + /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; @@ -432,9 +434,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa; params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr; - /* Disable PCH ACPI timer */ - params->EnableTcoTimer = !config->PmTimerDisabled; - /* Apply minimum assertion width settings if non-zero */ if (config->PchPmSlpS3MinAssert) params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert; diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f71beaed52..ce46d06b03 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_0 select REG_SCRIPT select SA_ENABLE_DPR + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 1e13428252..e2aee07114 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -235,6 +235,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Legacy 8254 timer support */ params->Early8254ClockGatingEnable = !CONFIG(USE_LEGACY_8254_TIMER); + params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER); + memcpy(params->SerialIoDevMode, config->SerialIoDevMode, sizeof(params->SerialIoDevMode)); @@ -297,7 +299,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Device4Enable = dev && dev->enabled; dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); params->PchThermalDeviceEnable = dev && dev->enabled; - params->EnableTcoTimer = !config->PmTimerDisabled; tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 41482f10bd..0bab45ab22 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -460,7 +460,6 @@ struct soc_intel_skylake_config { * Setting to 0 (default) disables Heci1 and hides the device from OS */ u8 HeciEnabled; - u8 PmTimerDisabled; /* * Enable VR specific mailbox command From 19325dac95fe50411d1c2a6caf580d3c3c76bd70 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 12 Nov 2020 20:23:52 +0530 Subject: [PATCH 250/262] vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1454 List of changes: 1. FSP-M Header: - Add new UPD Lp5CccConfig - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust UPD Offset for Reservedxx, PsOnEnable, RpPtmBytes, PmSupport, GtFreqMax, Hwp, TccActivationOffset, Cx, PchLockDownGlobalSmi, PcieRpLtrMaxSnoopLatency, PcieRpLtrMaxNoSnoopLatency, UnusedUpdSpace45 Change-Id: I973f48b2af0336f04ee16cd1c4c91940a49af0e3 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/47244 Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .../intel/fsp/fsp2_0/alderlake/FspmUpd.h | 22 +++++-- .../intel/fsp/fsp2_0/alderlake/FspsUpd.h | 60 +++++++++---------- 2 files changed, 46 insertions(+), 36 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index a4b885db47..552f50af3b 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -880,7 +880,17 @@ typedef struct { /** Offset 0x0797 - Reserved **/ - UINT8 Reserved38[50]; + UINT8 Reserved38[35]; + +/** Offset 0x07BA - Command Pins Mapping + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. +**/ + UINT8 Lp5CccConfig; + +/** Offset 0x07BB - Reserved +**/ + UINT8 Reserved39[14]; /** Offset 0x07C9 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -891,7 +901,7 @@ typedef struct { /** Offset 0x07CA - Reserved **/ - UINT8 Reserved39; + UINT8 Reserved40; /** Offset 0x07CB - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 @@ -901,7 +911,7 @@ typedef struct { /** Offset 0x07CC - Reserved **/ - UINT8 Reserved40[129]; + UINT8 Reserved41[129]; /** Offset 0x084D - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check @@ -911,7 +921,7 @@ typedef struct { /** Offset 0x084E - Reserved **/ - UINT8 Reserved41[292]; + UINT8 Reserved42[292]; /** Offset 0x0972 - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode @@ -922,7 +932,7 @@ typedef struct { /** Offset 0x0973 - Reserved **/ - UINT8 Reserved42[183]; + UINT8 Reserved43[183]; /** Offset 0x0A2A - GPIO Override Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings @@ -933,7 +943,7 @@ typedef struct { /** Offset 0x0A2B - Reserved **/ - UINT8 Reserved43[349]; + UINT8 Reserved44[349]; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index 685eeeb6c4..e78311cec9 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -723,9 +723,9 @@ typedef struct { /** Offset 0x0A70 - Reserved **/ - UINT8 Reserved41[113]; + UINT8 Reserved41[89]; -/** Offset 0x0AE1 - Enable PS_ON. +/** Offset 0x0AC9 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -733,29 +733,29 @@ typedef struct { **/ UINT8 PsOnEnable; -/** Offset 0x0AE2 - Reserved +/** Offset 0x0ACA - Reserved **/ UINT8 Reserved42[310]; -/** Offset 0x0C18 - RpPtmBytes +/** Offset 0x0C00 - RpPtmBytes **/ UINT8 RpPtmBytes[4]; -/** Offset 0x0C1C - Reserved +/** Offset 0x0C04 - Reserved **/ UINT8 Reserved43[99]; -/** Offset 0x0C7F - Enable/Disable IGFX PmSupport +/** Offset 0x0C67 - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x0C80 - Reserved +/** Offset 0x0C68 - Reserved **/ UINT8 Reserved44; -/** Offset 0x0C81 - GT Frequency Limit +/** Offset 0x0C69 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -769,22 +769,22 @@ typedef struct { **/ UINT8 GtFreqMax; -/** Offset 0x0C82 - Reserved +/** Offset 0x0C6A - Reserved **/ UINT8 Reserved45[24]; -/** Offset 0x0C9A - Enable or Disable HWP +/** Offset 0x0C82 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved $EN_DIS **/ UINT8 Hwp; -/** Offset 0x0C9B - Reserved +/** Offset 0x0C83 - Reserved **/ UINT8 Reserved46[8]; -/** Offset 0x0CA3 - TCC Activation Offset +/** Offset 0x0C8B - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is @@ -792,63 +792,63 @@ typedef struct { **/ UINT8 TccActivationOffset; -/** Offset 0x0CA4 - Reserved +/** Offset 0x0C8C - Reserved **/ UINT8 Reserved47[34]; -/** Offset 0x0CC6 - Enable or Disable CPU power states (C-states) +/** Offset 0x0CAE - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x0CC7 - Reserved +/** Offset 0x0CAF - Reserved **/ - UINT8 Reserved48[197]; + UINT8 Reserved48[196]; -/** Offset 0x0D8C - Enable LOCKDOWN SMI +/** Offset 0x0D73 - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x0D8D - Enable LOCKDOWN BIOS Interface +/** Offset 0x0D74 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x0D8E - Unlock all GPIO pads +/** Offset 0x0D75 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x0D8F - Reserved +/** Offset 0x0D76 - Reserved **/ - UINT8 Reserved49; + UINT8 Reserved49[2]; -/** Offset 0x0D90 - PCIE RP Ltr Max Snoop Latency +/** Offset 0x0D78 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 PcieRpLtrMaxSnoopLatency[28]; -/** Offset 0x0DC8 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x0DB0 - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 PcieRpLtrMaxNoSnoopLatency[28]; -/** Offset 0x0E00 - Reserved +/** Offset 0x0DE8 - Reserved **/ UINT8 Reserved50[313]; -/** Offset 0x0F39 - LpmStateEnableMask +/** Offset 0x0F21 - LpmStateEnableMask **/ UINT8 LpmStateEnableMask; -/** Offset 0x0F3A - Reserved +/** Offset 0x0F22 - Reserved **/ - UINT8 Reserved51[766]; + UINT8 Reserved51[702]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -867,11 +867,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x1238 +/** Offset 0x11E0 **/ - UINT8 UnusedUpdSpace48[6]; + UINT8 UnusedUpdSpace45[6]; -/** Offset 0x123E +/** Offset 0x11E6 **/ UINT16 UpdTerminator; } FSPS_UPD; From 11f212b825c1f1fbeaf8e4deb052872182d3fbce Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 12 Nov 2020 20:31:42 +0530 Subject: [PATCH 251/262] mb/intel/adlrvp: Update WWAN GPIO as per latest schematics WWAN_RST#: E10 -> F14 WWAN_PWR_EN: E13-> F21 Change-Id: I7182f384eb7a404dfe623c64e29467b41c6b0bdd Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/47519 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/intel/adlrvp/early_gpio.c | 4 ++-- src/mainboard/intel/adlrvp/gpio.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/adlrvp/early_gpio.c b/src/mainboard/intel/adlrvp/early_gpio.c index d45bf8e067..11938ed883 100644 --- a/src/mainboard/intel/adlrvp/early_gpio.c +++ b/src/mainboard/intel/adlrvp/early_gpio.c @@ -8,9 +8,9 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* WWAN_RST# */ - PAD_CFG_GPO(GPP_E10, 0, PLTRST), + PAD_CFG_GPO(GPP_F14, 0, PLTRST), /* WWAN_PWR_EN */ - PAD_CFG_GPO(GPP_E13, 1, DEEP), + PAD_CFG_GPO(GPP_F21, 1, DEEP), }; void variant_configure_early_gpio_pads(void) diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index f91b94faf4..039a437a1a 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -53,9 +53,9 @@ static const struct pad_config gpio_table[] = { /* WWAN_DISABLE_N */ PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* WWAN_RST# */ - PAD_CFG_GPO(GPP_E10, 1, PLTRST), + PAD_CFG_GPO(GPP_F14, 1, PLTRST), /* WWAN_PWR_EN */ - PAD_CFG_GPO(GPP_E13, 1, DEEP), + PAD_CFG_GPO(GPP_F21, 1, DEEP), /* WWAN_PERST# */ PAD_CFG_GPO(GPP_C5, 1, PLTRST), /* PEG_SLOT_WAKE_N */ From 89e83b76b4d50d0977345becf504a1afa0668211 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 12 Nov 2020 23:47:30 +0100 Subject: [PATCH 252/262] soc/intel/common/block/acpi: add Kconfig for CPPC entries generation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ieae9f221ffb27cf52cab21a130e18aa3929caea3 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/47540 Reviewed-by: Tim Wawrzynczak Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/acpi/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index ff59172f3b..d9a7a87859 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -4,3 +4,12 @@ config SOC_INTEL_COMMON_BLOCK_ACPI bool help Intel Processor common code for ACPI + +if SOC_INTEL_COMMON_BLOCK_ACPI + +config SOC_INTEL_COMMON_BLOCK_ACPI_CPPC + bool + help + Generate CPPC entries for Intel SpeedShift + +endif From 165893b67be4a116a96b242bf4ee5370ec707b43 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 6 Nov 2020 12:15:41 +0100 Subject: [PATCH 253/262] soc/intel/xeon_sp: Change the return type of get_iio_stack_info() The somewhat unrelated return value makes the function harder to understand and the return type is not consistently used. Use a different helper function to get the HOB Pci64BitResourceAllocation data. Change-Id: I9a03cbb0ebbb48cc052d4c082d359c0087aaeb3e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47298 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/soc/intel/xeon_sp/chip_common.c | 11 +++++++++-- src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h | 2 +- src/soc/intel/xeon_sp/cpx/soc_util.c | 4 +--- src/soc/intel/xeon_sp/skx/include/soc/soc_util.h | 2 +- src/soc/intel/xeon_sp/skx/soc_util.c | 4 +--- 5 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 5c78780656..47d8f5cc80 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -403,6 +403,13 @@ static void assign_stack_resources(struct iiostack_resource *stack_list, } } +static uint8_t is_pci64bit_alloc(void) +{ + const IIO_UDS *hob = get_iio_uds(); + + return hob->PlatformData.Pci64BitResourceAllocation; +} + static void xeonsp_pci_domain_read_resources(struct device *dev) { struct bus *link; @@ -425,8 +432,8 @@ static void xeonsp_pci_domain_read_resources(struct device *dev) xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL); struct iiostack_resource stack_info = {0}; - uint8_t pci64bit_alloc_flag = get_iiostack_info(&stack_info); - if (!pci64bit_alloc_flag) { + get_iiostack_info(&stack_info); + if (!is_pci64bit_alloc()) { /* * Split 32 bit address space between prefetchable and * non-prefetchable windows diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 649e6b5004..e3c971d49f 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -11,7 +11,7 @@ struct iiostack_resource { STACK_RES res[MAX_SOCKET * MAX_LOGIC_IIO_STACK]; }; -uint8_t get_iiostack_info(struct iiostack_resource *info); +void get_iiostack_info(struct iiostack_resource *info); const struct SystemMemoryMapHob *get_system_memory_map(void); diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index d2d12d1eba..242fcfe4f2 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -27,7 +27,7 @@ const struct SystemMemoryMapHob *get_system_memory_map(void) return *memmap_addr; } -uint8_t get_iiostack_info(struct iiostack_resource *info) +void get_iiostack_info(struct iiostack_resource *info) { const IIO_UDS *hob = get_iio_uds(); @@ -42,8 +42,6 @@ uint8_t get_iiostack_info(struct iiostack_resource *info) } } } - - return hob->PlatformData.Pci64BitResourceAllocation; } uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index b42aec0976..0f528110dd 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -11,7 +11,7 @@ struct iiostack_resource { STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; }; -uint8_t get_iiostack_info(struct iiostack_resource *info); +void get_iiostack_info(struct iiostack_resource *info); void config_reset_cpl3_csrs(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index af6dfcc341..d5e1ae13f4 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -55,7 +55,7 @@ const struct SystemMemoryMapHob *get_system_memory_map(void) return memmap_addr; } -uint8_t get_iiostack_info(struct iiostack_resource *info) +void get_iiostack_info(struct iiostack_resource *info) { const IIO_UDS *hob = get_iio_uds(); @@ -71,8 +71,6 @@ uint8_t get_iiostack_info(struct iiostack_resource *info) memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); } } - - return hob->PlatformData.Pci64BitResourceAllocation; } uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) From 6408ada4a20ca2811de8a158d0579b421f56d8fe Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 12 Nov 2020 17:33:00 +0100 Subject: [PATCH 254/262] soc/intel/xeon_sp: move get_iiostack_info() to a common place All this function does is looping over IIO stacks in the FSP HOB. The only 'SOC/FSP specific' thing is the way to detect if the stack is an IIO stack so add a callback to determine this. Change-Id: I4fa9c54d50279213a4174186a23c3cc156e21c9a Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47522 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- .../intel/xeon_sp/cpx/include/soc/soc_util.h | 7 ------- src/soc/intel/xeon_sp/cpx/soc_acpi.c | 1 + src/soc/intel/xeon_sp/cpx/soc_util.c | 16 ++-------------- src/soc/intel/xeon_sp/include/soc/util.h | 8 ++++++++ .../intel/xeon_sp/skx/include/soc/soc_util.h | 7 ------- src/soc/intel/xeon_sp/skx/soc_util.c | 18 +++--------------- src/soc/intel/xeon_sp/util.c | 17 +++++++++++++++++ 7 files changed, 31 insertions(+), 43 deletions(-) diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index e3c971d49f..5ce392863c 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -6,13 +6,6 @@ #include #include -struct iiostack_resource { - uint8_t no_of_stacks; - STACK_RES res[MAX_SOCKET * MAX_LOGIC_IIO_STACK]; -}; - -void get_iiostack_info(struct iiostack_resource *info); - const struct SystemMemoryMapHob *get_system_memory_map(void); uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index c35c2482f4..599ccff03d 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -16,6 +16,7 @@ #include #include #include +#include /* TODO: Check if the common/acpi weak function can be used */ unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 242fcfe4f2..578f67cda2 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -27,21 +27,9 @@ const struct SystemMemoryMapHob *get_system_memory_map(void) return *memmap_addr; } -void get_iiostack_info(struct iiostack_resource *info) +bool is_iio_stack_res(const STACK_RES *res) { - const IIO_UDS *hob = get_iio_uds(); - - // copy IIO Stack info from FSP HOB - info->no_of_stacks = 0; - for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { - for (int x = 0; x < MAX_IIO_STACK; ++x) { - const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; - if (ri->Personality == TYPE_UBOX_IIO) { - assert(info->no_of_stacks < ARRAY_SIZE(info->res)); - memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); - } - } - } + return res->Personality == TYPE_UBOX_IIO; } uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 014b238165..fc0dee7aba 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -17,4 +17,12 @@ unsigned int soc_get_num_cpus(void); void xeonsp_init_cpu_config(void); void set_bios_init_completion(void); +struct iiostack_resource { + uint8_t no_of_stacks; + STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; +}; + +void get_iiostack_info(struct iiostack_resource *info); +bool is_iio_stack_res(const STACK_RES *res); + #endif diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 0f528110dd..526f5a6a3c 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -6,13 +6,6 @@ #include #include -struct iiostack_resource { - uint8_t no_of_stacks; - STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; -}; - -void get_iiostack_info(struct iiostack_resource *info); - void config_reset_cpl3_csrs(void); const struct SystemMemoryMapHob *get_system_memory_map(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index d5e1ae13f4..7d95ae8600 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -55,22 +55,10 @@ const struct SystemMemoryMapHob *get_system_memory_map(void) return memmap_addr; } -void get_iiostack_info(struct iiostack_resource *info) +bool is_iio_stack_res(const STACK_RES *res) { - const IIO_UDS *hob = get_iio_uds(); - - // copy IIO Stack info from FSP HOB - info->no_of_stacks = 0; - for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { - for (int x = 0; x < MAX_IIO_STACK; ++x) { - const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; - // TODO: do we have situation with only bux 0 and one stack? - if (ri->BusBase >= ri->BusLimit) - continue; - assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK)); - memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); - } - } + // TODO: do we have situation with only bux 0 and one stack? + return res->BusBase < res->BusLimit; } uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 310421566c..b4f7eaab3c 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -119,6 +119,23 @@ const IIO_UDS *get_iio_uds(void) return hob; } +void get_iiostack_info(struct iiostack_resource *info) +{ + const IIO_UDS *hob = get_iio_uds(); + + // copy IIO Stack info from FSP HOB + info->no_of_stacks = 0; + for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { + for (int x = 0; x < MAX_IIO_STACK; ++x) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; + if (!is_iio_stack_res(ri)) + continue; + assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK)); + memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); + } + } +} + unsigned int soc_get_num_cpus(void) { /* The FSP IIO UDS HOB has field numCpus, it is actually socket count */ From 7598b4b40bf0f68dd63d8cd7506e36671436ab8f Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 6 Nov 2020 12:33:35 +0100 Subject: [PATCH 255/262] soc/intel/xeon_sp/acpi.c Loop over HOB stack for MADT generation To align MADT generation with DMAR, we loop over HOB entries instead of over copied HOB entries fetched from get_iio_stacks(). This makes it easier to see what is going on. Tested on ocp/deltalake Change-Id: I8ffe0322bb182b7ec5887354ec801e1f9f3d3288 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47300 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/soc/intel/xeon_sp/acpi.c | 54 +++++++++++++++++++----------------- 1 file changed, 29 insertions(+), 25 deletions(-) diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 5a77bf3b02..f747f872ea 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -73,12 +73,12 @@ static unsigned long acpi_madt_irq_overrides(unsigned long current) return current; } -static unsigned long add_madt_ioapic(unsigned long current, int stack, int ioapic_id, - uint32_t ioapic_base, int gsi_base) +static unsigned long add_madt_ioapic(unsigned long current, int socket, int stack, + int ioapic_id, uint32_t ioapic_base, int gsi_base) { - printk(BIOS_DEBUG, "Adding MADT IOAPIC for stack: %d, ioapic_id: 0x%x, " + printk(BIOS_DEBUG, "Adding MADT IOAPIC for socket: %d, stack: %d, ioapic_id: 0x%x, " "ioapic_base: 0x%x, gsi_base: 0x%x\n", - stack, ioapic_id, ioapic_base, gsi_base); + socket, stack, ioapic_id, ioapic_base, gsi_base); return acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, ioapic_id, ioapic_base, gsi_base); } @@ -86,7 +86,7 @@ static unsigned long add_madt_ioapic(unsigned long current, int stack, int ioapi unsigned long acpi_fill_madt(unsigned long current) { int cur_index; - struct iiostack_resource stack_info = {0}; + const IIO_UDS *hob = get_iio_uds(); /* With XEON-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ #if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) @@ -102,30 +102,34 @@ unsigned long acpi_fill_madt(unsigned long current) current = xeonsp_acpi_create_madt_lapics(current); cur_index = 0; - get_iiostack_info(&stack_info); - for (int stack = 0; stack < stack_info.no_of_stacks; ++stack) { - const STACK_RES *ri = &stack_info.res[stack]; - assert(cur_index < ARRAY_SIZE(ioapic_ids)); - assert(cur_index < ARRAY_SIZE(gsi_bases)); - int ioapic_id = ioapic_ids[cur_index]; - int gsi_base = gsi_bases[cur_index]; - current += add_madt_ioapic(current, stack, ioapic_id, ri->IoApicBase, - gsi_base); - ++cur_index; - - /* - * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. - * Add entry for PCH IOAPIC. - */ - if (stack == 0) { /* PCH IOAPIC */ + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { + const STACK_RES *ri = + &hob->PlatformData.IIO_resource[socket].StackRes[stack]; + if (!is_iio_stack_res(ri)) + continue; assert(cur_index < ARRAY_SIZE(ioapic_ids)); assert(cur_index < ARRAY_SIZE(gsi_bases)); - ioapic_id = ioapic_ids[cur_index]; - gsi_base = gsi_bases[cur_index]; - current += add_madt_ioapic(current, stack, ioapic_id, - ri->IoApicBase + 0x1000, gsi_base); + int ioapic_id = ioapic_ids[cur_index]; + int gsi_base = gsi_bases[cur_index]; + current += add_madt_ioapic(current, socket, stack, ioapic_id, + ri->IoApicBase, gsi_base); ++cur_index; + + /* + * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. + * Add entry for PCH IOAPIC. + */ + if (stack == 0 && socket == 0) { /* PCH IOAPIC */ + assert(cur_index < ARRAY_SIZE(ioapic_ids)); + assert(cur_index < ARRAY_SIZE(gsi_bases)); + ioapic_id = ioapic_ids[cur_index]; + gsi_base = gsi_bases[cur_index]; + current += add_madt_ioapic(current, socket, stack, ioapic_id, + ri->IoApicBase + 0x1000, gsi_base); + ++cur_index; + } } } From 99b38a9c2fb3bbf52ad254bfcabc80c2d19d3185 Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Thu, 19 Dec 2019 23:12:58 -0800 Subject: [PATCH 256/262] soc/intel/tigerlake: Add code for early tcss In order for USB Type-C idisplays to be detected prior to loading Kernel PMC IPC driver is needed to communicate with PMC in order to correctly set the USB Mux settings. This patch is adding in support for early detection of both Displays. BUG=b:151731851 BRANCH=NONE TEST=built and verified that TCSS MUX is being set on Volteer Change-Id: I58e66f21210d565fb8145d140d2fc7febecdd21a Signed-off-by: Brandon Breitenstein Reviewed-on: https://review.coreboot.org/c/coreboot/+/42079 Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/Kconfig | 7 + src/soc/intel/tigerlake/Makefile.inc | 1 + src/soc/intel/tigerlake/early_tcss.c | 271 ++++++++++++++++++ src/soc/intel/tigerlake/fsp_params.c | 6 + .../intel/tigerlake/include/soc/early_tcss.h | 139 +++++++++ 5 files changed, 424 insertions(+) create mode 100644 src/soc/intel/tigerlake/early_tcss.c create mode 100644 src/soc/intel/tigerlake/include/soc/early_tcss.h diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index f1ac774cd0..507f87100d 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -232,4 +232,11 @@ config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x2000 + +config EARLY_TCSS_DISPLAY + bool "Enable early TCSS display" + depends on RUN_FSP_GOP + help + Enable displays to be detected over Type-C ports during boot. + endif diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 3103d60d3b..4a41812324 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -31,6 +31,7 @@ romstage-y += reset.c ramstage-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c +ramstage-$(CONFIG_EARLY_TCSS_DISPLAY) += early_tcss.c ramstage-y += elog.c ramstage-y += espi.c ramstage-y += finalize.c diff --git a/src/soc/intel/tigerlake/early_tcss.c b/src/soc/intel/tigerlake/early_tcss.c new file mode 100644 index 0000000000..3944f61843 --- /dev/null +++ b/src/soc/intel/tigerlake/early_tcss.c @@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include + + +static uint32_t tcss_make_conn_cmd(int u, int u3, int u2, int ufp, int hsl, + int sbu, int acc) +{ + return TCSS_CD_FIELD(USAGE, u) | + TCSS_CD_FIELD(USB3, u3) | + TCSS_CD_FIELD(USB2, u2) | + TCSS_CD_FIELD(UFP, ufp) | + TCSS_CD_FIELD(HSL, hsl) | + TCSS_CD_FIELD(SBU, sbu) | + TCSS_CD_FIELD(ACC, acc); +} + +static uint32_t tcss_make_alt_mode_cmd_buf_0(int u, int u3, int m) +{ + return TCSS_ALT_FIELD(USAGE, u) | + TCSS_ALT_FIELD(USB3, u3) | + TCSS_ALT_FIELD(MODE, m); + +} + +static uint32_t tcss_make_alt_mode_cmd_buf_1(int p, int c, int ufp, int dp) +{ + return TCSS_ALT_FIELD(POLARITY, p) | + TCSS_ALT_FIELD(CABLE, c) | + TCSS_ALT_FIELD(UFP, ufp) | + TCSS_ALT_FIELD(DP_MODE, dp); +} + +static uint32_t tcss_make_safe_mode_cmd(int u, int u3) +{ + return TCSS_CD_FIELD(USAGE, u) | + TCSS_CD_FIELD(USB3, u3); +} + + +static uint32_t tcss_make_hpd_mode_cmd(int u, int u3, int hpd_lvl, int hpd_irq) +{ + return TCSS_HPD_FIELD(USAGE, u) | + TCSS_HPD_FIELD(USB3, u3) | + TCSS_HPD_FIELD(LVL, hpd_lvl) | + TCSS_HPD_FIELD(IRQ, hpd_irq); + +} + +static int send_pmc_req(int cmd_type, const struct pmc_ipc_buffer *req, + struct pmc_ipc_buffer *res, uint32_t size) +{ + + uint32_t cmd_reg; + uint32_t res_reg; + int tries = 2; + int r; + + cmd_reg = pmc_make_ipc_cmd(PMC_IPC_USBC_CMD_ID, PMC_IPC_USBC_SUBCMD_ID, + size); + + printk(BIOS_DEBUG, "Raw Buffer output 0 %08" PRIx32 "\n", req->buf[0]); + printk(BIOS_DEBUG, "Raw Buffer output 1 %08" PRIx32 "\n", req->buf[1]); + + do { + r = pmc_send_ipc_cmd(cmd_reg, req, res); + if (r < 0) { + printk(BIOS_ERR, "pmc_send_ipc_cmd failed\n"); + return -1; + } + + res_reg = res->buf[0]; + if (cmd_type == CONNECT_REQ) { + if (!TCSS_CONN_STATUS_HAS_FAILED(res_reg)) { + printk(BIOS_DEBUG, "pmc_send_ipc_cmd succeeded\n"); + return 0; + } + + if (TCSS_CONN_STATUS_IS_FATAL(res_reg)) { + printk(BIOS_ERR, "pmc_send_ipc_cmd status: fatal\n"); + return -1; + } + } else { + if (!TCSS_STATUS_HAS_FAILED(res_reg)) { + printk(BIOS_DEBUG, "pmc_send_ipc_cmd succeeded\n"); + return 0; + } + + if (TCSS_STATUS_IS_FATAL(res_reg)) { + printk(BIOS_ERR, "pmc_send_ipc_cmd status: fatal\n"); + return -1; + } + } + } while (--tries >= 0); + + printk(BIOS_ERR, "pmc_send_ipc_cmd failed after retries\n"); + return -1; +} + +static int send_pmc_connect_request(int port, struct tcss_mux mux_data, + struct pmc_ipc_buffer *res) +{ + uint32_t cmd; + struct pmc_ipc_buffer req = { 0 }; + + cmd = tcss_make_conn_cmd( + PMC_IPC_TCSS_CONN_REQ_RES, + mux_data.usb3_port, + mux_data.usb2_port, + mux_data.ufp, + mux_data.polarity, + mux_data.polarity, + mux_data.acc); + + req.buf[0] = cmd; + + printk(BIOS_DEBUG, "port C%d CONN req: usage %d usb3 %d usb2 %d " + "ufp %d ori_hsl %d ori_sbu %d dbg_acc %d\n", + port, + GET_TCSS_CD_FIELD(USAGE, cmd), + GET_TCSS_CD_FIELD(USB3, cmd), + GET_TCSS_CD_FIELD(USB2, cmd), + GET_TCSS_CD_FIELD(UFP, cmd), + GET_TCSS_CD_FIELD(HSL, cmd), + GET_TCSS_CD_FIELD(SBU, cmd), + GET_TCSS_CD_FIELD(ACC, cmd)); + + return send_pmc_req(CONNECT_REQ, &req, res, PMC_IPC_CONN_REQ_SIZE); +} + +static int send_pmc_safe_mode_request(int port, struct tcss_mux mux_data, + struct pmc_ipc_buffer *res) +{ + uint32_t cmd; + struct pmc_ipc_buffer req = { 0 }; + + cmd = tcss_make_safe_mode_cmd(PMC_IPC_TCSS_SAFE_MODE_REQ_RES, mux_data.usb3_port); + + req.buf[0] = cmd; + + printk(BIOS_DEBUG, "port C%d SAFE req: usage %d usb3 %d\n", + port, + GET_TCSS_CD_FIELD(USAGE, cmd), + GET_TCSS_CD_FIELD(USB3, cmd)); + + return send_pmc_req(SAFE_REQ, &req, res, PMC_IPC_SAFE_REQ_SIZE); +} + +static int send_pmc_dp_hpd_request(int port, struct tcss_mux mux_data) +{ + struct pmc_ipc_buffer *res = NULL; + struct pmc_ipc_buffer req = { 0 }; + uint32_t cmd; + + cmd = tcss_make_hpd_mode_cmd( + PMC_IPC_TCSS_HPD_REQ_RES, + mux_data.usb3_port, + mux_data.hpd_lvl, + mux_data.hpd_irq); + + req.buf[0] = cmd; + + return send_pmc_req(HPD_REQ, &req, res, PMC_IPC_HPD_REQ_SIZE); + +} + +static int send_pmc_dp_mode_request(int port, struct tcss_mux mux_data, + struct pmc_ipc_buffer *res) +{ + uint32_t cmd; + uint8_t dp_mode; + int ret; + + struct pmc_ipc_buffer req = { 0 }; + + cmd = tcss_make_alt_mode_cmd_buf_0( + PMC_IPC_TCSS_ALTMODE_REQ_RES, + mux_data.usb3_port, + PMC_IPC_DP_MODE); + + req.buf[0] = cmd; + + printk(BIOS_DEBUG, "port C%d ALT_1 req: usage %d usb3 %d dp_mode %d\n", + port, + GET_TCSS_ALT_FIELD(USAGE, cmd), + GET_TCSS_ALT_FIELD(USB3, cmd), + GET_TCSS_ALT_FIELD(MODE, cmd)); + + switch (mux_data.dp_mode) { + case MODE_DP_PIN_A: + dp_mode = 1; + break; + case MODE_DP_PIN_B: + dp_mode = 2; + break; + case MODE_DP_PIN_C: + dp_mode = 3; + break; + case MODE_DP_PIN_D: + dp_mode = 4; + break; + case MODE_DP_PIN_E: + dp_mode = 5; + break; + case MODE_DP_PIN_F: + dp_mode = 6; + break; + default: + dp_mode = 0; + break; + } + + cmd = tcss_make_alt_mode_cmd_buf_1( + mux_data.polarity, + mux_data.cable, + 0, /* ufp is not supported in DP ALT Mode request */ + dp_mode); + + printk(BIOS_DEBUG, "port C%d ALT_2 req: polarity %d cable %d ufp %d " + "dp_mode %d\n", + port, + GET_TCSS_ALT_FIELD(POLARITY, cmd), + GET_TCSS_ALT_FIELD(CABLE, cmd), + GET_TCSS_ALT_FIELD(UFP, cmd), + GET_TCSS_ALT_FIELD(DP_MODE, cmd)); + + req.buf[1] = cmd; + + ret = send_pmc_req(DP_REQ, &req, res, PMC_IPC_ALT_REQ_SIZE); + if (ret) + return ret; + + send_pmc_dp_hpd_request(port, mux_data); + return 0; +} + +void update_tcss_mux(int port, struct tcss_mux mux_data) +{ + struct pmc_ipc_buffer *rbuf = NULL; + int ret = 0; + + /* check if mux has a DP device */ + if (mux_data.dp) { + ret = send_pmc_connect_request(port, mux_data, rbuf); + if (ret) { + printk(BIOS_ERR, "Port %d connect request failed\n", port); + return; + } + ret = send_pmc_safe_mode_request(port, mux_data, rbuf); + if (ret) { + printk(BIOS_ERR, "Port %d safe mode request failed\n", port); + return; + } + + ret = send_pmc_dp_mode_request(port, mux_data, rbuf); + } + + if (ret) + printk(BIOS_ERR, "Port C%d mux set failed with error %d\n", port, ret); +} + +__weak void mainboard_early_tcss_enable(void) +{ + /* to be overwritten by each mainboard that needs early tcss */ +} diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 3427a61792..6de098aa3e 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -384,6 +385,11 @@ void platform_fsp_multi_phase_init_cb(uint32_t phase_index) switch (phase_index) { case 1: /* TCSS specific initialization here */ + printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", + __FILE__, __func__); + if (CONFIG(EARLY_TCSS_DISPLAY) && (vboot_recovery_mode_enabled() || + vboot_developer_mode_enabled())) + mainboard_early_tcss_enable(); break; default: break; diff --git a/src/soc/intel/tigerlake/include/soc/early_tcss.h b/src/soc/intel/tigerlake/include/soc/early_tcss.h new file mode 100644 index 0000000000..c009e8432c --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/early_tcss.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* PMC IPC related offsets and commands */ +#define PMC_IPC_USBC_CMD_ID 0xA7 +#define PMC_IPC_USBC_SUBCMD_ID 0x0 +#define PMC_IPC_CMD 0x0 +#define PMC_IPC_TCSS_CONN_REQ_RES 0x0 +#define PMC_IPC_TCSS_SAFE_MODE_REQ_RES 0x2 +#define PMC_IPC_TCSS_ALTMODE_REQ_RES 0x3 +#define PMC_IPC_TCSS_HPD_REQ_RES 0x4 +#define PMC_IPC_CONN_REQ_SIZE 2 +#define PMC_IPC_ALT_REQ_SIZE 8 +#define PMC_IPC_SAFE_REQ_SIZE 1 +#define PMC_IPC_HPD_REQ_SIZE 2 +#define PMC_IPC_DP_MODE 1 + +#define TCSS_CD_USAGE_SHIFT 0 +#define TCSS_CD_USAGE_MASK 0x0f +#define TCSS_CD_USB3_SHIFT 4 +#define TCSS_CD_USB3_MASK 0x0f +#define TCSS_CD_USB2_SHIFT 8 +#define TCSS_CD_USB2_MASK 0x0f +#define TCSS_CD_UFP_SHIFT 12 +#define TCSS_CD_UFP_MASK 0x01 +#define TCSS_CD_HSL_SHIFT 13 +#define TCSS_CD_HSL_MASK 0x01 +#define TCSS_CD_SBU_SHIFT 14 +#define TCSS_CD_SBU_MASK 0x01 +#define TCSS_CD_ACC_SHIFT 15 +#define TCSS_CD_ACC_MASK 0x01 +#define TCSS_CD_FAILED_SHIFT 16 +#define TCSS_CD_FAILED_MASK 0x01 +#define TCSS_CD_FATAL_SHIFT 17 +#define TCSS_CD_FATAL_MASK 0x01 + +#define TCSS_ALT_USAGE_SHIFT 0 +#define TCSS_ALT_USAGE_MASK 0x0f +#define TCSS_ALT_USB3_SHIFT 4 +#define TCSS_ALT_USB3_MASK 0x0f +#define TCSS_ALT_MODE_SHIFT 12 +#define TCSS_ALT_MODE_MASK 0x0f +#define TCSS_ALT_POLARITY_SHIFT 1 +#define TCSS_ALT_POLARITY_MASK 0x01 +#define TCSS_ALT_CABLE_SHIFT 2 +#define TCSS_ALT_CABLE_MASK 0x01 +#define TCSS_ALT_UFP_SHIFT 3 +#define TCSS_ALT_UFP_MASK 0x01 +#define TCSS_ALT_DP_MODE_SHIFT 8 +#define TCSS_ALT_DP_MODE_MASK 0x0f +#define TCSS_ALT_FAILED_SHIFT 8 +#define TCSS_ALT_FAILED_MASK 0x01 +#define TCSS_ALT_FATAL_SHIFT 9 +#define TCSS_ALT_FATAL_MASK 0x01 + +#define TCSS_HPD_USAGE_SHIFT 0 +#define TCSS_HPD_USAGE_MASK 0x0f +#define TCSS_HPD_USB3_SHIFT 4 +#define TCSS_HPD_USB3_MASK 0x0f +#define TCSS_HPD_LVL_SHIFT 12 +#define TCSS_HPD_LVL_MASK 0x01 +#define TCSS_HPD_IRQ_SHIFT 13 +#define TCSS_HPD_IRQ_MASK 0x01 + +#define TCSS_CD_FIELD(name, val) \ + (((val) & TCSS_CD_##name##_MASK) << TCSS_CD_##name##_SHIFT) + +#define GET_TCSS_CD_FIELD(name, val) \ + (((val) >> TCSS_CD_##name##_SHIFT) & TCSS_CD_##name##_MASK) + + +#define TCSS_ALT_FIELD(name, val) \ + (((val) & TCSS_ALT_##name##_MASK) << TCSS_ALT_##name##_SHIFT) + +#define TCSS_HPD_FIELD(name, val) \ + (((val) & TCSS_HPD_##name##_MASK) << TCSS_HPD_##name##_SHIFT) + +#define GET_TCSS_ALT_FIELD(name, val) \ + (((val) >> TCSS_ALT_##name##_SHIFT) & TCSS_ALT_##name##_MASK) + +#define TCSS_CONN_STATUS_HAS_FAILED(s) GET_TCSS_CD_FIELD(FAILED, s) +#define TCSS_STATUS_HAS_FAILED(s) GET_TCSS_ALT_FIELD(FAILED, s) +/* !fatal means retry */ +#define TCSS_CONN_STATUS_IS_FATAL(s) GET_TCSS_CD_FIELD(FATAL, s) +#define TCSS_STATUS_IS_FATAL(s) GET_TCSS_ALT_FIELD(FATAL, s) + +#define USB_2_PORT_MASK 0x0f +#define USB_3_PORT_MASK 0xf0 + +/* TCSS connection modes for PMC */ +enum pmc_ipc_conn_mode { + PMC_IPC_TCSS_DISCONNECT_MODE, + PMC_IPC_TCSS_USB_MODE, + PMC_IPC_TCSS_ALTERNATE_MODE, + PMC_IPC_TCSS_SAFE_MODE, + PMC_IPC_TCSS_HPD_MODE, + PMC_IPC_TCSS_TOTAL_MODES, +}; + +enum pmc_ipc_command_type { + CONNECT_REQ, + SAFE_REQ, + DP_REQ, + HPD_REQ, +}; + +/* DP Mode pin definitions */ +#define MODE_DP_PIN_A BIT(0) +#define MODE_DP_PIN_B BIT(1) +#define MODE_DP_PIN_C BIT(2) +#define MODE_DP_PIN_D BIT(3) +#define MODE_DP_PIN_E BIT(4) +#define MODE_DP_PIN_F BIT(5) + +/* struct to hold all tcss_mux related variables */ +struct tcss_mux { + bool dp; /* DP connected */ + bool usb; /* USB connected */ + bool cable; /* Activ/Passive Cable */ + bool polarity; /* polarity of connected device */ + bool hpd_lvl; /* HPD Level assert */ + bool hpd_irq; /* HPD IRQ assert */ + bool ufp; + bool acc; + uint8_t dp_mode; /* DP Operation Mode */ + uint8_t usb3_port; /* USB2 Port Number */ + uint8_t usb2_port; /* USB3 Port Number */ +}; + +void update_tcss_mux(int port, struct tcss_mux mux_data); + +/* + * Weak mainboard method to setup any mux configuration needed for early TCSS operations. + * This function will need to obtain any mux data needed to forward to IOM/PMC and call + * the update_tcss_mux method which will call any PMC commands needed to connect the + * ports. Since the mux data may be stored differently by different mainboards this + * must be overridden by the mainboard with its specific mux data stored in a struct tcss_mux + * struct as defined above. + */ +void mainboard_early_tcss_enable(void); From 50a1072180f05c20ec13d521af6f8930ceabb2c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 4 Nov 2020 00:19:28 +0100 Subject: [PATCH 257/262] soc/intel/cnl: replace the remains of HeciEnabled by device state in dt MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The option `HeciEnabled` was partly replaced by use of the device on/off state in the devicetree in commit 3de90d1. The option has been removed from the corresponding boards, so `HeciEnabled` is always 0 and ME always gets disabled during soc finalize, when `HECI_DISABLE_USING_SMM` is set. Replace the option in the finalize function by the same dt state check that sets the FSP option and drop the remaints of `HeciEnabled`. Devicetrees still having `HeciEnabled` have been adapted to keep the current behaviour. Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/47195 Reviewed-by: Nico Huber Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- .../google/hatch/variants/ambassador/overridetree.cb | 4 +--- .../google/hatch/variants/genesis/overridetree.cb | 4 +--- src/mainboard/prodrive/hermes/devicetree.cb | 4 +--- .../siemens/chili/variants/base/devicetree.cb | 4 +--- .../siemens/chili/variants/chili/devicetree.cb | 4 +--- src/soc/intel/cannonlake/chip.h | 3 --- src/soc/intel/cannonlake/smihandler.c | 10 +++++----- 7 files changed, 10 insertions(+), 23 deletions(-) diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb index adb00e485f..835a8aae3a 100644 --- a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb @@ -1,7 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" - # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -370,6 +367,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/hatch/variants/genesis/overridetree.cb b/src/mainboard/google/hatch/variants/genesis/overridetree.cb index adb00e485f..835a8aae3a 100644 --- a/src/mainboard/google/hatch/variants/genesis/overridetree.cb +++ b/src/mainboard/google/hatch/variants/genesis/overridetree.cb @@ -1,7 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" - # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -370,6 +367,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 5615554208..b276919b3f 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -24,9 +24,7 @@ chip soc/intel/cannonlake device pci 14.2 on end # RAM controller device pci 14.5 off end # SDCard - device pci 16.0 on # Management Engine Interface 1 - register "HeciEnabled" = "1" - end + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 on end # Management Engine Interface 2 device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on end # SATA diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index cca88384ff..196cd81359 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -48,9 +48,7 @@ chip soc/intel/cannonlake device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on # Management Engine Interface 1 - register "HeciEnabled" = "1" - end + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index 3c9d968506..6c5a306473 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -100,9 +100,7 @@ chip soc/intel/cannonlake device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on # Management Engine Interface 1 - register "HeciEnabled" = "1" - end + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 2a52627be7..a084f67b46 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -253,9 +253,6 @@ struct soc_intel_cannonlake_config { * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ struct vr_config domain_vr_config[NUM_VR_DOMAINS]; - /* HeciEnabled decides the state of Heci1 at end of boot - * Setting to 0 (default) disables Heci1 and hides the device from OS */ - uint8_t HeciEnabled; /* Enables support for Teton Glacier hybrid storage device */ uint8_t TetonGlacierMode; diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 266c258966..dd8db5b1f5 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include #include #include #include @@ -17,11 +17,11 @@ */ void smihandler_soc_at_finalize(void) { - const struct soc_intel_cannonlake_config *config; + if (!CONFIG(HECI_DISABLE_USING_SMM)) + return; - config = config_of_soc(); - - if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE); + if (!is_dev_enabled(dev)) heci_disable(); } From 0c3845d2ee5e582937f65f488e15055fe49464b0 Mon Sep 17 00:00:00 2001 From: Stanley Wu Date: Thu, 5 Nov 2020 21:10:39 +0800 Subject: [PATCH 258/262] mb/google/volteer/variant/lindar: Update devicetree settings Update I2C address for Goodix touchscreen and add ELAN touchscreen & Synaptics trackpad device. Follow CB:47415 to correct HID over I2C device to be level triggerd. BUG=b:160013582 TEST=emerge-volteer coreboot and check system dmesg and evtest can get device. Change-Id: I070fb0e06b588f128253270502c9c2c427c62b84 Signed-off-by: Stanley Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/47390 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../volteer/variants/lindar/overridetree.cb | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index a318ccaac9..64f5ab9910 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -58,7 +58,19 @@ chip soc/intel/tigerlake register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 14 on end + device i2c 5d on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end end end device ref i2c5 on @@ -70,6 +82,15 @@ chip soc/intel/tigerlake register "probed" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "generic.wake" = "GPE0_DW2_15" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end end device ref north_xhci on chip drivers/usb/acpi From 6615c6eaf798556b94ecc44d241222d6b19cd119 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Tue, 27 Oct 2020 15:58:31 -0700 Subject: [PATCH 259/262] mrc_cache: Move code for triggering memory training into mrc_cache Currently the decision of whether or not to use mrc_cache in recovery mode is made within the individual platforms' drivers (ie: fsp2.0, fsp1.1, etc.). As this is not platform specific, but uses common vboot infrastructure, the code can be unified and moved into mrc_cache. The conditions are as follows: 1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain switch is true) 2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this means that memory training will occur after verified boot, meaning that mrc_cache will be filled with data from executing RW code. So in this case, we never want to use the training data in the mrc_cache for recovery mode. 3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens before verfied boot, meaning that the mrc_cache data is generated by RO code, so it is safe to use for a recovery boot. 4. Any platform that does not use vboot should be unaffected. Additionally, we have removed the MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the mrc_cache driver takes care of invalidating the mrc_cache data for normal mode. If the platform: 1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data 2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set BUG=b:150502246 BRANCH=None TEST=1. run dut-control power_state:rec_force_mrc twice on lazor ensure that memory retraining happens both times run dut-control power_state:rec twice on lazor ensure that memory retraining happens only first time 2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig boot twice to ensure caching of memory training occurred on each boot. Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp1_1/romstage.c | 48 ++++++------- src/drivers/intel/fsp2_0/memory_init.c | 12 ---- src/drivers/mrc_cache/Kconfig | 5 -- src/drivers/mrc_cache/mrc_cache.c | 70 +++++++++++++++---- src/mainboard/google/dedede/Kconfig | 1 - src/mainboard/google/deltaur/Kconfig | 1 - src/mainboard/google/drallion/Kconfig | 1 - src/mainboard/google/eve/Kconfig | 1 - src/mainboard/google/fizz/Kconfig | 1 - src/mainboard/google/hatch/Kconfig | 2 - src/mainboard/google/octopus/Kconfig | 1 - src/mainboard/google/poppy/Kconfig | 1 - src/mainboard/google/reef/Kconfig | 1 - src/mainboard/google/sarien/Kconfig | 1 - src/mainboard/google/volteer/Kconfig | 1 - src/mainboard/intel/adlrvp/Kconfig | 2 - src/mainboard/intel/glkrvp/Kconfig | 1 - src/mainboard/intel/jasperlake_rvp/Kconfig | 1 - src/mainboard/intel/tglrvp/Kconfig | 1 - src/northbridge/intel/haswell/raminit.c | 9 +-- .../intel/sandybridge/raminit_mrc.c | 8 +-- src/soc/intel/broadwell/raminit.c | 38 +++++----- src/soc/qualcomm/sc7180/Kconfig | 1 - 23 files changed, 103 insertions(+), 105 deletions(-) diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 5a59c502a9..5129dc696b 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -41,35 +41,29 @@ static void raminit_common(struct romstage_params *params) params->saved_data_size = 0; params->saved_data = NULL; if (!params->disable_saved_data) { - if (vboot_recovery_mode_enabled()) { - /* Recovery mode does not use MRC cache */ + /* Assume boot device is memory mapped. */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + params->saved_data = NULL; + if (CONFIG(CACHE_MRC_SETTINGS)) + params->saved_data = + mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, + params->fsp_version, + &mrc_size); + if (params->saved_data) { + /* MRC cache found */ + params->saved_data_size = mrc_size; + + } else if (s3wake) { + /* Waking from S3 and no cache. */ printk(BIOS_DEBUG, - "Recovery mode: not using MRC cache.\n"); + "No MRC cache " + "found in S3 resume path.\n"); + post_code(POST_RESUME_FAILURE); + /* FIXME: A "system" reset is likely enough: */ + full_reset(); } else { - /* Assume boot device is memory mapped. */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - - params->saved_data = NULL; - if (CONFIG(CACHE_MRC_SETTINGS)) - params->saved_data = - mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, - params->fsp_version, - &mrc_size); - if (params->saved_data) { - /* MRC cache found */ - params->saved_data_size = mrc_size; - - } else if (s3wake) { - /* Waking from S3 and no cache. */ - printk(BIOS_DEBUG, - "No MRC cache " - "found in S3 resume path.\n"); - post_code(POST_RESUME_FAILURE); - /* FIXME: A "system" reset is likely enough: */ - full_reset(); - } else { - printk(BIOS_DEBUG, "No MRC cache found.\n"); - } + printk(BIOS_DEBUG, "No MRC cache found.\n"); } } diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 68cc1215a5..27e34fef0d 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -92,18 +92,6 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) if (!CONFIG(CACHE_MRC_SETTINGS)) return; - /* - * In recovery mode, force retraining: - * 1. Recovery cache is not supported, or - * 2. Memory retrain switch is set. - */ - if (vboot_recovery_mode_enabled()) { - if (!CONFIG(HAS_RECOVERY_MRC_CACHE)) - return; - if (get_recovery_mode_retrain_switch()) - return; - } - /* Assume boot device is memory mapped. */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig index b09c19672e..df6973b0a4 100644 --- a/src/drivers/mrc_cache/Kconfig +++ b/src/drivers/mrc_cache/Kconfig @@ -17,11 +17,6 @@ config HAS_RECOVERY_MRC_CACHE bool default n -config MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN - bool - depends on VBOOT_STARTS_IN_BOOTBLOCK - default n - config MRC_SETTINGS_VARIABLE_DATA bool default n diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index eb43123c67..8b26ea5905 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -69,7 +69,20 @@ static const struct cache_region normal_training = { .type = MRC_TRAINING_DATA, .elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL, .tpm_hash_index = MRC_RW_HASH_NV_INDEX, +#if CONFIG(VBOOT_STARTS_IN_ROMSTAGE) + /* + * If VBOOT_STARTS_IN_ROMSTAGE is selected, this means that + * memory training happens before vboot (in RO) and the + * mrc_cache data is always safe to use. + */ .flags = NORMAL_FLAG | RECOVERY_FLAG, +#else + /* + * If !VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens after + * vboot (in RW code) and is never safe to use in recovery. + */ + .flags = NORMAL_FLAG, +#endif }; static const struct cache_region variable_data = { @@ -78,7 +91,20 @@ static const struct cache_region variable_data = { .type = MRC_VARIABLE_DATA, .elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE, .tpm_hash_index = 0, +#if CONFIG(VBOOT_STARTS_IN_ROMSTAGE) + /* + * If VBOOT_STARTS_IN_ROMSTAGE is selected, this means that + * memory training happens before vboot (in RO) and the + * mrc_cache data is always safe to use. + */ .flags = NORMAL_FLAG | RECOVERY_FLAG, +#else + /* + * If !VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens after + * vboot (in RW code) and is never safe to use in recovery. + */ + .flags = NORMAL_FLAG, +#endif }; /* Order matters here for priority in matching. */ @@ -255,6 +281,13 @@ static int mrc_cache_find_current(int type, uint32_t version, const size_t md_size = sizeof(*md); const bool fail_bad_data = true; + /* + * In recovery mode, force retraining if the memory retrain + * switch is set. + */ + if (vboot_recovery_mode_enabled() && get_recovery_mode_retrain_switch()) + return -1; + cr = lookup_region(®ion, type); if (cr == NULL) @@ -566,10 +599,24 @@ static void invalidate_normal_cache(void) const char *name = DEFAULT_MRC_CACHE; const uint32_t invalid = ~MRC_DATA_SIGNATURE; - /* Invalidate only on recovery mode with retraining enabled. */ + /* + * If !HAS_RECOVERY_MRC_CACHE and VBOOT_STARTS_IN_ROMSTAGE is + * selected, this means that memory training occurs before + * verified boot (in RO), so normal mode cache does not need + * to be invalidated. + */ + if (!CONFIG(HAS_RECOVERY_MRC_CACHE) && CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) + return; + + /* We only invalidate the normal cache in recovery mode. */ if (!vboot_recovery_mode_enabled()) return; - if (!get_recovery_mode_retrain_switch()) + + /* + * For platforms with a recovery mrc_cache, no need to + * invalidate when retrain switch is not set. + */ + if (CONFIG(HAS_RECOVERY_MRC_CACHE) && !get_recovery_mode_retrain_switch()) return; if (fmap_locate_area_as_rdev_rw(name, &rdev) < 0) { @@ -599,7 +646,7 @@ static void update_mrc_cache_from_cbmem(int type) cr = lookup_region(®ion, type); if (cr == NULL) { - printk(BIOS_ERR, "MRC: could not find cache_region type %d\n", type); + printk(BIOS_INFO, "MRC: could not find cache_region type %d\n", type); return; } @@ -631,8 +678,7 @@ static void finalize_mrc_cache(void *unused) update_mrc_cache_from_cbmem(MRC_VARIABLE_DATA); } - if (CONFIG(MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN)) - invalidate_normal_cache(); + invalidate_normal_cache(); protect_mrc_region(); } @@ -642,13 +688,6 @@ int mrc_cache_stash_data(int type, uint32_t version, const void *data, { const struct cache_region *cr; - cr = lookup_region_type(type); - if (cr == NULL) { - printk(BIOS_ERR, "MRC: failed to add to cbmem for type %d.\n", - type); - return -1; - } - struct mrc_metadata md = { .signature = MRC_DATA_SIGNATURE, .data_size = size, @@ -664,6 +703,13 @@ int mrc_cache_stash_data(int type, uint32_t version, const void *data, size_t cbmem_size; cbmem_size = sizeof(*cbmem_md) + size; + cr = lookup_region_type(type); + if (cr == NULL) { + printk(BIOS_INFO, "MRC: No region type found. Skip adding to cbmem for type %d.\n", + type); + return 0; + } + cbmem_md = cbmem_add(cr->cbmem_id, cbmem_size); if (cbmem_md == NULL) { diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 6da65052cd..891b48acc9 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -47,7 +47,6 @@ config CHROMEOS select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_EARLY_EC_SYNC select VBOOT_LID_SWITCH diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig index dafd593ab6..8d958493bd 100644 --- a/src/mainboard/google/deltaur/Kconfig +++ b/src/mainboard/google/deltaur/Kconfig @@ -90,7 +90,6 @@ config VARIANT_DIR config VBOOT select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH endif # BOARD_GOOGLE_BASEBOARD_DELTAUR diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index d535d141e1..6c90eed9a8 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -93,7 +93,6 @@ config DEVICETREE config VBOOT select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH endif # BOARD_GOOGLE_BASEBOARD_DRALLION diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index 9316c7f213..ece0119a3e 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -28,7 +28,6 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE select VBOOT_LID_SWITCH - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config CHROMEOS select DSAR_ENABLE diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index a21df378ef..e09f853337 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -40,7 +40,6 @@ config OVERRIDE_DEVICETREE config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config DRIVER_TPM_SPI_BUS default 0x1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 4d7d5ec990..12e56384bd 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -54,7 +54,6 @@ config CHROMEOS select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU @@ -183,7 +182,6 @@ config VARIANT_DIR config VBOOT select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_EARLY_EC_SYNC config USE_PM_ACPI_TIMER diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index b9c6a1ba34..588c8ed331 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -46,7 +46,6 @@ config CHROMEOS default y select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH config MAINBOARD_DIR diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index d8b90bcdc3..2656d28173 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -208,7 +208,6 @@ config VARIANT_SPECIFIC_OPTIONS_SORAKA config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH config UART_FOR_CONSOLE diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 76a864062f..9744d74738 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -43,7 +43,6 @@ config TPM_TIS_ACPI_INTERRUPT config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH if BASEBOARD_REEF_LAPTOP config MAINBOARD_DIR diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 5b580724bb..9b0d25158c 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -94,7 +94,6 @@ config DEVICETREE config VBOOT select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH endif # BOARD_GOOGLE_BASEBOARD_SARIEN diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index a5cc1966dc..07a5fde7a1 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -45,7 +45,6 @@ config CHROMEOS select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH select VBOOT_EARLY_EC_SYNC diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 57b0524ce3..b6d3ff3cdb 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -25,7 +25,6 @@ config CHROMEOS select GBB_FLAG_FORCE_MANUAL_RECOVERY select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config MAINBOARD_DIR string @@ -82,7 +81,6 @@ config VBOOT select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config UART_FOR_CONSOLE int diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig index 7b1b564e52..172dfa2e97 100644 --- a/src/mainboard/intel/glkrvp/Kconfig +++ b/src/mainboard/intel/glkrvp/Kconfig @@ -45,7 +45,6 @@ config CHROMEOS config VBOOT select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select EC_GOOGLE_CHROMEEC_SWITCHES if GLK_CHROME_EC config MAINBOARD_DIR diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index 1125a9b7f2..7bfd15878c 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -59,7 +59,6 @@ config CHROMEOS select GBB_FLAG_FORCE_MANUAL_RECOVERY select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config VBOOT select VBOOT_LID_SWITCH diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 4d43e23454..9df542dfa6 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -31,7 +31,6 @@ config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES if TGL_CHROME_EC select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB select VBOOT_EARLY_EC_SYNC diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 63d70f792f..290e402fcb 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -112,10 +112,11 @@ void sdram_initialize(struct pei_data *pei_data) printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); - /* Do not pass MRC data in for recovery mode boot, always pass it in for S3 resume */ - if (!(CONFIG(HASWELL_VBOOT_IN_BOOTBLOCK) && vboot_recovery_mode_enabled()) - || pei_data->boot_mode == 2) - prepare_mrc_cache(pei_data); + /* + * Always pass in mrc_cache data. The driver will determine + * whether to use the data or not. + */ + prepare_mrc_cache(pei_data); /* If MRC data is not found, we cannot continue S3 resume */ if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 444ecf8cc7..8df7d1b36a 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -133,12 +133,10 @@ void sdram_initialize(struct pei_data *pei_data) printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); /* - * Do not pass MRC data in for recovery mode boot, - * Always pass it in for S3 resume. + * Always pass in mrc_cache data. The driver will determine + * whether to use the data or not. */ - if (!(CONFIG(SANDYBRIDGE_VBOOT_IN_BOOTBLOCK) && vboot_recovery_mode_enabled()) || - pei_data->boot_mode == 2) - prepare_mrc_cache(pei_data); + prepare_mrc_cache(pei_data); /* If MRC data is not found we cannot continue S3 resume. */ if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c index 7020ddfe0d..e51b4f7b66 100644 --- a/src/soc/intel/broadwell/raminit.c +++ b/src/soc/intel/broadwell/raminit.c @@ -85,29 +85,23 @@ void raminit(struct pei_data *pei_data) broadwell_fill_pei_data(pei_data); - if (CONFIG(BROADWELL_VBOOT_IN_BOOTBLOCK) && - vboot_recovery_mode_enabled()) { - /* Recovery mode does not use MRC cache */ - printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); - } else { - /* Assume boot device is memory mapped. */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + /* Assume boot device is memory mapped. */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - pei_data->saved_data = - mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0, - &mrc_size); - if (pei_data->saved_data) { - /* MRC cache found */ - pei_data->saved_data_size = mrc_size; - } else if (pei_data->boot_mode == ACPI_S3) { - /* Waking from S3 and no cache. */ - printk(BIOS_DEBUG, - "No MRC cache found in S3 resume path.\n"); - post_code(POST_RESUME_FAILURE); - system_reset(); - } else { - printk(BIOS_DEBUG, "No MRC cache found.\n"); - } + pei_data->saved_data = + mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0, + &mrc_size); + if (pei_data->saved_data) { + /* MRC cache found */ + pei_data->saved_data_size = mrc_size; + } else if (pei_data->boot_mode == ACPI_S3) { + /* Waking from S3 and no cache. */ + printk(BIOS_DEBUG, + "No MRC cache found in S3 resume path.\n"); + post_code(POST_RESUME_FAILURE); + system_reset(); + } else { + printk(BIOS_DEBUG, "No MRC cache found.\n"); } /* diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index 4cd1c41cac..066ff5db1c 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -33,7 +33,6 @@ config VBOOT select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK - select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config SC7180_QSPI bool From 77038b16fff3801b6209696cc4fea861800f1165 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 6 Nov 2020 12:59:46 +0100 Subject: [PATCH 260/262] soc/intel/xeon_sp: Improve generating PCH IOAPIC MADT entry The PCH IOAPIC ID is 0x8 so it needs to be generated before the IIO IOAPICs. Since we will get rid of the ioapic_id array this makes it more readable. Change-Id: I64a3b259e438ef666fb68a433cceda10aebdb1bf Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47301 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/soc/intel/xeon_sp/acpi.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index f747f872ea..3b4b7133e4 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -86,6 +86,8 @@ static unsigned long add_madt_ioapic(unsigned long current, int socket, int stac unsigned long acpi_fill_madt(unsigned long current) { int cur_index; + int ioapic_id; + int gsi_base; const IIO_UDS *hob = get_iio_uds(); /* With XEON-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ @@ -102,6 +104,12 @@ unsigned long acpi_fill_madt(unsigned long current) current = xeonsp_acpi_create_madt_lapics(current); cur_index = 0; + ioapic_id = ioapic_ids[cur_index]; + gsi_base = gsi_bases[cur_index]; + current += add_madt_ioapic(current, 0, 0, ioapic_id, + hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase, + gsi_base); + ++cur_index; for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { @@ -111,25 +119,20 @@ unsigned long acpi_fill_madt(unsigned long current) continue; assert(cur_index < ARRAY_SIZE(ioapic_ids)); assert(cur_index < ARRAY_SIZE(gsi_bases)); - int ioapic_id = ioapic_ids[cur_index]; - int gsi_base = gsi_bases[cur_index]; - current += add_madt_ioapic(current, socket, stack, ioapic_id, - ri->IoApicBase, gsi_base); - ++cur_index; + ioapic_id = ioapic_ids[cur_index]; + gsi_base = gsi_bases[cur_index]; + uint32_t ioapic_base = ri->IoApicBase; /* * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. - * Add entry for PCH IOAPIC. + * The IIO IOAPIC is placed at 0x1000 from the reported base. */ - if (stack == 0 && socket == 0) { /* PCH IOAPIC */ - assert(cur_index < ARRAY_SIZE(ioapic_ids)); - assert(cur_index < ARRAY_SIZE(gsi_bases)); - ioapic_id = ioapic_ids[cur_index]; - gsi_base = gsi_bases[cur_index]; - current += add_madt_ioapic(current, socket, stack, ioapic_id, - ri->IoApicBase + 0x1000, gsi_base); - ++cur_index; - } + if (stack == 0 && socket == 0) + ioapic_base += 0x1000; + + current += add_madt_ioapic(current, socket, stack, ioapic_id, + ioapic_base, gsi_base); + ++cur_index; } } From ed21df6cec49f2c7dd5ae8286eaee958104e781d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 19 Sep 2020 00:08:45 +0200 Subject: [PATCH 261/262] soc/intel/common/block: add code for ACPI CPPC entries generation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Copy the code for CPPC entries generation, needed for Intel SpeedShift, from SKL to common ACPI code. SKL is going to use common ACPI code, too, in the future, so this code duplication will vanish soon. Test: dumped SSDT from Clevo L140CU and checked decompiled version after enabling CPPC entries via Kconfig Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45535 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/acpi/acpi.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 5951b30e11..f0ff89889a 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include #include @@ -9,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -20,6 +22,8 @@ #include #include +#define CPUID_6_EAX_ISST (1 << 7) + __attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current) { /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ @@ -391,6 +395,23 @@ void generate_t_state_entries(int core, int cores_per_package) acpigen_write_TSS_package(entries, soc_tss_table); } +static void generate_cppc_entries(int core_id) +{ + if (!(CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPPC) && + cpuid_eax(6) & CPUID_6_EAX_ISST)) + return; + + /* Generate GCPC package in first logical core */ + if (core_id == 0) { + struct cppc_config cppc_config; + cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2); + acpigen_write_CPPC_package(&cppc_config); + } + + /* Write _CPC entry for each logical core */ + acpigen_write_CPPC_method(); +} + __weak void soc_power_states_generation(int core_id, int cores_per_package) { @@ -421,6 +442,8 @@ void generate_cpu_entries(const struct device *device) /* Generate C-state tables */ generate_c_state_entries(); + generate_cppc_entries(core_id); + /* Soc specific power states generation */ soc_power_states_generation(core_id, cores_per_package); From c66e1c2a319a682a4616589901df301a816076ae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 12 Nov 2020 23:50:37 +0100 Subject: [PATCH 262/262] soc/intel/cnl: enable ACPI CPPC entries generation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable CPPC entries generation, needed for Intel SpeedShift. Test: dumped SSDT from Clevo L140CU and checked decompiled version Change-Id: I0c8066a31d3bec27776836aac54c335c0e5d74e6 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/47541 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 7b9b88be61..f4273407a8 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -103,6 +103,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU