skylake: fix serial port with new code base

Many Kconfig options changed in coreboot.org since
skylake was first started. Fix Kconfig option name
changes, and also provide a common option, UART_DEBUG
that can be selected to select all the necessary
options.

Note: It's still a requirement to manually unset the
      8250IO option because that's unconditionally set.

BUG=chrome-os-partner:43419
BUG=chrome-os-partner:43463
BRANCH=None
TEST=Built glados. Booted into kernel. Kernel reboots somewhere.

Original-Change-Id: I9e6549ea0f1d6b9ffe64a73856ec87b5bc7b7091
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289951
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I0e6b492d7279cc35d4fb3ac17fd727177adce39d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11172
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin
2015-07-30 16:52:56 -05:00
parent 14bb36c5ca
commit e33a1724b3
7 changed files with 69 additions and 12 deletions

View File

@ -18,11 +18,11 @@
* Foundation, Inc.
*/
#include <console/uart.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <stdlib.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
@ -36,10 +36,11 @@ static void pch_uart_read_resources(struct device *dev)
pci_dev_read_resources(dev);
/* Set the configured UART base address for the debug port */
if (IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32) &&
pch_uart_is_debug(dev)) {
if (IS_ENABLED(CONFIG_UART_DEBUG) && pch_uart_is_debug(dev)) {
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
res->size = 0x1000;
/* Need to set the base and size for the resource allocator. */
res->base = UART_DEBUG_BASE_ADDRESS;
res->size = UART_DEBUG_BASE_SIZE;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
}