sio/ite/common: Add generic environment-controller driver
The environment-controller entity is shared by many ITE super-i/o chips. There are some differences between the chips, though. To cover that, the super-i/o chip should select Kconfig options of this driver accordingly. The current implementation isn't exhaustive: It covers only those parts that are connected on boards I could test, plus those that are currently used by the IT8772F. The latter could be ported to use this driver if somebody minds to test it. Change-Id: I7a40f677f667d103ce1d09a3e468915729067803 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17284 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Nico Huber
Nico Huber
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src/superio/ite/common/env_ctrl.c
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src/superio/ite/common/env_ctrl.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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* Copyright (C) 2016 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdlib.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <delay.h>
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#include "env_ctrl.h"
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#include "env_ctrl_chip.h"
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static inline u8 ite_ec_read(const u16 base, const u8 addr)
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{
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outb(addr, base + 5);
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return inb(base + 6);
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}
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static inline void ite_ec_write(const u16 base, const u8 addr, const u8 value)
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{
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outb(addr, base + 5);
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outb(value, base + 6);
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}
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static void extemp_force_idle_status(const u16 base)
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{
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u8 reg;
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int retries = 10;
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/* Wait up to 10ms for non-busy state. */
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while (retries > 0) {
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reg = ite_ec_read(base, ITE_EC_EXTEMP_STATUS);
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if ((reg & ITE_EC_EXTEMP_STATUS_HOST_BUSY) == 0x0)
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break;
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retries--;
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mdelay(1);
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}
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if (retries == 0 && (reg & ITE_EC_EXTEMP_STATUS_HOST_BUSY) == 0x1) {
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/*
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* SIO is busy due to unfinished peci transaction.
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* Re-configure Register 0x8E to terminate processes.
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*/
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ite_ec_write(base, ITE_EC_EXTEMP_CONTROL,
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ITE_EC_EXTEMP_CTRL_AUTO_4HZ |
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ITE_EC_EXTEMP_CTRL_AUTO_START);
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}
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}
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/*
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* Setup External Temperature to read via PECI into TMPINx register
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*/
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static void enable_peci(const u16 base, const u8 tmpin)
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{
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if (tmpin == 0 || tmpin > ITE_EC_TMPIN_CNT)
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return;
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/* Enable PECI interface */
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ite_ec_write(base, ITE_EC_INTERFACE_SELECT,
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ITE_EC_INTERFACE_SEL_PECI |
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ITE_EC_INTERFACE_SPEED_TOLERANCE);
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/* Setup External Temperature using PECI GetTemp */
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ite_ec_write(base, ITE_EC_EXTEMP_ADDRESS,
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PECI_CLIENT_ADDRESS);
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ite_ec_write(base, ITE_EC_EXTEMP_COMMAND,
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PECI_GETTEMP_COMMAND);
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ite_ec_write(base, ITE_EC_EXTEMP_WRITE_LENGTH,
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PECI_GETTEMP_WRITE_LENGTH);
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ite_ec_write(base, ITE_EC_EXTEMP_READ_LENGTH,
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PECI_GETTEMP_READ_LENGTH);
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ite_ec_write(base, ITE_EC_EXTEMP_CONTROL,
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ITE_EC_EXTEMP_CTRL_AUTO_4HZ |
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ITE_EC_EXTEMP_CTRL_AUTO_START);
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/* External Temperature reported in TMPINx register */
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ite_ec_write(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE,
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(tmpin & 3) << 6);
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}
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/*
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* Set up External Temperature to read via thermal diode/resistor
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* into TMPINx register
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*/
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static void enable_tmpin(const u16 base, const int tmpin,
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const enum ite_ec_thermal_mode mode)
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{
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u8 reg;
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reg = ite_ec_read(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE);
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switch (mode) {
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case THERMAL_DIODE:
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reg |= ITE_EC_ADC_TEMP_DIODE_MODE(tmpin);
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break;
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case THERMAL_RESISTOR:
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reg |= ITE_EC_ADC_TEMP_RESISTOR_MODE(tmpin);
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break;
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default:
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printk(BIOS_WARNING,
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"Unsupported thermal mode 0x%x on TMPIN%d\n",
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mode, tmpin);
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return;
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}
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ite_ec_write(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE, reg);
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/* Enable the startup of monitoring operation */
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reg = ite_ec_read(base, ITE_EC_CONFIGURATION);
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reg |= ITE_EC_CONFIGURATION_START;
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ite_ec_write(base, ITE_EC_CONFIGURATION, reg);
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}
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static void fan_smartconfig(const u16 base, const u8 fan,
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const enum ite_ec_fan_mode mode,
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const struct ite_ec_fan_smartconfig *const conf)
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{
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u8 pwm_ctrl;
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u8 pwm_start = 0;
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u8 pwm_auto = 0;
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if (mode == FAN_SMART_SOFTWARE) {
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pwm_ctrl = ITE_EC_FAN_CTL_PWM_MODE_SOFTWARE;
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/* 50% duty cycle by default */
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const u8 duty = conf->pwm_start ? conf->pwm_start : 50;
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if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_8BIT_PWM))
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pwm_start = ITE_EC_FAN_CTL_PWM_DUTY(duty);
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else
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pwm_ctrl |= ITE_EC_FAN_CTL_PWM_DUTY(duty);
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} else {
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pwm_ctrl = ITE_EC_FAN_CTL_PWM_MODE_AUTOMATIC;
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pwm_ctrl |= ITE_EC_FAN_CTL_TEMPIN(conf->tmpin);
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pwm_start = ITE_EC_FAN_CTL_PWM_START_DUTY(conf->pwm_start);
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pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope);
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pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope);
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ite_ec_write(base, ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(fan),
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conf->tmp_off);
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ite_ec_write(base, ITE_EC_FAN_CTL_TEMP_LIMIT_START(fan),
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conf->tmp_start);
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/* Full speed above 127°C by default */
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ite_ec_write(base, ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(fan),
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conf->tmp_full ? conf->tmp_full : 127);
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ite_ec_write(base, ITE_EC_FAN_CTL_DELTA_TEMP(fan),
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ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(conf->tmp_delta));
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}
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ite_ec_write(base, ITE_EC_FAN_CTL_PWM_CONTROL(fan), pwm_ctrl);
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ite_ec_write(base, ITE_EC_FAN_CTL_PWM_START(fan), pwm_start);
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ite_ec_write(base, ITE_EC_FAN_CTL_PWM_AUTO(fan), pwm_auto);
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}
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static void enable_fan(const u16 base, const u8 fan,
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const struct ite_ec_fan_config *const conf)
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{
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u8 reg;
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if (conf->mode == FAN_IGNORE)
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return;
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/* FAN_CTL2 might have its own frequency setting */
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if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2) && fan == 2) {
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reg = ite_ec_read(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE);
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reg &= ~ITE_EC_FAN_PWM_CLOCK_MASK;
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reg |= ITE_EC_FAN_PWM_DEFAULT_CLOCK;
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ite_ec_write(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE, reg);
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}
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if (conf->mode >= FAN_SMART_SOFTWARE) {
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fan_smartconfig(base, fan, conf->mode, &conf->smart);
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} else {
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reg = ite_ec_read(base, ITE_EC_FAN_CTL_MODE);
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if (conf->mode == FAN_MODE_ON)
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reg |= ITE_EC_FAN_CTL_ON(fan);
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else
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reg &= ~ITE_EC_FAN_CTL_ON(fan);
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ite_ec_write(base, ITE_EC_FAN_CTL_MODE, reg);
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}
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if (IS_ENABLED(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG)
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&& conf->mode >= FAN_MODE_ON) {
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reg = ite_ec_read(base, ITE_EC_FAN_TAC_COUNTER_ENABLE);
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reg |= ITE_EC_FAN_TAC_16BIT_ENABLE(fan);
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ite_ec_write(base, ITE_EC_FAN_TAC_COUNTER_ENABLE, reg);
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}
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reg = ite_ec_read(base, ITE_EC_FAN_MAIN_CTL);
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if (conf->mode >= FAN_MODE_ON)
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reg |= ITE_EC_FAN_MAIN_CTL_TAC_EN(fan);
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else
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reg &= ~ITE_EC_FAN_MAIN_CTL_TAC_EN(fan);
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if (conf->mode >= FAN_SMART_SOFTWARE)
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reg |= ITE_EC_FAN_MAIN_CTL_SMART(fan);
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else
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reg &= ~ITE_EC_FAN_MAIN_CTL_SMART(fan);
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ite_ec_write(base, ITE_EC_FAN_MAIN_CTL, reg);
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}
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void ite_ec_init(const u16 base, const struct ite_ec_config *const conf)
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{
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size_t i;
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/* Configure 23.43kHz PWM active high output */
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u8 fan_ctl = ite_ec_read(base, ITE_EC_FAN_CTL_MODE);
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fan_ctl &= ~ITE_EC_FAN_PWM_CLOCK_MASK;
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fan_ctl |= ITE_EC_FAN_PWM_DEFAULT_CLOCK;
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fan_ctl |= ITE_EC_FAN_CTL_POLARITY_HIGH;
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ite_ec_write(base, ITE_EC_FAN_CTL_MODE, fan_ctl);
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/* Enable PECI if configured */
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enable_peci(base, conf->peci_tmpin);
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/* Enable HWM if configured */
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for (i = 0; i < ITE_EC_TMPIN_CNT; ++i)
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enable_tmpin(base, i + 1, conf->tmpin_mode[i]);
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/* Enable reading of voltage pins */
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ite_ec_write(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask);
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/* Enable FANx if configured */
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for (i = 0; i < ITE_EC_FAN_CNT; ++i)
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enable_fan(base, i + 1, &conf->fan[i]);
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/*
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* System may get wrong temperature data when SIO is in
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* busy state. Therefore, check the status and terminate
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* processes if needed.
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*/
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if (conf->peci_tmpin != 0)
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extemp_force_idle_status(base);
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}
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