soc/intel/xeon_sp: Use common _CRS code generation
Drop SoC specific code and use generic implementation provided by pci_domain_fill_ssdt. TEST=Booted on IBM/SBP1 to Ubuntu 22.04. TEST=intel/archercity CRB Change-Id: I8b0bc2eb02569b5d74f8521d79e0af8fee880c80 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80796 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This commit is contained in:
Patrick Rudolph
Lean Sheng Tan
parent
abc274474a
commit
e357ac3321
@ -1,5 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpigen_pci.h>
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#include <assert.h>
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#include <console/console.h>
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#include <device/pci.h>
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@ -243,6 +244,7 @@ static struct device_operations iio_pcie_domain_ops = {
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#if CONFIG(HAVE_ACPI_TABLES)
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.acpi_name = soc_acpi_name,
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.write_acpi_tables = northbridge_write_acpi_tables,
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.acpi_fill_ssdt = pci_domain_fill_ssdt,
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#endif
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};
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@ -257,6 +259,7 @@ static struct device_operations ubox_pcie_domain_ops = {
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#if CONFIG(HAVE_ACPI_TABLES)
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.acpi_name = soc_acpi_name,
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.write_acpi_tables = northbridge_write_acpi_tables,
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.acpi_fill_ssdt = pci_domain_fill_ssdt,
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#endif
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};
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@ -348,6 +351,7 @@ static struct device_operations iio_cxl_domain_ops = {
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#if CONFIG(HAVE_ACPI_TABLES)
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.acpi_name = soc_acpi_name,
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.write_acpi_tables = northbridge_write_acpi_tables,
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.acpi_fill_ssdt = pci_domain_fill_ssdt,
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#endif
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};
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@ -1,5 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpigen_pci.h>
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#include <arch/ioapic.h>
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#include <console/console.h>
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#include <console/debug.h>
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@ -43,72 +43,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
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void uncore_fill_ssdt(const struct device *device)
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{
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struct iiostack_resource stack_info = {0};
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/* Only add RTxx entries once. */
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if (device->upstream->secondary != 0 || device->upstream->segment_group != 0)
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return;
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get_iiostack_info(&stack_info);
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for (uint8_t stack = 0; stack < stack_info.no_of_stacks; ++stack) {
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const STACK_RES *ri = &stack_info.res[stack];
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char rtname[16];
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snprintf(rtname, sizeof(rtname), "\\_SB.PC%02x", stack);
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acpigen_write_scope(rtname);
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acpigen_write_name("_CRS");
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printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for stack: %d\n",
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rtname, stack);
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acpigen_write_resourcetemplate_header();
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/* bus resource */
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acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit,
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0x0, (ri->BusLimit - ri->BusBase + 1));
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/* additional io resources on socket 0 bus 0 */
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if (stack == 0) {
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/* ACPI 6.4.2.5 I/O Port Descriptor */
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acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1);
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/* IO decode CF8-CFF */
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0);
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918);
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C);
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020);
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}
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/* IO resource */
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acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase,
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ri->PciResourceIoLimit, 0x0,
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(ri->PciResourceIoLimit - ri->PciResourceIoBase + 1));
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/* additional mem32 resources on socket 0 bus 0 */
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if (stack == 0) {
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acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE,
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VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE);
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acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
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(SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
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SPI_BASE_SIZE);
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}
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/* Mem32 resource */
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acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base,
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ri->PciResourceMem32Limit, 0x0,
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(ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1));
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/* Mem64 resource */
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acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base,
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ri->PciResourceMem64Limit, 0x0,
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(ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1));
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acpigen_write_resourcetemplate_footer();
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/* Scope */
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acpigen_pop_len();
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}
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}
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/* TODO: See if we can use the common generate_p_state_entries */
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@ -1,5 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpigen_pci.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <device/pci.h>
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@ -56,82 +56,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
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void uncore_fill_ssdt(const struct device *device)
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{
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const IIO_UDS *hob = get_iio_uds();
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/* Only add RTxx entries once. */
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if (device->upstream->secondary != 0)
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return;
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for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) {
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if (!soc_cpu_is_enabled(socket))
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continue;
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iio++;
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IIO_RESOURCE_INSTANCE iio_resource =
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hob->PlatformData.IIO_resource[socket];
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for (int stack = 0; stack <= PSTACK2; ++stack) {
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const STACK_RES *ri = &iio_resource.StackRes[stack];
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char rtname[16];
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snprintf(rtname, sizeof(rtname), "\\_SB.PC%02x", socket * MAX_IIO_STACK + stack);
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acpigen_write_scope(rtname);
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acpigen_write_name("_CRS");
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printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n",
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rtname, socket, stack);
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acpigen_write_resourcetemplate_header();
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/* bus resource */
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acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit,
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0x0, (ri->BusLimit - ri->BusBase + 1));
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// additional io resources on socket 0 bus 0
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if (socket == 0 && stack == 0) {
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/* ACPI 6.4.2.5 I/O Port Descriptor */
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acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1);
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/* IO decode CF8-CFF */
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF,
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0, 0x03B0);
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7,
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0, 0x0918);
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB,
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0, 0x000C);
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF,
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0, 0x0020);
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}
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/* IO resource */
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acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase,
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ri->PciResourceIoLimit, 0x0,
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(ri->PciResourceIoLimit - ri->PciResourceIoBase + 1));
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// additional mem32 resources on socket 0 bus 0
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if (socket == 0 && stack == 0) {
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acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE,
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VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE);
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acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
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(SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
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SPI_BASE_SIZE);
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}
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/* Mem32 resource */
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acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base,
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ri->PciResourceMem32Limit, 0x0,
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(ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1));
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/* Mem64 resource */
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acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base,
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ri->PciResourceMem64Limit, 0x0,
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(ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1));
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acpigen_write_resourcetemplate_footer();
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/* Scope */
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acpigen_pop_len();
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}
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}
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}
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void soc_power_states_generation(int core, int cores_per_package)
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@ -1,5 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpigen_pci.h>
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#include <arch/ioapic.h>
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#include <console/console.h>
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#include <console/debug.h>
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@ -1,5 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpigen_pci.h>
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#include <stdbool.h>
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#include <console/console.h>
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@ -26,6 +26,7 @@ static struct device_operations ioat_domain_ops = {
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#if CONFIG(HAVE_ACPI_TABLES)
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.acpi_name = soc_acpi_name,
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.write_acpi_tables = northbridge_write_acpi_tables,
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.acpi_fill_ssdt = pci_domain_fill_ssdt,
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#endif
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};
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@ -53,279 +53,11 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
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fill_fadt_extended_pm_io(fadt);
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}
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static void create_dsdt_iou_pci_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri,
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bool stack_enabled)
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{
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/*
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Stacks 0 (TYPE_UBOX_IIO)
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Scope: PC<socket><stack>, ResourceTemplate: P0RS
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Stacks 1 .. 5 (TYPE_UBOX_IIO)
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Scope: PC<socket><stack>, ResourceTemplate: RBRS
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*/
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/* write _CRS scope */
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char tres[16];
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snprintf(tres, sizeof(tres), "\\_SB.PC%d%X", socket, stack);
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acpigen_write_scope(tres);
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acpigen_write_name("_CRS");
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printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", tres,
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socket, stack);
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acpigen_write_resourcetemplate_header();
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/* Bus Resource */
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if (stack_enabled) {
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/* For stack with CXL device, the PCIe bus resource is BusBase only. */
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if (is_iio_cxl_stack_res(ri))
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acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusBase, 0x0, 1);
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else
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acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit, 0x0,
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(ri->BusLimit - ri->BusBase + 1));
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} else {
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acpigen_resource_word(2, 0, 0, 0, 0, 0, 0, 0);
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}
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/* Additional IO resources on socket 0 bus 0 */
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if (socket == 0 && stack == 0) {
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/* ACPI 6.4.2.5 I/O Port Descriptor */
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acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1);
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/* IO decode CF8-CFF */
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0);
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918);
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C);
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acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020);
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}
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/* IO resource */
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if (stack_enabled) {
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acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase,
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ri->PciResourceIoLimit, 0x0,
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(ri->PciResourceIoLimit - ri->PciResourceIoBase + 1));
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/* Additional Mem32 resources on socket 0 bus 0 */
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if (socket == 0 && stack == 0) {
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acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE,
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VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE);
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acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
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(SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
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SPI_BASE_SIZE);
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}
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/* Mem32 resource */
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acpigen_resource_dword(
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0, 0xc, 1, 0, ri->PciResourceMem32Base, ri->PciResourceMem32Limit, 0x0,
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(ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1));
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/* Mem64 resource */
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acpigen_resource_qword(
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0, 0xc, 1, 0, ri->PciResourceMem64Base, ri->PciResourceMem64Limit, 0x0,
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(ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1));
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} else {
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/* Zeroed IO resource */
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acpigen_resource_word(1, 0, 3, 0, 0, 0, 0, 0);
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/* Zeroed Mem32 resource */
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acpigen_resource_dword(0, 0, 1, 0, 0, 0, 0, 0);
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/* Zeroed Mem64 resource */
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acpigen_resource_dword(0, 0, 1, 0, 0, 0, 0, 0);
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}
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acpigen_write_resourcetemplate_footer();
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acpigen_pop_len();
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}
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static void create_dsdt_iou_cxl_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled)
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{
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/*
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Stacks 1 .. 5 (TYPE_UBOX_IIO)
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Scope: CX<socket><stack>, ResourceTemplate: RBRS
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*/
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/* write _CRS scope */
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char tres[16];
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snprintf(tres, sizeof(tres), "\\_SB.CX%d%X", socket, stack);
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acpigen_write_scope(tres);
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acpigen_write_name("_CRS");
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printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", tres,
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socket, stack);
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acpigen_write_resourcetemplate_header();
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if (stack_enabled) {
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/* bus resource, from (BusBase + 1) to BusLimit */
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acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase + 1, ri->BusLimit, 0x0,
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(ri->BusLimit - ri->BusBase));
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/* IO resource */
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acpigen_resource_word(1, 0xc, 0x3, 0, ri->IoBase, ri->PciResourceIoBase - 1,
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0x0, ri->PciResourceIoBase - ri->IoBase);
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/* Mem32 resource */
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acpigen_resource_dword(0, 0xc, 1, 0, ri->Mmio32Base,
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ri->PciResourceMem32Base - 1, 0x0,
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ri->PciResourceMem32Base - ri->Mmio32Base);
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/* Mem64 resource */
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acpigen_resource_qword(0, 0xc, 1, 0, ri->Mmio64Base,
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ri->PciResourceMem64Base - 1, 0x0,
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ri->PciResourceMem64Base - ri->Mmio64Base);
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} else {
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/* bus resource, from (BusBase + 1) to BusLimit */
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acpigen_resource_word(2, 0, 0, 0, 0, 0, 0, 0);
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/* IO resource */
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acpigen_resource_word(1, 0, 3, 0, 0, 0, 0, 0);
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/* Mem32 resource */
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acpigen_resource_dword(0, 0, 1, 0, 0, 0, 0, 0);
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/* Mem64 resource */
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acpigen_resource_qword(0, 0, 1, 0, 0, 0, 0, 0);
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}
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acpigen_write_resourcetemplate_footer();
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acpigen_pop_len();
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}
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static void create_dsdt_ioat_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled)
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{
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if (!stack_enabled)
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return;
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/*
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Stacks 8 .. B (TYPE_DINO)
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Scope: DI<socket><stack> for DINO, ResourceTemplate: DT
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Scope: CP<socket><stack> for CPM (i.e., QAT), ResourceTemplate: MT
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Scope: HQ<socket><stack> for HQM (i.e., DLB), ResourceTemplate: HT
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*/
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enum {
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DSDT_DINO = 0,
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DSDT_CPM,
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DSDT_HQM,
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DSDT_CPM1,
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DSDT_HQM1
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};
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uint8_t rlist[] = {DSDT_DINO, DSDT_CPM, DSDT_HQM, DSDT_CPM1, DSDT_HQM1};
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for (int i = 0; i < ARRAY_SIZE(rlist); ++i) {
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uint8_t bus_base, bus_limit;
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uint64_t mem64_base, mem64_limit;
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char tres[16];
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/* Note, This allocates the resources in a different order than
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* coreboot (DINO base is last). This causes the kernel to
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* reallocate the DINO BARs.
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* TODO: Use the resource settings from coreboot */
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if (rlist[i] == DSDT_DINO) {
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bus_base = ri->BusBase;
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||||
bus_limit = ri->BusBase;
|
||||
mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE + HQM_MMIO_SIZE
|
||||
+ CPM_MMIO_SIZE + HQM_MMIO_SIZE;
|
||||
mem64_limit = ri->PciResourceMem64Limit;
|
||||
snprintf(tres, sizeof(tres), "\\_SB.DI%d%X", socket, stack);
|
||||
} else if (rlist[i] == DSDT_CPM) {
|
||||
bus_base = ri->BusBase + CPM_BUS_OFFSET;
|
||||
bus_limit = bus_base + CPM_RESERVED_BUS;
|
||||
mem64_base = ri->PciResourceMem64Base;
|
||||
mem64_limit = mem64_base + CPM_MMIO_SIZE - 1;
|
||||
snprintf(tres, sizeof(tres), "\\_SB.PM%d%X", socket, stack);
|
||||
} else if (rlist[i] == DSDT_HQM) {
|
||||
bus_base = ri->BusBase + HQM_BUS_OFFSET;
|
||||
bus_limit = bus_base + HQM_RESERVED_BUS;
|
||||
mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE;
|
||||
mem64_limit = mem64_base + HQM_MMIO_SIZE - 1;
|
||||
snprintf(tres, sizeof(tres), "\\_SB.HQ%d%X", socket, stack);
|
||||
} else if (rlist[i] == DSDT_CPM1) {
|
||||
bus_base = ri->BusBase + CPM1_BUS_OFFSET;
|
||||
bus_limit = bus_base + CPM_RESERVED_BUS;
|
||||
mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE + HQM_MMIO_SIZE;
|
||||
mem64_limit = mem64_base + CPM_MMIO_SIZE - 1;
|
||||
snprintf(tres, sizeof(tres), "\\_SB.PN%d%X", socket, stack);
|
||||
} else {
|
||||
bus_base = ri->BusBase + HQM1_BUS_OFFSET;
|
||||
bus_limit = bus_base + HQM_RESERVED_BUS;
|
||||
mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE + HQM_MMIO_SIZE
|
||||
+ CPM_MMIO_SIZE;
|
||||
mem64_limit = mem64_base + HQM_MMIO_SIZE - 1;
|
||||
snprintf(tres, sizeof(tres), "\\_SB.HR%d%X", socket, stack);
|
||||
}
|
||||
|
||||
/* Note, some SKU doesn't provide CPM1 and HQM1 and owns smaller bus ranges
|
||||
accordingly*/
|
||||
if (bus_limit > ri->BusLimit)
|
||||
continue;
|
||||
|
||||
printk(BIOS_DEBUG,
|
||||
"\tCreating Dino ResourceTemplate %s for socket: %d, "
|
||||
"stack: %d\n bus_base:0x%x, bus_limit:0x%x\n",
|
||||
tres, socket, stack, bus_base, bus_limit);
|
||||
|
||||
acpigen_write_scope(tres);
|
||||
acpigen_write_name("_CRS");
|
||||
acpigen_write_resourcetemplate_header();
|
||||
|
||||
acpigen_resource_word(2, 0xc, 0, 0, bus_base, bus_limit, 0x0,
|
||||
(bus_limit - bus_base + 1));
|
||||
|
||||
/* Mem32 resource */
|
||||
if (rlist[i] == DSDT_DINO)
|
||||
acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base,
|
||||
ri->PciResourceMem32Limit, 0x0,
|
||||
(ri->PciResourceMem32Limit
|
||||
- ri->PciResourceMem32Base + 1));
|
||||
|
||||
/* Mem64 resource */
|
||||
acpigen_resource_qword(0, 0xc, 1, 0, mem64_base, mem64_limit, 0,
|
||||
(mem64_limit - mem64_base + 1));
|
||||
|
||||
acpigen_write_resourcetemplate_footer();
|
||||
acpigen_pop_len();
|
||||
}
|
||||
}
|
||||
|
||||
static void create_dsdt_ubox_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled)
|
||||
{
|
||||
/*
|
||||
Stacks D .. E (TYPE_UBOX)
|
||||
Scope: UC/UD<socket><0..1> for UBOX[1-2], ResourceTemplate: UT/UU
|
||||
*/
|
||||
for (int i = 0; i < 2; ++i) {
|
||||
char tres[16];
|
||||
/* write _CRS scope */
|
||||
if (i == 0)
|
||||
snprintf(tres, sizeof(tres), "\\_SB.UC%d%X", socket, stack);
|
||||
else
|
||||
snprintf(tres, sizeof(tres), "\\_SB.UD%d%X", socket, stack);
|
||||
|
||||
printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n",
|
||||
tres, socket, stack);
|
||||
|
||||
acpigen_write_scope(tres);
|
||||
acpigen_write_name("_CRS");
|
||||
acpigen_write_resourcetemplate_header();
|
||||
|
||||
if (!stack_enabled)
|
||||
acpigen_resource_word(2, 0, 0, 0, 0, 0, 0, 0);
|
||||
else if (i == 0)
|
||||
acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusBase, 0x0, 1);
|
||||
else
|
||||
acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase + 1, ri->BusBase + 1,
|
||||
0x0, 1);
|
||||
|
||||
acpigen_write_resourcetemplate_footer();
|
||||
acpigen_pop_len();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Add a DSDT ACPI Name field for STACK enable setting.
|
||||
* This is retrieved by the device _STA defined in iiostack.asl
|
||||
*/
|
||||
static void create_dsdt_stack_sta(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled)
|
||||
static void create_dsdt_stack_sta(uint8_t socket, uint8_t stack, bool stack_enabled)
|
||||
{
|
||||
char stack_sta[16];
|
||||
snprintf(stack_sta, sizeof(stack_sta), "ST%d%X", socket, stack);
|
||||
@ -375,17 +107,11 @@ void uncore_fill_ssdt(const struct device *device)
|
||||
__func__, socket, stack, ri->Personality);
|
||||
|
||||
if (stack <= IioStack5) { // TYPE_UBOX_IIO
|
||||
create_dsdt_iou_pci_resource(socket, stack, ri, stack_enabled);
|
||||
if (is_iio_cxl_stack_res(ri))
|
||||
create_dsdt_iou_cxl_resource(socket, stack, ri,
|
||||
stack_enabled);
|
||||
create_dsdt_stack_sta(socket, stack, ri, stack_enabled);
|
||||
create_dsdt_stack_sta(socket, stack, stack_enabled);
|
||||
} else if (stack >= IioStack8 && stack <= IioStack11) { // TYPE_DINO
|
||||
create_dsdt_ioat_resource(socket, stack, ri, stack_enabled);
|
||||
create_dsdt_stack_sta(socket, stack, ri, stack_enabled);
|
||||
create_dsdt_stack_sta(socket, stack, stack_enabled);
|
||||
} else if (stack == IioStack13) { // TYPE_UBOX
|
||||
create_dsdt_ubox_resource(socket, stack, ri, stack_enabled);
|
||||
create_dsdt_stack_sta(socket, stack, ri, stack_enabled);
|
||||
create_dsdt_stack_sta(socket, stack, stack_enabled);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user