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arch/x86: Indent using tabs not spaces

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No functional changes - just whitespace fixes.
Signed-off-by: Martin Roth <martinroth@google.com>

Change-Id: I8ffa87240bcbd3d657ed9dc619b5e5bf9de734d7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12853
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Martin Roth
2016-01-06 15:21:02 -07:00
parent 67e11d1e4f
commit e369010ab8
8 changed files with 89 additions and 89 deletions
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32
src/arch/x86/c_start.S
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@ -402,26 +402,26 @@ _idt_end:
SetCodeSelector:
.intel_syntax noprefix
# save rsp because iret will align it to a 16 byte boundary
mov rdx, rsp
# save rsp because iret will align it to a 16 byte boundary
mov rdx, rsp
# use iret to jump to a 64-bit offset in a new code segment
# iret will pop cs:rip, flags, then ss:rsp
mov ax, ss # need to push ss..
push rax # push ss instuction not valid in x64 mode, so use ax
push rsp
pushfq
push rcx # cx is code segment selector from caller
mov rax, offset setCodeSelectorLongJump
push rax
# use iret to jump to a 64-bit offset in a new code segment
# iret will pop cs:rip, flags, then ss:rsp
mov ax, ss # need to push ss..
push rax # push ss instuction not valid in x64 mode, so use ax
push rsp
pushfq
push rcx # cx is code segment selector from caller
mov rax, offset setCodeSelectorLongJump
push rax
# the iret will continue at next instruction, with the new cs value loaded
iretq
# the iret will continue at next instruction, with the new cs value loaded
iretq
setCodeSelectorLongJump:
# restore rsp, it might not have been 16-byte aligned on entry
mov rsp, rdx
ret
# restore rsp, it might not have been 16-byte aligned on entry
mov rsp, rdx
ret
.att_syntax prefix
.previous