Broadwell: Synchronize for power management with FRC

Set Root Port 0 PCI CFG Offset 0xE2[5:4] before ASPM configuration.

BUG=chrome-os-partner:31424
TEST=Build an image, and check the procedure and recommended setting
is applied correctly.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>

Change-Id: I94820787d4ed4a6bf8db8898b7de14467c9d6630
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 24bdea6cd67d5657b94058233cd26130f68c44e4
Original-Change-Id: I98713f615885ac02867942ece2be1cea8ce04ab2
Original-Reviewed-on: https://chromium-review.googlesource.com/219994
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com>
Original-Tested-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: http://review.coreboot.org/9211
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/intel/broadwell/broadwell/iobp.h

@@ -23,5 +23,6 @@
 u32 pch_iobp_read(u32 address);
 void pch_iobp_write(u32 address, u32 data);
 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
+void pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp);
 
 #endif

src/soc/intel/broadwell/broadwell/rcba.h

@@ -76,6 +76,8 @@
 #define  IOBPS_WRITE	0x0700
 #define IOBPU		0x233a
 #define  IOBPU_MAGIC	0xf000
+#define  IOBP_PCICFG_READ	0x0400
+#define  IOBP_PCICFG_WRITE	0x0500
 
 #define D31IP		0x3100	/* 32bit */
 #define D31IP_TTIP	24	/* Thermal Throttle Pin */

src/soc/intel/broadwell/iobp.c

@@ -123,3 +123,30 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
 
 	pch_iobp_write(address, data);
 }
+
+void pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp)
+{
+	if (!data || !resp)
+		return;
+
+	*resp = -1;
+	if (!iobp_poll())
+		return;
+
+	/* RCBA2330[31:0] = Address */
+	RCBA32(IOBPIRI) = addr;
+	/* RCBA2338[15:8] = opcode */
+	RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x00ff) | op_code;
+	/* RCBA233A[15:8] = 0xf0 RCBA233A[7:0] = Route ID */
+	RCBA16(IOBPU) = IOBPU_MAGIC | route_id;
+
+	RCBA32(IOBPD) = *data;
+	/* Set RCBA2338[0] to trigger IOBP transaction*/
+	RCBA16(IOBPS) = RCBA16(IOBPS) | 0x1;
+
+	if (!iobp_poll())
+		return;
+
+	*resp = (RCBA16(IOBPS) & IOBPS_TX_MASK) >> 1;
+	*data = RCBA32(IOBPD);
+}

src/soc/intel/broadwell/pcie.c

@@ -123,6 +123,8 @@ static void pcie_iosf_port_grant_count(device_t dev)
 static void root_port_init_config(device_t dev)
 {
 	int rp;
+	u32 data;
+	u8 resp, id;
 
 	if (root_port_is_first(dev)) {
 		rpc.orig_rpfn = RCBA32(RPFN);
@@ -170,6 +172,15 @@ static void root_port_init_config(device_t dev)
 	}
 
 	pcie_update_cfg(dev, 0x418, 0, 0x02000430);
+
+	/* set RP0 PCICFG E2h[5:4] = 11b before configuring ASPM */
+	if (root_port_is_first(dev)) {
+		id = 0xe0 + (u8)(RCBA32(RPFN) & 0x07);
+		pch_iobp_exec(0xE00000E0, IOBP_PCICFG_READ, id, &data, &resp);
+		data |= (0x30 << 16);
+		pch_iobp_exec(0xE00000E0, IOBP_PCICFG_WRITE, id, &data, &resp);
+	}
+
 	/* Cache pci device. */
 	rpc.ports[rp - 1] = dev;
 }