intel/cpu: Switch older models to TSC_MONOTONIC_TIMER

The implementation of udelay() with LAPIC timers
existed first, as we did not have calculations
implemented for TSC frequency.

Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/model_106cx/Kconfig

@@ -6,7 +6,9 @@ config CPU_INTEL_MODEL_106CX
 	select ARCH_RAMSTAGE_X86_32
 	select SMP
 	select SSE2
-	select UDELAY_LAPIC
+	select UDELAY_TSC
+	select TSC_CONSTANT_RATE
+	select TSC_MONOTONIC_TIMER
 	select SIPI_VECTOR_IN_ROM
 	select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE