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src: Get rid of unneeded whitespace

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Change-Id: I3873cc8ff82cb043e4867a6fe8c1f253ab18714a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS
2018-06-29 21:41:41 +02:00
committed by Patrick Georgi
parent 21b71ce66b
commit e3e3f4f4ed
10 changed files with 20 additions and 20 deletions
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4
src/arch/arm/include/armv7/arch/cache.h
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@@ -48,8 +48,8 @@
#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */
#define SCTLR_Z (1 << 11) /* Branch prediction enable */
#define SCTLR_I (1 << 12) /* Instruction cache enable */
#define SCTLR_V (1 << 13) /* Low/high exception vectors */
#define SCTLR_RR (1 << 14) /* Round Robin select */
#define SCTLR_V (1 << 13) /* Low/high exception vectors */
#define SCTLR_RR (1 << 14) /* Round Robin select */
/* Bits 16:15 are reserved */
#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */
/* Bit 18 is reserved */

4
src/arch/arm64/include/armv8/arch/cache.h
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@@ -48,8 +48,8 @@
#define SCTLR_EL1_UMA (1 << 9) /* User mask access */
#define SCTLR_EL1_DZE (1 << 14) /* DC ZVA instruction at EL0 */
#define SCTLR_EL1_UCT (1 << 15) /* CTR_EL0 register EL0 access */
#define SCTLR_EL1_NTWI (1 << 16) /* Not trap WFI */
#define SCTLR_EL1_NTWE (1 << 18) /* Not trap WFE */
#define SCTLR_EL1_NTWI (1 << 16) /* Not trap WFI */
#define SCTLR_EL1_NTWE (1 << 18) /* Not trap WFE */
#define SCTLR_EL1_E0E (1 << 24) /* Exception endianness at EL0 */
#define SCTLR_EL1_UCI (1 << 26) /* EL0 access to cache instructions */