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mb/google/rex/var/karis: Adjust touchscreen power-on sequence

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According to datasheet, EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high
should over 5ms. And current measure result is 200us.
Set EN_TCHSCR_PWR to output high in bootblock to make it meet datasheet
requirment.

Measurement result of EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high:
Power on --> 31.7 ms
Resume --> 38.7 ms

BUG=b:314245238
TEST=Measure the sequence

Change-Id: I56e455a980b465f27794b30df058ec0944befc2e
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79571
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tyler Wang
2023-12-12 10:04:47 +08:00
committed by Subrata Banik
parent ba07f95992
commit e41bf5f373
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/google/rex/variants/karis/gpio.c
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@@ -398,6 +398,9 @@ static const struct pad_config early_gpio_table[] = {
/* GPP_H10 : [] ==> SOC_WP_OD */ /* GPP_H10 : [] ==> SOC_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG),
/* GPP_C00 : [] ==> EN_TCHSCR_PWR */
PAD_CFG_GPO(GPP_C00, 1, DEEP),
}; };
static const struct pad_config romstage_gpio_table[] = { static const struct pad_config romstage_gpio_table[] = {