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soc/intel/xeon_sp: Add iio_ioapic.c

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Move the soc_get_ioapic_info for platforms with IIO IO-APICs to
a separate file from src/soc/intel/xeon_sp/acpi.c.

TEST=Build intel/archerticy CRB

Change-Id: I59022b7685539491604724ef3b550da1cfd53f13
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Shuo Liu
2024-04-06 05:13:27 +08:00
committed by Felix Held
parent 9d6333c839
commit e43f387022
3 changed files with 42 additions and 39 deletions
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1
src/soc/intel/xeon_sp/Makefile.mk
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@@ -15,6 +15,7 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c
ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c numa.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
ramstage-$(CONFIG_XEON_SP_HAVE_IIO_IOAPIC) += iio_ioapic.c
smm-y += smihandler.c pmutil.c
postcar-y += spi.c

39
src/soc/intel/xeon_sp/acpi.c
View File

@@ -90,45 +90,6 @@ const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
return map;
}
#if CONFIG(XEON_SP_HAVE_IIO_IOAPIC)
static uintptr_t xeonsp_ioapic_bases[CONFIG(XEON_SP_HAVE_IIO_IOAPIC) * 8 + 1];
size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[])
{
int index = 0;
const IIO_UDS *hob = get_iio_uds();
*ioapic_bases = xeonsp_ioapic_bases;
for (int socket = 0; socket < CONFIG_MAX_SOCKET; socket++) {
if (!soc_cpu_is_enabled(socket))
continue;
for (int stack = 0; stack < MAX_IIO_STACK; ++stack) {
const STACK_RES *ri =
&hob->PlatformData.IIO_resource[socket].StackRes[stack];
uint32_t ioapic_base = ri->IoApicBase;
if (ioapic_base == 0 || ioapic_base == 0xFFFFFFFF)
continue;
assert(index < ARRAY_SIZE(xeonsp_ioapic_bases));
xeonsp_ioapic_bases[index++] = ioapic_base;
if (!CONFIG(XEON_SP_HAVE_IIO_IOAPIC))
return index;
/*
* Stack 0 has non-PCH IOAPIC and PCH IOAPIC.
* The IIO IOAPIC is placed at 0x1000 from the reported base.
*/
if (socket == 0 && stack == 0) {
ioapic_base += 0x1000;
assert(index < ARRAY_SIZE(xeonsp_ioapic_bases));
xeonsp_ioapic_bases[index++] = ioapic_base;
}
}
}
return index;
}
#endif
void iio_domain_set_acpi_name(struct device *dev, const char *prefix)
{
const union xeon_domain_path dn = {

41
src/soc/intel/xeon_sp/iio_ioapic.c Normal file
View File

@@ -0,0 +1,41 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <assert.h>
#include <intelblocks/acpi.h>
#include <soc/chip_common.h>
#include <soc/util.h>
#include <stdint.h>
#include <stdlib.h>
static uintptr_t xeonsp_ioapic_bases[CONFIG_MAX_SOCKET * MAX_IIO_STACK + 1];
size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[])
{
int index = 0;
const IIO_UDS *hob = get_iio_uds();
*ioapic_bases = xeonsp_ioapic_bases;
for (int socket = 0; socket < CONFIG_MAX_SOCKET; socket++) {
if (!soc_cpu_is_enabled(socket))
continue;
for (int stack = 0; stack < MAX_IIO_STACK; ++stack) {
const STACK_RES *ri =
&hob->PlatformData.IIO_resource[socket].StackRes[stack];
uint32_t ioapic_base = ri->IoApicBase;
if (ioapic_base == 0 || ioapic_base == 0xFFFFFFFF)
continue;
xeonsp_ioapic_bases[index++] = ioapic_base;
/*
* Stack 0 has non-PCH IOAPIC and PCH IOAPIC.
* The IIO IOAPIC is placed at 0x1000 from the reported base.
*/
if (socket == 0 && stack == 0) {
ioapic_base += 0x1000;
xeonsp_ioapic_bases[index++] = ioapic_base;
}
}
}
return index;
}