AMD: Isolate AGESA and PI build environments

To backport features introduced with recent Chromebooks and/or Intel
boards in general, heavy work on the AMD AGESA platform infrastructure
is required. With the AGESA PI available in binary form only, community
members have little means to verify, debug and develop for the said
platforms.

Thus it makes sense to fork the existing agesawrapper interfaces, to give
AMD PI platforms a clean and independent sandbox. New directory layout
reflects the separation already taken place under 3rdparty/ and vendorcode/.

Change-Id: Ib60861266f8a70666617dde811663f2d5891a9e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7149
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)

src/cpu/amd/pi/00730F01/Kconfig

@@ -0,0 +1,69 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+config CPU_AMD_PI_00730F01
+	bool
+	select PCI_IO_CFG_EXT
+	select X86_AMD_FIXED_MTRRS
+
+if CPU_AMD_PI_00730F01
+
+config CPU_ADDR_BITS
+	int
+	default 40
+
+config CPU_SOCKET_TYPE
+	hex
+	default 0x10
+
+# DDR2 and REG
+config DIMM_SUPPORT
+	hex
+	default 0x0104
+
+config EXT_RT_TBL_SUPPORT
+	bool
+	default n
+
+config EXT_CONF_SUPPORT
+	bool
+	default n
+
+config CBB
+	hex
+	default 0x0
+
+config CDB
+	hex
+	default 0x18
+
+config XIP_ROM_BASE
+	hex
+	default 0xfff80000
+
+config XIP_ROM_SIZE
+	hex
+	default 0x100000
+
+config HIGH_SCRATCH_MEMORY_SIZE
+	hex
+	# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
+	default 0xA1000
+
+endif